TWI788871B - Method of forming semiconductor device and method of performing physical deposition process - Google Patents

Abstract

A method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form an opening. A plasma deposition process is performed to form a seed layer in the opening, in which performing the plasma deposition process includes disposing the wafer below a magnet module and rotating the magnet module. The magnet module includes a carrier structure, a placement plate and a magnet. A center of the carrier structure, a center of the placement plate and a center of the magnet form a triangle. A filling layer is formed on the seed layer.

Description

Method of forming semiconductor device and method of performing physical deposition process

The present disclosure relates to a method of forming a semiconductor device and a method of performing a physical deposition process.

Physical vapor deposition (PVD) is commonly used in the semiconductor industry, as well as in solar, glass coating, and other industries. PVD systems are used to deposit metal layers on substrates, such as semiconductor wafers, positioned in a vacuum plasma chamber. The PVD process is used to deposit target materials on semiconductor wafers. In some PVD systems, the target to be coated is placed in a vacuum chamber containing an inert gas such as argon.

According to some embodiments of the present disclosure, a method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form openings. performing a plasma deposition process to form a seed layer in the opening, wherein performing the plasma deposition process includes placing the wafer under a magnet module and rotating the magnet module, the magnet module including a carrier structure, a placement plate and a magnet, the carrier structure The center of the magnet, the center of the placement plate and the center of the magnet form a triangle. A filling layer is formed on the seed layer.

According to some embodiments of the present disclosure, a method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form openings. performing a plasma deposition process to form a seed layer in the opening, wherein performing the plasma deposition process includes rotating a magnet module on the wafer to control the plasma of the plasma deposition process, the magnet module has a radius of rotation, and the plasma The target for the deposition process has a diameter, and the ratio of the radius of rotation to the diameter is about 0.013 to about 0.038. A filling layer is formed on the seed layer.

According to some embodiments of the present disclosure, a method of performing a physical deposition process includes providing an enclosure baffle to define a chamber. A wafer pedestal is disposed in the chamber, the wafer pedestal configured to support the wafer. The magnet module is set on the wafer base platform, and the magnet module includes a carrier structure and a magnet. The target is set under the carrier structure, wherein the target includes a first area and a second area, and the first area is closer to a center of the target than the second area. The distance between the center of the carrier structure and the center of the magnet is determined according to the variation of the erosion depth between the first area and the second area of the target.

A plurality of implementations of the present disclosure will be disclosed in the following diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary, and thus should not be used to limit the present disclosure. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings. In addition, for the convenience of readers, the size of each element in the drawings is not drawn according to actual scale.

It should be understood that relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as shown in the drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "below" can encompass both an orientation of "below" and "upper," depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

In addition, "about", "approximately", "approximately" or "substantially" used herein generally means that the error or range of the value is within 20%, preferably within 10%. , preferably within 5%. Unless expressly stated in the text, the numerical values mentioned are regarded as approximate values, that is to say, there are errors or ranges indicated by "about", "approximately", "substantially" or "substantially".

FIG. 1 shows a schematic diagram of a processing apparatus 100 according to some embodiments of the present disclosure. See Figure 1. The processing equipment 100 can be configured to perform a deposition process and an etching process. The processing equipment 100 includes an enclosure baffle 102, a chamber 104, a collimator 110, a wafer susceptor table 120, a power supply 130, a power supply 132, a power supply A supplier 134 and a magnet module 140 .

Enclosing baffle 102 is configured to form (define) chamber 104 . The chamber 104 includes an upper portion 104 a and a lower portion 104 b , wherein the upper portion 104 a and the lower portion 104 b can be separated by a collimator 110 . The collimator 110 can be installed between the wafer susceptor table 120 and the magnet module 140 . For example, the collimator 110 can be mounted on the enclosure baffle 102 via a plurality of fixing elements (such as screws). In some embodiments, the collimator 110 may include a plurality of channels, and the channels may have a hexagonal cross-sectional configuration. For example, the channels of the collimator 110 may collectively form a honeycomb profile such that atoms or molecules entering the channels have a lower likelihood of sticking to the corners of the channels to extend the lifetime of the collimator 110 . In some other implementations, the channels of the collimator 110 may also have cross-sectional configurations of other shapes, such as triangles, squares, rectangles, other shapes that can form honeycombs, or combinations thereof.

The wafer susceptor table 120 may be configured to support a wafer W. As shown in FIG. In other words, the wafer W is disposed in the lower portion 104 b of the chamber 104 . In some embodiments, the wafer susceptor table 120 may be an electrostatic chuck. For example, Coulomb force or Johnsen-Rahbek force can be generated by applying voltage to the wafer pedestal 120 to fix the wafer W on the wafer pedestal 120 . In some other embodiments, the wafer pedestal 120 can have chuck pins, which can be positioned on the edge of the wafer W to ensure that the wafer W is fixed on the wafer pedestal 120. . In some embodiments, the wafer susceptor table 120 may incorporate a temperature control and maintenance system, the aforementioned system allowing the temperature of the wafer W to be controlled. For example, wafer susceptor stage 120 may be used to cool wafer W while chamber 104 is being heated and plasma P is generated therein. Adjusting the temperature of the wafer W can improve the properties of the deposited material layers in the wafer W and increase the deposition rate.

The power supply 130 , the power supply 132 and the power supply 134 are disposed in the processing equipment 100 to generate and control the plasma P in the chamber 104 , and guide sputtering, etching or re-etching according to requirements. In detail, the power supply 130 may be a direct current (DC) power supply, and the power supply 130 is electrically coupled to the magnet module 140 (eg, the carrier structure 142 ) to provide the carrier structure 142 with DC power. The power supply 132 may be a radio frequency alternating current power supply, and the power supply 132 is electrically coupled to the wafer susceptor table 120 . The power supply 134 can be a power supply of radio frequency alternating current, and the power supply 134 can be electrically coupled to the electrode plate 160 in the chamber 104 to generate and control the plasma P. In some embodiments, the power supply 134 can be electrically coupled to the electromagnetic coil 150 to generate an electromagnetic field to guide ions in the chamber 104 . The electromagnetic coil 150 is located outside the enclosure baffle 102 . In some embodiments, in addition to the power supply 130 , another RF AC power supply can also be electrically coupled to the magnet module 140 . In some embodiments, the power (eg, DC power) applied by the power supply 130 to the carrier structure 142 is about 20 kW or greater. In some embodiments, the power (eg, RF power) applied by the power supply 132 to the wafer susceptor stage 120 is about 500W or greater. In some embodiments, the radio frequency of the power supply 132 is greater than the radio frequency of the power supply 134 . For example, the radio frequency of the power supply 132 is about 10 MHz to about 15 MHz (eg, about 13.5 MHz), and the radio frequency of the power supply 134 is about 1 MHz to about 5 MHz (eg, about 2 MHz).

In some embodiments of the present disclosure, the plasma P can be generated in the processing apparatus 100 by introducing a plasma feed gas, such as argon (Ar), into the chamber 104 . Electrons provided by power supply 130 , power supply 132 , and power supply 134 collide with atoms of the plasma feed gas to generate ions (eg, copper ions). The negative bias voltage applied by the power supply 130 can attract ions toward the target T. The ions collide with the target T with high energy. In other words, the negative bias voltage applied by the power supply 130 accelerates the cations of the plasma P toward the target T to sputter atoms from the target T. Referring to FIG. The sputtered atoms are transferred from the surface of the target T by direct momentum transfer. The sputtered atoms may or may not be ionized, and a subset of the sputtered atoms is deposited onto the wafer W.

The magnet module 140 is disposed on the upper portion 104 a of the chamber 104 , and the magnet module 140 may include a carrier structure 142 and a magnet (magnetron) 144 . The carrier structure 142 is configured to support a target T, and can ensure that the target T is fixed on the carrier structure 142 during the deposition process. The target T is a material layer and is formed on the wafer W in a subsequent deposition process. The target T may be a conductive material and reacts with the gas in the chamber 104 to form a deposited metal layer. For example, the target T may comprise a metal or an alloy material, wherein the metal may be, for example, titanium (Ti), aluminum (Al), tantalum (Ta), copper (Cu), manganese (Mn) or other appropriate metal materials, The alloy may be, for example, a copper-manganese (Cu—Mn) alloy or other suitable alloy material. A magnet 144 may be disposed on the carrier structure 142 to generate a magnetic field in the chamber 104 . In detail, the magnet 144 can be fixed on the carrier structure 142 through a magnet holder. The magnet 144 and the target T are respectively disposed on opposite sides of the carrier structure 142 . The magnet 144 can provide the chamber 104 with a magnetic field, which can increase the residence time of the electrons by spiraling the electrons through the plasma P. By changing the shape of the magnetic field of the magnet 144, the plasma P can be controlled directionally. Therefore, the degree of ionization of the plasma gas can be increased. In some embodiments, the magnet 144 can control the uniformity of the plasma P (especially the uniformity of the plasma P near the wafer W) by providing RF or DC bias. Also, since wafer W is typically a circular wafer, concentric electromagnetic coils can be used. More about the structure of the magnet module 140 will be discussed in detail in the relevant paragraphs of FIG. 2 .

In some embodiments, the processing apparatus 100 further includes a shielding plate 170 disposed on the upper portion 104 a of the chamber 104 . The shielding plate 170 can be disposed between the carrier structure 142 and the collimator 110 . In detail, the shielding plate 170 is disposed between the target T and the wafer W to prevent ions (such as copper ions) from depositing on the wafer base 120 during the process and contaminating the wafer W.

FIG. 2 illustrates the magnet module 140 of the processing apparatus 100 according to some embodiments of the present disclosure. As shown in FIGS. 1 and 2 , the magnet module 140 includes a carrier structure 142 , a magnet 144 and a placement tray 146 . The carrier structure 142 , the magnet 144 and the placement plate 146 may all have a circular profile when viewed from above (top view). The placement tray 146 may be located at the edge of the carrier structure 142 and the magnet 144 is located at the edge of the placement tray 146 . In other words, the placement plate 146 can be regarded as a magnet holding device of the magnet module, and is used to fix the magnet 144 on the carrier structure 142 . In some embodiments, the magnet 144 is located on the edge of the placement plate 146 and the carrier structure 142, and in FIG. The edge of 144 is substantially tangent to point A1. In some embodiments, point A and point A1 are located at different locations. For example, point A and point A1 are located at two different points on the circumference of the placement tray 146 . In some embodiments, the point A overlaps with the point A1 , for example, when the angle θ2 between the distance L1 and the distance L2 is substantially zero.

The carrier structure 142 has a center M1. In some embodiments, the center of the target T also overlaps the center M1 of the carrier structure 142 . The placement tray 146 has a center M2. The center M1 of the carrier structure 142 does not overlap with the center M2 of the placement tray 146 and is separated by a distance L1 . In some embodiments, the distance L1 is constant, that is, the placement tray 146 can be fixed off-axis on the carrier structure 142 , but the placement tray 146 can rotate along the center M1 of the carrier structure 142 with a radius of rotation equal to the distance L1 .

In addition, the magnet 144 has a center M. As shown in FIG. The center M2 of the placement plate 146 does not overlap with the center M of the magnet 144 and is separated by a distance L2. In some embodiments, the distance L2 is constant, that is, the magnet 144 can be fixed on the placement disk 146 off-axis, but the magnet 144 can rotate along the center M2 of the placement disk 146, and the radius of rotation is the distance L2, so as to change the position of the magnet 144. The relative position between the center M of and the center M1 of the carrier structure 142 .

In some embodiments, the center M1 of the carrier structure 142, the center M2 of the placement plate 146, and the center M of the magnet 144 are not located on the same straight line. In other words, the line segment connecting the center M1 of the carrier structure 142 , the center M2 of the placement tray 146 and the center M of the magnet 144 is not a straight line, for example, a triangle may be formed. In some embodiments, the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement tray 146 is substantially greater than the distance L2 between the center M2 of the placement tray 146 and the center M of the magnet 144 . In some embodiments, the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement tray 146 and the distance L2 between the center M2 of the placement tray 146 and the center M of the magnet 144 are both constant. For example, distance L1 is about 4 inches to about 5 inches, and distance L2 is about 2 inches to about 3 inches.

In some embodiments, the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement tray 146 has an included angle θ1 with a reference line, and an included angle θ2 between the distance L1 and the distance L2 (that is, by the center M1, The exterior angle of the angle M2 of the triangle formed by M2 and M). In some embodiments, the included angle θ2 is substantially greater than the included angle θ1. In some embodiments of the present disclosure, by adjusting the relative positions of the center M1 of the carrier structure 142 , the center M2 of the placement plate 146 , and the center M of the magnet 144 , the included angle θ2 can be an acute angle (greater than 0 degrees). When the included angle θ2 is an acute angle, the distribution of the plasma P is changed, so that the degree of erosion (erosion) of each area of the target T by the plasma P is relatively uniform, so as to improve the uniformity of the erosion of the target T, thereby prolonging the target T. T's lifetime. In some embodiments, the included angle θ2 ranges from about 70 degrees to about 80 degrees. For example, the included angle θ2 may be about 75 degrees. If the included angle θ2 is less than about 70 degrees or greater than about 80 degrees, it will cause the plasma P to be too concentrated in some areas of the target T, resulting in poor erosion uniformity of the target T, for example, a certain area of the target T is covered by the plasma. The degree of P erosion is too fast, and the target T is etched through early. Furthermore, a large number of metal particles will be produced in the area eroded too quickly by the plasma P, and these metal particles may cause some channels of the collimator 110 to block early.

In some embodiments, by adjusting the relative positions of the center M1 of the carrier structure 142, the center M2 of the placement plate 146, and the center M of the magnet 144, the distance between the center M1 of the carrier structure 142 and the center M of the magnet 144 can be changed (increased). The distance r between them can be regarded as the rotation radius of the magnet 144 . In other words, as the included angle θ2 decreases from 180 degrees to an acute angle, the distance r (that is, the rotation radius of the magnet 144 ) can be increased. That is, during the deposition process, the included angle θ2 is a constant value (that is, the relative position between the placement disk 146 and the magnet 144 does not change), and the included angle θ2 is an acute angle, and the placement disk 146 drives the magnet 144 along the center of the carrier structure 142 M1 rotates (that is, the angle θ1 changes). Such setting can improve the erosion uniformity of the target T, so as to prevent or avoid some areas of the target T from being corroded early, thereby improving the service life of the target T, and increasing the utilization rate of other areas of the target T (such as increase by about 5%). Furthermore, the time for metal particles to block the channel of the collimator 110 can be slowed down.

In some embodiments, the radius of rotation r of the magnet 144 may range from about 2.455 inches to about 6.689 inches. If the radius of rotation r is less than 2.455 inches, the target T will be etched through early and the erosion uniformity of the target T will be poor; if the radius of rotation r is greater than 6.689 inches, it may be impossible to control the position where the plasma P interacts with the target T , and cannot effectively improve the uniformity of target T erosion.

In addition, the target material T has a width (or diameter) D. In some embodiments, the radius of rotation r is less than half the width D (ie, less than D/2). For example, the ratio (r/D) of the radius of rotation r to the width D is about 0.013 to about 0.038. If the ratio r/D falls within the above range, a target erosion distribution similar to curve C2 in Figure 3B can be obtained; if the ratio r/D falls outside the above range, it is possible to obtain a curve C1 similar to Figure 3A The target erosion distribution is shown.

FIG. 3A and FIG. 3B are schematic diagrams showing the relationship between the erosion depth of the target and the radius of the target according to some embodiments of the present disclosure. Refer to Figure 1, Figure 2, Figure 3A and Figure 3B together. When the center M1 of the carrier structure 142, the center M2 of the placement disc 146, and the center M of the magnet 144 are in a straight line (such as the center M is located between the centers M1 and M2), the center M1 of the carrier structure 142 and the center M2 of the placement disc 146 The distance L1 between them and the included angle θ2 of the distance L2 between the center M2 of the placement disk 146 and the center M of the magnet 144 is 180 degrees, as shown in the curve C1 of Figure 3A (it uses about 3500 kWh for the target material T (kWh)), the erosion depth of the target T in each zone has a significant gap (for example, the gap is between about 2.36 inches to 5.5 inches (from about 60 mm to about 140 mm) range), which will lead to The erosion of the target T is non-uniform, and when the regions 1 and 3 of the target T still have a usable thickness, the region 2 of the target T may be etched through early. However, when the included angle θ2 between the distance L1 between the center M1 of the carrier structure 142 and the center M2 of the placement tray 146 and the distance L2 between the center M2 of the placement tray 146 and the center M of the magnet 144 is an acute angle, as shown in FIG. 3B As shown in the curve C2 of the target T (after using about 4000 kWh for the target T), compared with the curve C1 of Figure 3A, the erosion depth of the target T in area 3 increases, while the erosion depth of area 1 and area 2 Slow down, so the erosion depth of the target T in each zone can be relatively uniform. That is, the distance r between the center M1 of the carrier structure 142 and the center M of the magnet 144 is determined by the erosion depth of each region of the target T (eg, region 1 , region 2 and/or region 3 ). In this way, the target material T can achieve higher usage efficiency, and the service life of the target material T can be extended. For example, the service life of the target T shown by the curve C1 in FIG. 3A is about 4300 kWh, while the service life of the target T shown by the curve C2 in FIG. 3B can be increased to about 4600 kWh.

In addition, as shown by the curve C1 in Fig. 3A, since the erosion depth of the target T in the region 2 is relatively large, more metal particles are generated under the region 2 of the target T, and these excessive metal particles may block the target material early. The partial channels of the opposite regions of the collimator 110 make the distribution of the metal particles passing through the collimator 110 uneven. On the contrary, as shown in the curve C2 of FIG. 3B, because the erosion depth of the target material T in the region 1, region 2 and region 3 is similar, the uniformity of the metal particles produced in each region is similar, so the collimator 110 can be slowed down. The situation where the channels in each zone are blocked unevenly.

The above-mentioned deposition method can be applied to semiconductor manufacturing process. 4 to 9 illustrate semiconductor devices in different stages of some embodiments of the present disclosure. As shown in FIG. 4 , a dielectric layer 210 is formed on the wafer 200 . It should be understood that the wafer 200 in FIGS. 4 to 9 can be regarded as the wafer W in FIG. 1 , which will be described first. In some embodiments, wafer 200 may include a substrate underlying dielectric layer 210 and may include active layers such as doped silicon, undoped silicon, or a silicon-on-insulator (SOI) substrate. In some embodiments, the SOI substrate includes a layer of semiconductor material (eg, a layer of silicon material) formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on the substrate, and may be a silicon or glass substrate. In some embodiments, other substrates, such as multilayer or gradient substrates, may also be used.

In some embodiments, circuitry is formed on a substrate, and may be of a certain type suitable for a particular application. In some embodiments, the circuit includes electronic components formed on a substrate with one or more dielectric layers overlying the electronic components. Metal layers may be formed between overlying dielectric layers to route electrical signals between electronic components. Electronic components may also be formed in one or more dielectric layers. For example, the circuit may include various N-type metal-oxide-semiconductor (NMOS) and/or P-type metal-oxide-semiconductor (PMOS) elements, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc. interconnected to Perform one or more functions. Functions may include memory structures, processing structures, sensors, amplifiers, power dividers, input/output circuits, and the like. It should be understood that the above examples are only for illustration to further explain the application of some implementations of the present disclosure, rather than limiting some implementations of the present disclosure.

The dielectric layer 210 may include low-k dielectric materials (materials with a lower dielectric constant than silicon dioxide), such as silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphorous Silicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, SiOxCyHz, spin-on-glass, spin-on-polymer, silicon-carbon material, the above compounds, the above composite materials, or other suitable materials. In some embodiments, the dielectric layer 210 may include a very low dielectric material, such as a dielectric layer material with a dielectric constant less than about 2.9 (eg, a K value between about 2.5 and 2.6). In some embodiments, the method of forming the dielectric layer 210 may include performing chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or other suitable deposition methods.

See Figure 5. An etching process is performed on the dielectric layer 210 to form the opening 220 . Opening 220 may expose wafer 200 . The etching process can use dry etching or wet etching. When dry etching is used, the process gas may include carbon tetrafluoride (CF ₄ ), trifluoromethane (CHF ₃ ), nitrogen trifluoride (NF ₃ ), sulfur hexafluoride (SF ₆ ), bromine (Br ₂ ), hydrogen bromide (HBr), chlorine (Cl ₂ ) or any combination of the above. A rarefied gas such as nitrogen (N ₂ ), oxygen (O ₂ ), or argon (Ar) may optionally be used. When wet etching is used, the etchant may include ammonium hydroxide:hydrogen peroxide:water (NH ₄ OH:H ₂ O ₂ :H 2 O) (also known as APM), hydroxylamine (NH ₂ OH), potassium hydroxide (KOH ), nitric acid:ammonium fluoride:water (HNO ₃ :NH ₄ F:H ₂ O) and/or other suitable etchant.

See Figure 6. In some embodiments, a degassing process may be performed on the structure of FIG. 5 to remove residues on the surface of the wafer 200, such as moisture (H ₂ O), organic matter, or other residues. For example, the degassing process can remove moisture from the surface of the wafer 200 by heating to a high temperature (eg, 150°C to 500°C).

After performing the degassing process, the native oxide on the surface of the wafer 200 can be removed. In some embodiments, hydrogen ions may be provided to the surface of the wafer 200 such that the hydrogen ions react with the native oxide to remove the native oxide.

Next, a first barrier layer 230 is conformally formed in the opening 220 of the dielectric layer 210 . In some embodiments, the first barrier layer 230 can be a metal layer including tantalum (Ta), cobalt (Co), titanium (Ti), or a nitride of the above metals (such as tantalum nitride (TaN) or titanium nitride (TiN)). In some embodiments, the method of forming the first barrier layer 230 may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods.

Next, a second barrier layer 240 is conformally formed on the first barrier layer 230 . The second barrier layer 240 may include tantalum (Ta), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), combinations thereof, or other suitable Material. In some embodiments, the method of forming the second barrier layer 240 may include physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition methods. In some embodiments, the first barrier layer 230 and the second barrier layer 240 are formed by the same deposition method, such as physical vapor deposition. In some embodiments, the first barrier layer 230 and the second barrier layer 240 are made of different materials. For example, the first barrier layer 230 is made of tantalum nitride (TaN), and the second barrier layer 240 is made of tantalum (Ta).

Please also refer to Figure 1, Figure 2, Figure 3B and Figure 7. After the first barrier layer 230 and the second barrier layer 240 are formed, a seed layer 250 is conformally formed on the second barrier layer 240 . In some embodiments of the present disclosure, the processing apparatus 100 of FIG. 1 may be used to form the seed layer 250 on the wafer 200 (wafer W). Due to the configuration of the magnet module 140 (that is, the angle θ2 between the distance L1 and the distance L2 is an acute angle), the target T can have a relatively uniform erosion profile, so the service life of the target T can be improved. In this way, the uniformity of the seed layer 250 can be improved. In some embodiments, the seed layer 250 may be a metal layer including titanium (Ti), aluminum (Al), tantalum (Ta), copper (Cu), manganese (Mn), or other suitable metal materials. In some embodiments, the seed layer 250 may be a metal alloy, such as copper-manganese (Cu—Mn) alloy or other suitable alloy materials. In some embodiments, the method of forming the seed layer 250 may use the processing equipment 100 of FIG. 1 and form it on the wafer W (wafer 200 ) by performing physical vapor deposition (PVD).

See Figure 8. After the seed layer 250 is formed, a conductive material is filled into the opening 220 of the dielectric layer 210 to form the filling layer 260 . In some embodiments, fill layer 260 includes metal, elemental metal, transition metal, or other suitable conductive material. For example, the fill layer can be copper.

See Figure 9. After the filling layer 260 is formed, a planarization process is performed to remove the first barrier layer 230 , the second barrier layer 240 , the seed layer 250 and the filling layer 260 outside the opening 220 . In some embodiments, the planarization process is a chemical-mechanical polishing (CMP) process. In some embodiments, the dielectric layer 210 , the first barrier layer 230 , the second barrier layer 240 , the seed layer 250 are coplanar with the top surface of the filling layer 260 . In this way, an interconnect structure including the dielectric layer 210, the first barrier layer 230, the second barrier layer 240, the seed layer 250 and the filling layer 260, and conductive lines can be formed on the wafer 200. or conduction through the structure.

FIG. 10 shows a schematic plan view of a cluster tool 300 according to some embodiments of the present disclosure. As shown in FIG. 10 , the processing station 300 includes a central transfer chamber 310 , a processing chamber 320 , a processing chamber 330 , a processing chamber 340 and a processing chamber 350 .

The central transport chamber 310 includes a central transport mechanism 312 capable of physically transporting wafers (such as the wafer W in FIG. 1 or the wafer 200 in FIGS. 4 to 9 ). The central transfer chamber 310 is connected to the process chambers 320 to 350 and a load lock 360a and a load lock 360b. This configuration allows the central transfer chamber 310 to transfer at least one wafer between the processing chambers 320 to 350 and the wafer carrier transfer chambers 360a and 360b. In some embodiments, multiple wafers may be transported in processing station 300 .

The processing chambers 320 to 350 may be configured to perform fabrication steps on a wafer. Wafer fabrication steps may include deposition process, etching process, heat treatment, cleaning process, planarization process and/or testing process. The deposition process may include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), electrochemical deposition (ECD), atomic layer deposition (ALD) and/or other suitable deposition process. The etching process may include dry etching, wet etching, ion beam etching, lithography, ion deposition, or other suitable etching processes. Heat treatment may include annealing, thermal oxidation, or other suitable heat treatments. The cleaning process may include rinsing, plasma ashing, or other suitable cleaning processes. In some embodiments, the processing chambers 320 to 350 can respectively perform different processes, which will be described in detail in the following paragraphs.

In some embodiments, the processing chamber 320 may be configured to perform a wafer degas process. In some embodiments, the semiconductor device can be put into the processing chamber 320 in the step of _FIG . , or other residues. For example, the degassing process can remove moisture from the surface of the wafer by heating to a high temperature (eg, 150°C to 500°C).

The processing chamber 330 may be configured to remove native oxide on the wafer to expose conductive features within the wafer. In some embodiments, in the step of FIG. 6 , the semiconductor device can be placed into the processing chamber 330 , and hydrogen ions are passed through, so that the hydrogen ions react with the native oxide to remove the native oxide.

The processing chamber 340 may be configured to form a barrier layer on the wafer. In some embodiments, the semiconductor device can be put into the processing chamber 340 in the step of FIG. 6 , and the opening 220 on the wafer 200 conformally forms the first barrier layer 230 and the second barrier layer 240 .

The processing chamber 350 may be configured to form a seed layer on the wafer. In some embodiments, the semiconductor device can be put into the processing chamber 350 in the step of FIG. 7 , and the seed layer 250 is conformally formed on the first barrier layer 230 and the second barrier layer 240 . In some embodiments, the processing chamber 350 may be considered the processing apparatus 100 .

In some embodiments, the processing station 300 may include an equipment front end module (EFEM) 370 . The central transfer chamber 310 is connected to the front-end module 370 of the equipment through the load lock chambers 360a and 360b. Wafers may be inserted into the load lock chamber 360 a and then into the processing chambers 320 - 350 . The wafer load transfer chamber 360a can generate a gas environment compatible with the equipment front-end module 370 or the central transfer chamber 310 according to the next position or step of the loaded wafer. For example, the gas content of wafer load lock chamber 360a may be varied by mechanisms such as adding pure gas, creating a vacuum, and/or other mechanisms for regulating load lock chamber 360a.

The front-end module 370 of the equipment can provide a closed environment, so that the wafer (the wafer W in FIG. 1 or the wafer 200 in FIGS. 4 to 9 ) can enter or take out the processing station 300 from the closed environment. . The front end module 370 includes a load lock mechanism 372 that performs the physical transfer of the wafer. Wafers may enter processing station 300 through a load port in transport carrier 380 . In some embodiments, the transport carrier 380 is configured to accommodate wafers. The transport carrier 380 is hermetically sealed to provide a micro-environment for the wafers to avoid contamination.

In some embodiments, the structure in FIG. 5 (hereinafter referred to as the wafer) can be placed on the transport carrier 380 first, and then enter the wafer carrier transfer chamber 360 a from the equipment front-end module 370 . After the wafer loading transfer chamber 360 a is evacuated, the wafer enters the central transfer chamber 310 and is sent into the processing chamber 320 by the central transfer mechanism 312 for degassing process. Next, the wafer is transported by the central transport mechanism 312 and then enters the processing chamber 330 for a process of removing native oxide. Then, the wafer is transported by the central transport mechanism 312 and enters the processing chamber 340 for the process of forming the first barrier layer 230 and the second barrier layer 240 . Afterwards, the wafer is transported by the central transport mechanism 312 and then enters the processing chamber 350 to form the seed layer 250 . The processing equipment 100 in FIG. 1 can be placed in the processing chamber 350 , and the included angle θ2 of the magnet module can be adjusted in the processing chamber 350 (as shown in FIG. 2 ).

To sum up, since the processing equipment of some embodiments of the present disclosure has a magnet module, the distance between the center of the carrier structure of the magnet module and the center of the placement disk and the distance between the center of the placement disk and the center of the magnet The angle between them is an acute angle, which can improve the uniformity of target erosion, thereby increasing the service life of the target.

According to some embodiments of the present disclosure, a method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form openings. performing a plasma deposition process to form a seed layer in the opening, wherein performing the plasma deposition process includes placing the wafer under a magnet module and rotating the magnet module, the magnet module including a carrier structure, a placement plate and a magnet, the carrier structure The center of the magnet, the center of the placement plate and the center of the magnet form a triangle. A filling layer is formed on the seed layer.

In some embodiments, the center of the placement disc has an outer angle in a triangle formed by the center of the carrier structure, the center of the placement disc and the center of the magnet, and the outer corner is an acute angle. In some embodiments, the outer angle ranges from 70 degrees to 80 degrees. In some embodiments, the seed layer includes a copper-manganese alloy.

According to some embodiments of the present disclosure, a method of forming a semiconductor device includes forming a dielectric layer on a wafer. The dielectric layer is etched to form openings. performing a plasma deposition process to form a seed layer in the opening, wherein performing the plasma deposition process includes rotating a magnet module on the wafer to control the plasma of the plasma deposition process, the magnet module has a radius of rotation, and the plasma The target for the deposition process has a diameter, and the ratio of the radius of rotation to the diameter is about 0.013 to about 0.0378. A filling layer is formed on the seed layer.

In some embodiments, the magnet module includes a carrier structure, a placement plate placed on the carrier structure, and a magnet placed on the placement plate. In a top view, the center of the carrier structure, the center of the placement plate, and the center of the magnet are not in a straight line . In some embodiments, the target and the magnet are located on opposite sides of the carrier structure.

According to some embodiments of the present disclosure, a method of performing a physical deposition process includes providing an enclosure baffle to define a chamber. A wafer pedestal is disposed in the chamber, the wafer pedestal configured to support the wafer. The magnet module is set on the wafer base platform, and the magnet module includes a carrier structure and a magnet. The target is set under the carrier structure, wherein the target includes a first area and a second area, and the first area is closer to a center of the target than the second area. The distance between the center of the carrier structure and the center of the magnet is determined according to the variation of the erosion depth between the first area and the second area of the target.

In some embodiments, the distance is from about 2.455 inches to about 6.689 inches. In some embodiments, the distance between the center of the support structure and the center of the magnet is determined such that the erosion depth of the first region of the target is slowed and the erosion depth of the second region of the target is increased.

Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.

100: Processing equipment 102: enclosed baffle 104: chamber 110: collimator 104a: upper part 104b: lower part 120: Wafer base platform 130: Power supply 132: Power supply 134: Power supply 140:Magnet module 142: Carrier structure 144: magnet 146: place plate 150: electromagnetic coil 160: electrode plate 170: shielding board 200: Wafer 210: dielectric layer 220: opening 230: The first barrier layer 240: Second barrier layer 250: seed layer 260: filling layer 300: processing station 310: Central transfer chamber 312: Central conveying mechanism 320: processing chamber 330: processing chamber 340: processing chamber 350: processing chamber 360a: Wafer loading transfer room 360b: Wafer loading transfer room 370:Equipment front-end module 372:Load Lock Mechanism 380: transport carrier 1: area 2: area 3: area A: point A1: point D: width L1: distance L2: Distance M: center M1: center M2: center (corner) P: Plasma r: distance (radius of rotation) T: Target W: Wafer θ1: included angle θ2: included angle

The detailed description of the embodiments of the disclosed invention will be fully understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Similar features are denoted by the same reference numerals in the description and drawings. Figure 1 shows a schematic diagram of a processing facility according to some embodiments of the present disclosure. FIG. 2 illustrates a magnet module of a processing device according to some embodiments of the present disclosure. Figures 3A and 3B illustrate the relationship between the erosion depth of the target and the radius of the target according to some embodiments of the present disclosure. 4 to 9 illustrate semiconductor devices in different stages of some embodiments of the present disclosure. Figure 10 depicts a schematic plan view of a cluster tool according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

140:Magnet module 142: Carrier structure 144: magnet 146: place plate A: point A1: point L1: distance L2: Distance M: Center M1: center M2: center (corner) r: distance (radius of rotation) θ1: included angle θ2: included angle

Claims (10)

A method of forming a semiconductor device, comprising: forming a dielectric layer on a wafer; etching the dielectric layer to form an opening; performing a plasma deposition process to form a seed layer in the opening, wherein Performing the plasma deposition process includes placing the wafer under a magnet module and rotating the magnet module, the magnet module including a carrier structure, a placement plate and a magnet, a center of the carrier structure, the placement A center of the disk and a center of the magnet form a triangle, the triangle has an outer angle, and the outer angle is an acute angle; and a filling layer is formed on the seed layer. The method of claim 1, wherein the distance between the center of the carrier structure and the center of the placement tray is substantially greater than the distance between the center of the placement tray and the center of the magnet. The method according to claim 2, wherein the outer angle ranges from 70 degrees to 80 degrees. The method according to claim 1, wherein the seed layer comprises copper-manganese alloy. A method of forming a semiconductor device, comprising: forming a dielectric layer on a wafer; etching the dielectric layer to form an opening; performing a plasma deposition process to form a seed layer in the opening, wherein performing the plasma deposition process includes rotating a magnet module on the wafer to control the electrical The plasma of the plasma deposition process, the magnet module has a radius of rotation, and a target of the plasma deposition process has a diameter, the ratio of the radius of rotation to the diameter is about 0.013 to about 0.038, the magnet module Comprising a carrier structure, a placement plate placed on the carrier structure and a magnet placed on the placement plate, the target and the magnet are respectively located on opposite sides of the carrier structure; and a filling layer is formed on the seed layer superior. The method as claimed in claim 5, wherein in the top view, a center of the carrier structure, a center of the placement plate, and a center of the magnet are not in a straight line. The method according to claim 6, wherein the radius of rotation is less than half of the diameter of the target. A method of performing a physical deposition process, comprising: providing an enclosure to define a chamber; providing a wafer pedestal in the chamber, the wafer pedestal configured to support a wafer; a magnet module on the wafer base platform, the magnet module includes a carrier structure and a magnet; disposing a target under the carrier structure, wherein the target comprises a first area and a second area, the first area being closer to a center of the target than the second area; and according to the target according to the first area and a second area The variation in etch depth of the first zone and the second zone determines a distance between a center of the support structure and a center of the magnet, the distance being from about 2.455 inches to about 6.689 inches. The method of claim 8, wherein the carrier structure and the magnet both have a circular profile when viewed from above. The method as claimed in claim 8, wherein the distance between the center of the carrier structure and the center of the magnet is determined such that the erosion depth of the first region of the target slows down and the second region of the target The erosion depth increases.

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