TWI788542B - Lead frame material, manufacturing method thereof, and semiconductor package using the lead frame material - Google Patents
Lead frame material, manufacturing method thereof, and semiconductor package using the lead frame material Download PDFInfo
- Publication number
- TWI788542B TWI788542B TW108109707A TW108109707A TWI788542B TW I788542 B TWI788542 B TW I788542B TW 108109707 A TW108109707 A TW 108109707A TW 108109707 A TW108109707 A TW 108109707A TW I788542 B TWI788542 B TW I788542B
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- frame material
- layer
- roughened layer
- grain boundaries
- Prior art date
Links
Images
Classifications
-
- H10W70/457—
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/615—Microstructure of the layers, e.g. mixed structure
- C25D5/617—Crystalline layers
-
- C—CHEMISTRY; METALLURGY
- C05—FERTILISERS; MANUFACTURE THEREOF
- C05D—INORGANIC FERTILISERS NOT COVERED BY SUBCLASSES C05B, C05C; FERTILISERS PRODUCING CARBON DIOXIDE
- C05D7/00—Fertilisers producing carbon dioxide
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
- C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/60—Electroplating characterised by the structure or texture of the layers
- C25D5/605—Surface topography of the layers, e.g. rough, dendritic or nodular layers
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
-
- H10W70/421—
-
- H10W72/00—
-
- H10W74/00—
Landscapes
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Organic Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本發明的引線框架材料,其具有導電性基體與形成在前述導電性基體的至少單面上之粗化層,在前述引線框架材料的剖面作觀察,平行於前述導電性基體的表面而在預定長度內作測定所獲得之存在於前述粗化層的表面中的晶界數量為20個/微米以下。本發明的引線框架材料,其即使在高溫高濕環境下經過長時間使用的情況下,樹脂密接性也優良。The lead frame material of the present invention has a conductive substrate and a roughened layer formed on at least one surface of the conductive substrate. When viewed in the cross-section of the aforementioned lead frame material, it is parallel to the surface of the aforementioned conductive substrate at a predetermined The number of grain boundaries existing in the surface of the aforementioned roughened layer measured within the length is 20 grain boundaries/micrometer or less. The lead frame material of the present invention is excellent in resin adhesion even after being used for a long period of time in a high-temperature, high-humidity environment.
Description
本發明關於一種引線框架材料及其製造方法、以及使用此引線框架材料之半導體封裝體。The invention relates to a lead frame material, a manufacturing method thereof, and a semiconductor package using the lead frame material.
在電子機器和電器設備中,組裝有大量的樹脂密封型半導體裝置。樹脂密封型半導體裝置是將藉由導線等而彼此電性連接之半導體元件與引線框架材料利用模塑樹脂加以密封而成。在這種樹脂密封型半導體裝置中,為了對引線框架材料賦予接合性、耐熱性、密封性等功能,大多施加有金(Au)、銀(Ag)、錫(Sn)等外裝鍍層。In electronic equipment and electric equipment, a large number of resin-sealed semiconductor devices are assembled. Resin-encapsulated semiconductor devices are formed by sealing semiconductor elements and lead frame materials that are electrically connected to each other by wires and the like with molding resin. In such resin-sealed semiconductor devices, exterior plating such as gold (Au), silver (Ag), and tin (Sn) is often applied to the lead frame material in order to impart functions such as bondability, heat resistance, and sealing.
近年來,為了簡化組裝步驟以及降低成本,使用一種引線框架材料(預鍍框架(Pre-Plated Frame),以下縮寫為PPF),其針對藉由焊料等來實行將半導體裝置構裝於印刷基板上,預先對引線框架材料的表面,施行可提高與焊料之間的潤濕性的作法的鍍覆(例如,施行Ni/Pd/Au鍍覆)(例如,參照專利文獻1)。In recent years, in order to simplify assembly steps and reduce costs, a lead frame material (pre-plated frame (Pre-Plated Frame), hereinafter abbreviated as PPF) has been used, which is aimed at mounting semiconductor devices on printed substrates with solder or the like. , the surface of the lead frame material is preliminarily plated to improve wettability with solder (for example, Ni/Pd/Au plating) (for example, refer to Patent Document 1).
另外,為了提高樹脂密封型半導體裝置中的引線框架材料與模塑樹脂之間的密接性,提出有一種將引線框架材料的鍍覆表面作粗化之技術(例如,參照專利文獻2、專利文獻3)。In addition, in order to improve the adhesion between the lead frame material and the molding resin in the resin-sealed semiconductor device, a technique of roughening the plated surface of the lead frame material has been proposed (for example, refer to Patent Document 2, Patent Document 3).
這些將鍍覆表面作粗化之技術,其藉由將引線框架材料的鍍覆表面作粗化,期待(1)增加引線框架材料與模塑樹脂之間的黏接面積的效果、(2)模塑樹脂成為容易咬合至粗化後的鍍膜表面的凹凸的效果(亦即,定錨效應(anchor effect))等。These techniques for roughening the plated surface are expected to (1) increase the bonding area between the lead frame material and the molding resin by roughening the plated surface of the lead frame material, (2) Molding resin becomes easy to catch to the unevenness effect (that is, the anchor effect (anchor effect)) of the plated film surface after roughening, etc.
藉此,成為可提升模塑樹脂對於引線框架材料的密接性,且可防止引線框架材料與模塑樹脂之間的剝離,並且可提升樹脂密封型半導體裝置的可靠度。 [先前技術文獻] (專利文獻)Thereby, the adhesiveness of the molding resin to the lead frame material can be improved, peeling between the lead frame material and the molding resin can be prevented, and the reliability of the resin-sealed semiconductor device can be improved. [Prior Art Literature] (patent literature)
專利文獻1:日本特許第2543619號公報 專利文獻2:日本特許第3228789號公報 專利文獻3:日本特開平第10-27873號公報Patent Document 1: Japanese Patent No. 2543619 Patent Document 2: Japanese Patent No. 3228789 Patent Document 3: Japanese Patent Application Laid-Open No. 10-27873
[發明所欲解決的問題] 藉由如上所述的鍍覆表面的粗化,引線框架材料的樹脂密接性相較於以往確實有所提升。然而,已知近年所要求的高可靠度的水準,例如,在溫度85℃且濕度85%的高溫高濕環境下進行168小時的曝露試驗後,會散見有引線框架材料與樹脂之間產生間隙的案例。這被認為是因為變成大量使用以往不太使用之四方平面無引腳封裝(Quad Flat Non-Leaded Package,QFN)型以及小外形封裝(Small Outline Package,SOP)型等封裝,於是對於密接性的要求水準變得更高。由此可知,在引線框架材料的樹脂密接性方面尚有改善空間。[Problem to be solved by the invention] Due to the roughening of the plating surface as described above, the resin adhesiveness of the lead frame material has definitely been improved compared to conventional ones. However, it is known that the high level of reliability required in recent years, for example, after a 168-hour exposure test in a high-temperature and high-humidity environment at a temperature of 85°C and a humidity of 85%, gaps may appear between the lead frame material and the resin. case. This is considered to be due to a large number of packages such as Quad Flat Non-Leaded Package (QFN) and Small Outline Package (SOP) that have not been used in the past have been widely used. The level of requirements has become higher. From this, it can be seen that there is room for improvement in the resin adhesion of the lead frame material.
本發明目的在於提供一種引線框架材料及其製造方法、以及使用此引線框架材料之半導體封裝體,該引線框架材料即使在高溫高濕環境下經過長時間使用的情況下,樹脂密接性也優良。An object of the present invention is to provide a lead frame material, a method of manufacturing the same, and a semiconductor package using the lead frame material, which are excellent in resin adhesion even after long-term use in a high-temperature and high-humidity environment.
[用以解決問題的技術手段] 本發明的主要構成如下。 [1]一種引線框架材料,其具有導電性基體與形成在前述導電性基體的至少單面上之粗化層,該引線框架材料的特徵在於:在前述引線框架材料的剖面作觀察,平行於前述導電性基體的表面而在預定長度內作測定所獲得之存在於前述粗化層的表面中的晶界數量為20個/微米(個/µm)以下。 [2]如上述[1]所述之引線框架材料,其中,在前述引線框架材料的剖面作觀察,前述粗化層的高度在0.1微米(µm)以上且5.0µm以下的範圍內。 [3]如上述[1]或[2]所述之引線框架材料,其中,前述引線框架材料的最外表面的比表面積為120%以上。 [4]如上述[1]~[3]中任一項所述之引線框架材料,其中,在前述引線框架材料的剖面作觀察,Σ5以下的共位晶界佔存在於前述粗化層中的前述粗化層的全部晶界的比率為90.0%以上。 [5]如上述[1]~[4]中任一項所述之引線框架材料,其中,前述導電性基體是由從銅、銅合金、鐵、鐵合金、鋁及鋁合金之群組中選出的金屬或合金所構成。 [6]如上述[1]~[5]中任一項所述之引線框架材料,其中,前述粗化層包含銅及鎳中的至少一種元素。 [7]如上述[1]~[6]中任一項所述之引線框架材料,其中,進一步具有一個以上的下述層:形成在前述粗化層上,具有與前述粗化層不同的組成,且包含從鎳、鈀、銠、釕、鉑、銥、金、銀及錫之群組中選出的一種以上的元素。 [8]一種引線框架材料的製造方法,其為上述[1]~[7]中任一項所述之引線框架材料的製造方法,該製造方法的特徵在於:前述粗化層藉由電鍍形成。 [9]一種半導體封裝體,其使用上述[1]~[7]中任一項所述之引線框架材料製成。[Technical means to solve the problem] The main constitution of the present invention is as follows. [1] A lead frame material having a conductive substrate and a roughened layer formed on at least one surface of the conductive substrate, the lead frame material is characterized in that, when viewed in a section of the aforementioned lead frame material, parallel to The number of grain boundaries present on the surface of the roughened layer measured over a predetermined length of the surface of the conductive substrate is 20 grain boundaries/micrometer (pieces/µm) or less. [2] The lead frame material according to the above [1], wherein the height of the roughened layer is in the range of 0.1 micrometer (µm) to 5.0 µm when viewed in a cross section of the lead frame material. [3] The lead frame material according to the above [1] or [2], wherein the specific surface area of the outermost surface of the lead frame material is 120% or more. [4] The lead frame material according to any one of the above [1] to [3], wherein when observed in a cross section of the lead frame material, colocated grain boundaries below Σ5 are present in the roughened layer. The ratio of all grain boundaries in the roughened layer is 90.0% or more. [5] The lead frame material according to any one of [1] to [4] above, wherein the conductive substrate is selected from the group consisting of copper, copper alloy, iron, iron alloy, aluminum, and aluminum alloy. composed of metals or alloys. [6] The lead frame material according to any one of [1] to [5] above, wherein the roughened layer contains at least one element selected from copper and nickel. [7] The lead frame material according to any one of [1] to [6] above, further comprising one or more layers formed on the roughened layer and having a layer different from that of the roughened layer. Composition, and contains at least one element selected from the group of nickel, palladium, rhodium, ruthenium, platinum, iridium, gold, silver and tin. [8] A method for producing a lead frame material, which is the method for producing a lead frame material according to any one of [1] to [7] above, wherein the production method is characterized in that the roughened layer is formed by electroplating. . [9] A semiconductor package made of the lead frame material described in any one of [1] to [7] above.
[發明的功效] 依據本發明,則能夠提供一種引線框架材料及其製造方法、以及使用此引線框架材料之半導體封裝體,該引線框架材料即使在高溫高濕環境下經過長時間使用的情況下,樹脂密接性也優良。[Efficacy of the invention] According to the present invention, it is possible to provide a lead frame material, a method of manufacturing the same, and a semiconductor package using the lead frame material, which have excellent resin adhesion even after being used for a long time in a high-temperature and high-humidity environment. excellent.
以下,基於實施型態來詳細說明本發明。Hereinafter, the present invention will be described in detail based on embodiments.
本發明人針對上述問題點而進行深入研究和開發的結果,注意到將表面作粗化後的層(以下,亦稱為粗化層)的表面中存在的粗化層的晶界越多,在高溫高濕試驗後越容易發生樹脂剝離。而且,發現藉由將引線框架材料的剖面中的存在於粗化層的表面中的晶界的數量控制在預定數量以下,即使在高溫高濕試驗後,也能夠維持樹脂的高度抗剪強度(shear strength),其結果,成功獲得一種引線框架材料,其樹脂密接性相較於以往更高。 本發明是基於該見解而完成。As a result of intensive research and development by the present inventors on the above-mentioned problems, it has been noticed that the more grain boundaries of the roughened layer exist on the surface of the roughened layer (hereinafter also referred to as the roughened layer), Resin peeling is more likely to occur after the high temperature and high humidity test. Also, it was found that by controlling the number of grain boundaries present in the surface of the roughened layer in the cross section of the lead frame material to be below a predetermined number, high shear strength of the resin can be maintained even after a high-temperature and high-humidity test ( shear strength), and as a result, we succeeded in obtaining a lead frame material with higher resin adhesion than before. This invention was completed based on this knowledge.
根據本發明之引線框架材料,其具有導電性基體與形成在前述導電性基體的至少單面上之粗化層。而且,在前述引線框架材料的剖面作觀察,平行於前述導電性基體的表面而在預定長度內作測定所獲得之存在於前述粗化層的表面中的晶界數量為20個/µm以下。According to the lead frame material of the present invention, it has a conductive substrate and a roughened layer formed on at least one side of the conductive substrate. In addition, the number of grain boundaries existing in the surface of the roughened layer measured within a predetermined length parallel to the surface of the conductive substrate by observing the cross section of the lead frame material is 20 grain boundaries/µm or less.
導電性基體包含銅(Cu)、鐵(Fe)或鋁(Al)。作為導電性基體,較佳是由從銅、銅合金、鐵、鐵合金、鋁及鋁合金之群組中選出的金屬或合金所構成,因為導電性和散熱性優良。The conductive matrix contains copper (Cu), iron (Fe) or aluminum (Al). As the conductive substrate, it is preferably composed of a metal or alloy selected from the group of copper, copper alloy, iron, iron alloy, aluminum, and aluminum alloy because of its excellent conductivity and heat dissipation.
例如,作為銅合金的示例,能夠舉出銅業發展協會(Copper Development Association,CDA)揭露之合金也就是C18045(Cu-0.3Cr-0.25Sn-0.5Zn)、C19400(Cu-2.3Fe-0.03P-0.15Zn)。另外,作為鐵合金的示例,能夠舉出42合金(Fe-42Ni)。並且,各元素前的數字表示合金中的質量百分率。這些合金和金屬的導電率等特性各自不同,因此會依據引線框架材料要求的特性來適當選擇。For example, examples of copper alloys include alloys disclosed by the Copper Development Association (CDA), that is, C18045 (Cu-0.3Cr-0.25Sn-0.5Zn), C19400 (Cu-2.3Fe-0.03P -0.15Zn). Moreover, 42 alloy (Fe-42Ni) can be mentioned as an example of an iron alloy. In addition, the numbers before each element represent the mass percentage in the alloy. These alloys and metals have different properties such as electrical conductivity, so they are appropriately selected according to the properties required for the lead frame material.
導電性基體的厚度並無特別限定,但例如是在0.03毫米(mm)以上且1.00mm以下的範圍內,較佳是在0.03mm以上且0.30mm以下的範圍內。The thickness of the conductive substrate is not particularly limited, but is, for example, within a range of 0.03 millimeters (mm) to 1.00 mm, preferably 0.03 mm to 0.30 mm.
在導電性基體的至少單面上形成粗化層。導電性基體的單面意謂導電性基體的頂面或底面。例如,粗化層可以僅形成在導電性基體的頂面或僅形成在導電性基體的底面上,也可以形成在頂面與底面上。A roughened layer is formed on at least one surface of the conductive substrate. One side of the conductive substrate means the top or bottom surface of the conductive substrate. For example, the roughening layer may be formed only on the top surface of the conductive substrate or only on the bottom surface of the conductive substrate, or may be formed on both the top surface and the bottom surface.
第1圖是示意性表示根據本發明之引線框架材料且用於說明存在於粗化層的表面中的晶界的計數方式之圖。並且,雖然第1圖是引線框架材料的剖面圖,但為了說明晶界,並未施加斜線也就是剖面線(hatching)以求簡便。Fig. 1 is a diagram schematically showing a lead frame material according to the present invention and for explaining how to count grain boundaries existing in the surface of a roughened layer. In addition, although FIG. 1 is a cross-sectional view of a lead frame material, in order to illustrate grain boundaries, oblique lines (hatching) are not added for simplicity.
如第1圖所示,在引線框架材料10的剖面作觀察,平行於導電性基體20的表面而在預定長度L內作測定所獲得之存在於粗化層30的表面中的晶界數量為20個/µm以下。As shown in FIG. 1, the number of grain boundaries existing in the surface of the roughened
具體而言,存在於粗化層30的表面中的晶界32的數量的計數方式如下。粗化層30的晶界32,其在粗化層30內是由實線來表示。存在於粗化層30的表面中的晶界,其如第1圖所示,表示為:在引線框架材料10的剖面作觀察時,用於表示存在於粗化層30的內部的晶界32之實線,延伸至粗化層30的表面(輪廓線)為止而相交的點(交點);並且,存在於粗化層30的內部的晶界32與粗化層30的表面(輪廓線)之交點位置,由空心圓圈作為標記來表示。然後,在平行於導電性基體20的表面之方向的預定長度L的範圍內,空心圓圈的數量,也就是表示存在於粗化層30的內部的晶界32之實線與粗化層30的表面之交點的數量,即為在預定長度L內作測定所獲得之存在於粗化層30的表面中的粗化層30的晶界32的數量。在第1圖所示之引線框架材料10中,當預定長度L為1μm時,在預定長度L內測定所獲得之存在於粗化層30的表面中的晶界32的數量是17個/μm。Specifically, the number of
在使模塑樹脂密接於引線框架材料10的表面時,會有存在於粗化層30的表面中的晶界32成為起點,而在模塑樹脂中產生龜裂(crack)或模塑樹脂從引線框架材料剝離的情況。因此,存在於粗化層30的表面中的晶界32的數量越少,越會抑制這種龜裂的發生和樹脂密接性的下降。存在於上述粗化層30的表面中的晶界32的數量(個數密度)是20個/μm以下,較佳是18個/μm以下,更佳是15個/μm以下,若上述晶界32的數量是20個/μm以下,則會充分抑制龜裂的發生和樹脂密接性的下降。When the molding resin is brought into close contact with the surface of the
存在於粗化層30的表面中的粗化層30的晶界32,其能夠藉由例如使用聚焦離子束掃描式離子顯微鏡(FIB-SIM)來觀察引線框架材料10的剖面而加以測定。The
粗化層30包含銅及鎳(Ni)中的至少一種元素。作為粗化層30,為了形成樹脂密接性優良的粗化形狀,較佳是由從銅、銅合金、鎳、鎳合金及銅鎳合金之群組中選出的金屬或合金所構成。The roughened
第2圖是示意性表示根據本發明之引線框架材料10且用於說明粗化層30的高度之圖。與第1圖同樣地,雖然第2圖是引線框架材料10的剖面圖,但為了說明粗化層30的高度,並未施加斜線也就是剖面線以求簡便。FIG. 2 is a diagram schematically showing the
在引線框架材料10的剖面作觀察,粗化層30的高度較佳是在0.1μm以上且5.0μm以下的範圍內,更佳是在0.1μm以上且3.0μm以下的範圍內。若粗化層30的高度是0.1μm以上,則對於樹脂之定錨效應會增加,而且粗化層30的比表面積會增加,因此樹脂密接性會增加。另外,若粗化層30的高度是5.0μm以下,則能夠抑制粗化層的部分脫落也就是所謂的落粉,因此可降低用於去除製造時落粉之粗化材料之維護頻率,而提升生產性。若粗化層30的高度在上述範圍內,則上述效果會充分提升。Observing the cross section of the
具體而言,粗化層30的高度如下。如第2圖所示,首先,連接粗化層30的凸部40a的二側的根部41a和41b、以及凸部40a的頂點部42而繪製三角形。隨後,針對此三角形,將根部41a和41b的連接線作為底邊B以及將頂點部42作為頂點,測量三角形的高度H。亦即,從頂點部42對底邊B拉垂直線,測量此垂直線的長度(三角形的高度H)。然後,針對預定數量的凸部40a,測量三角形的高度H,並將該測定值的平均值作為粗化層30的高度。Specifically, the height of the roughened
此處,粗化層30的凸部40a的一側的根部41a,其是在第2圖所示之引線框架材料10的剖面作觀察時,在相鄰於凸部40a之凸部40b、與凸部40a之間的粗化層30表面部分之中的最低的表面位置(最低點位置)。另外,凸部40a的另一側的根部41b,其是包夾凸部40a而位於與凸部40b相反側之凸部40c、與凸部40a之間的粗化層30表面部分之中的最低的表面位置(最低點位置)。另外,凸部40a的頂點42是凸部40a中的最高位置。Here, the
關於凸部40b及凸部40c的高度的測定方法,其亦與上述凸部40a的方法相同。Also about the measuring method of the height of the
粗化層30的高度,其能夠藉由例如使用掃描式電子顯微鏡(SEM)來觀察引線框架材料10的剖面而加以測定。The height of the roughened
另外,引線框架材料10的最外表面的比表面積,其較佳是120%以上,更佳是140%以上。比表面積意謂三維表面積相對於二維表面積之百分率((三維表面積/二維表面積)×100(%))之數值。引線框架材料10的最外表面(最表層)的比表面積越大,與樹脂之間的接觸面積增加越多,因此提升了樹脂密接性。若引線框架材料的最外表面的比表面積是120%以上,則樹脂密接性足夠大。In addition, the specific surface area of the outermost surface of the
引線框架材料10的最外表面的比表面積,其能夠藉由例如使用三維白光干涉型顯微鏡來觀察表面並算出三維表面積相對於二維表面積之百分率(%)來獲得。The specific surface area of the outermost surface of the
另外,在引線框架材料10的剖面作觀察,Σ5以下的共位晶界佔存在於粗化層30中的全部晶界的比率,其較佳是90.0%以上,更佳是92.0%以上。上述Σ5以下的共位晶界的比率越大,越會抑制在高溫高濕環境下長時間放置後之引線框架的樹脂密接性的下降。若上述Σ5以下的共位晶界的比率是90.0%以上,則會充分抑制樹脂密接性的下降。In addition, when observed in the cross-section of the
共位晶界意謂幾何學上整合性(coherency)高的特殊晶界,被定義為共位晶格點密度的倒數之Σ值越小,意謂該整合性越高。The cosite grain boundary means a special grain boundary with high geometric coherency, and is defined as the smaller the Σ value of the reciprocal of the cosite lattice point density, the higher the coherency.
本發明人由各種實驗的結果,發現在Σ值為5以下的共位晶界的比率成為90.0%以上時,在引線框架材料的耐熱試驗前後也就是在高溫高濕環境下,放置前後的樹脂密接性會良好地維持。此處,推定Σ值大的晶界因為是高能量構造,所以容易產生晶界劣化現象,容易因加熱而在晶界處產生剝離,並且,認為藉由形成Σ值小的晶界,在加熱後也能良好地維持樹脂密接性。因此,由抑制在高溫高濕環境下放置後的樹脂密接性的下降之觀點,共位晶界的Σ值越低越好。另外,Σ5以下的共位晶界的比率越高,上述效果越高。From the results of various experiments, the present inventors have found that when the ratio of colocated grain boundaries with a Σ value of 5 or less becomes 90.0% or more, the resin before and after the heat resistance test of the lead frame material, that is, in a high-temperature and high-humidity environment, before and after leaving Adhesion is well maintained. Here, it is estimated that the grain boundary with a large Σ value is a high-energy structure, so the grain boundary deterioration phenomenon is likely to occur, and peeling at the grain boundary is likely to occur due to heating, and it is considered that by forming a grain boundary with a small Σ value, the After that, the resin adhesion can be maintained well. Therefore, from the viewpoint of suppressing a decrease in resin adhesion after being left in a high-temperature, high-humidity environment, the lower the Σ value of the cosite grain boundary, the better. In addition, the higher the ratio of cosited grain boundaries equal to or less than Σ5, the higher the above-mentioned effect.
在引線框架材料的剖面也就是粗化層的剖面中的共位晶界的分析時,能夠使用電子背向散射繞射法(Electron Back Scatter Diffraction,EBSD)。 EBSD是利用在SEM內對試料照射電子束時產生的反射電子菊池線繞射(菊池圖案)之結晶方位分析技術。Electron Back Scatter Diffraction (EBSD) can be used to analyze the co-localized grain boundaries in the cross-section of the lead frame material, that is, the roughened layer. EBSD is a crystal orientation analysis technique that utilizes Kikuchi line diffraction (Kikuchi pattern) of reflected electrons that occurs when an electron beam is irradiated to a sample in a SEM.
另外,引線框架材料10可進一步具有一個以上的下述層(未圖示):形成在粗化層30上,具有與粗化層30不同的組成,且包含從鎳、鈀(Pd)、銠(Rh)、釕(Ru)、鉑(Pt)、銥(Ir)、金(Au)、銀(Ag)及錫(Sn)之群組中選出的一種以上的元素。In addition, the
在粗化層30上形成之層為一層時,此層也就是引線框架的最外表層是表面層。構成表面層之物質,其依據引線框架材料的要求特性而適當選擇。表面層由包含從金、銀及錫之群組中選出的一種以上的元素之金屬或合金所構成。表面層較佳是由金鈷合金、金、銀或錫構成,因為焊料潤濕性優良。When the layer formed on the
表面層的厚度並無特別限定,但若厚度過大,則會掩埋源自於粗化層30的高度之粗化層30的凹凸,於是樹脂密接性的提升效果有可能會下降,所以表面層的厚度的上限較佳是3.00μm以下。進一步,在構成表面層之材料主要為金等貴金屬時,材料的成本會增加,所以在使用貴金屬時,表面層的厚度的上限較佳是1.00μm以下。The thickness of the surface layer is not particularly limited, but if the thickness is too large, the unevenness of the roughened
在粗化層30上形成之層為複數層時,最外表層是表面層,且形成在表面層與粗化層30之間的層是中間層。中間層可以是一層,也可以是二層以上。例如,在中間層是二層時,粗化層側的層是中間下層,表面層側的層是中間上層。中間層會提升粗化層30與表面層之間的密接性,而且會抑制導電性基體10和粗化層30的由於熱所造成的擴散和氧化。When the layers formed on the roughened
中間層由包含從鎳、鈀、銠、釕、鉑及銥之群組中選出的一種以上的元素之金屬或合金所構成。The intermediate layer is made of metal or alloy containing one or more elements selected from the group of nickel, palladium, rhodium, ruthenium, platinum and iridium.
中間層可依據所需特性來選擇元素和厚度,在中間層是一層時,若是要求耐熱性,則期望鎳的厚度形成在0.02μm以上且2.50μm以下的範圍內,更佳是0.08μm以上且2.00μm以下的範圍內。若是要求與表面層或粗化層之間的密接性等,則期望鈀、銠、釕、鉑、銥的厚度形成在0.014μm以上且0.100μm以下的範圍內。在中間層是二層時,中間層的元素與厚度可藉由上述組合來決定。另外,在中間層由三層以上構成時,從加工性和維持粗化形狀的觀點來看,期望以合計厚度不超出2.5μm以下的範圍之方式來形成。The element and thickness of the intermediate layer can be selected according to the required characteristics. When the intermediate layer is one layer, if heat resistance is required, it is desirable that the thickness of nickel be formed within the range of 0.02 μm or more and 2.50 μm or less, more preferably 0.08 μm or more and 2.50 μm or less. In the range below 2.00μm. If adhesion to the surface layer or the roughened layer is required, it is desirable that the thickness of palladium, rhodium, ruthenium, platinum, and iridium be formed within the range of 0.014 μm or more and 0.100 μm or less. When the middle layer is two layers, the elements and thickness of the middle layer can be determined by the above combination. In addition, when the intermediate layer is composed of three or more layers, it is desirable to form it so that the total thickness does not exceed the range of 2.5 μm or less from the viewpoint of workability and roughened shape maintenance.
表面層及中間層的厚度,其能夠藉由螢光X射線膜厚計等膜厚計來加以測定。The thickness of the surface layer and the intermediate layer can be measured with a film thickness meter, such as a fluorescent X-ray film thickness meter.
依據引線框架材料的用途,適當選擇有無表面層及中間層、以及中間層的數量。Depending on the application of the lead frame material, the presence or absence of the surface layer and the intermediate layer, and the number of the intermediate layer are appropriately selected.
作為引線框架材料的製造方法,能夠利用鍍覆(plating)、披覆(clad)、蒸鍍、濺鍍等成膜方法來形成各層,由生產性和存在於粗化層的表面中的晶界數量的控制性來看,較佳是利用電鍍法來形成各層,特別是粗化層。電鍍液的組成及鍍覆條件能夠適當決定。另外,為了抑制引線框架材料的製造所需的原料使用量,單面鍍覆或厚度差異鍍覆(differential-thickness plating)也是有效的手段。As the manufacturing method of the lead frame material, each layer can be formed by using a film-forming method such as plating (plating), cladding (clad), vapor deposition, and sputtering. From the viewpoint of quantity controllability, it is preferable to form each layer, especially the roughened layer, by electroplating. The composition of the plating solution and the plating conditions can be appropriately determined. In addition, in order to suppress the amount of raw materials used for the production of the lead frame material, single-side plating or differential-thickness plating (differential-thickness plating) is also an effective means.
作為控制利用電鍍法形成的存在於粗化層(電鍍層)的表面中的晶界數量(個數密度)的方法,例如,能夠舉出在藉由電鍍形成粗化層時,控制電沉積(electrodeposition)時的結晶成長。為了使晶界數量在上述範圍內,可將粗化形成(電鍍)時的電壓以成為5V以上且10V以下的方式來適當調整。另外,為了控制電沉積時的結晶成長,導電性基體周圍的鍍液的流速會變得重要。若鍍液的流速高,則小的晶粒會大量成長,因此可適當調節。不過,流速難以定量測定,在一邊使用攪拌子來攪拌鍍浴,一邊利用電鍍法來形成粗化層的情況下,可適當調整攪拌子的轉速。作為粗化層的形成方法,作為其他鍍覆條件,適當變更電流密度、鍍液中的導電性鹽的濃度、浴溫等會特別有效。As a method of controlling the number of grain boundaries (number density) existing in the surface of the roughened layer (plated layer) formed by the electroplating method, for example, when the roughened layer is formed by electroplating, controlling the electrodeposition ( electrodeposition) during crystal growth. In order to make the number of grain boundaries fall within the above-mentioned range, the voltage at the time of roughening formation (plating) can be adjusted suitably so that it may become 5V or more and 10V or less. In addition, in order to control crystal growth during electrodeposition, the flow rate of the plating solution around the conductive substrate becomes important. If the flow rate of the plating solution is high, a large number of small crystal grains will grow, so it can be adjusted appropriately. However, it is difficult to quantitatively measure the flow rate. When forming a roughened layer by electroplating while stirring the plating bath using a stirrer, the rotation speed of the stirrer can be appropriately adjusted. As a method of forming the roughened layer, it is particularly effective to appropriately change the current density, the concentration of the conductive salt in the plating solution, the bath temperature, and the like as other plating conditions.
引線框架材料,支撐並固定半導體元件,作為用於進行與外部電性和訊號交換之連接端子,例如用於半導體封裝體。依據要被安裝之半導體元件,引線框架材料可合適地用於電晶體和電容器、發光二極體(LED)等。Lead frame material, supports and fixes semiconductor components, as connection terminals for exchanging electricity and signals with the outside, such as for semiconductor packages. The lead frame material can be suitably used for transistors and capacitors, light emitting diodes (LEDs), and the like depending on semiconductor elements to be mounted.
依據以上說明之實施型態,引線框架材料的存在於粗化層的表面中的晶界數量被控制在預定值以下,因此即使在高溫高濕環境下經過長時間使用的情況下,樹脂密接性也良好。According to the embodiment described above, the number of grain boundaries existing in the surface of the roughened layer of the lead frame material is controlled below a predetermined value, so that resin adhesion is improved even after a long period of use in a high-temperature and high-humidity environment. Also good.
以上,已針對實施型態作說明,但本發明並非限定於上述實施型態,而包含本發明的概念及申請專利範圍所包含的所有態樣,在本發明的範圍內,能夠進行各種改變。 [實施例]The embodiments have been described above, but the present invention is not limited to the above-mentioned embodiments, but includes all the aspects included in the concept of the present invention and the claims, and various changes can be made within the scope of the present invention. [Example]
隨後,針對實施例及比較例作說明,但本發明並非限定於這些實施例。Next, Examples and Comparative Examples will be described, but the present invention is not limited to these Examples.
(實施例1~19、比較例1~5) 對於表1所示的種類且具有板厚之導電性基體,在以下所示的條件下,作為預處理,施行陰極電解脫脂及酸洗後,利用表1及以下所示的條件之電鍍法,在導電性基體上形成粗化層。接著,在形成中間層(中間下層和中間上層)和表面層時,利用表1及以下所示的條件之電鍍法,以成為表1所示的厚度之方式,在粗化層上形成中間層、表面層等。如此,獲得了引線框架材料。(Examples 1-19, Comparative Examples 1-5) For conductive substrates of the types shown in Table 1 and having a plate thickness, under the conditions shown below, as a pretreatment, after performing cathodic electrolytic degreasing and pickling, the electroplating method using the conditions shown in Table 1 and below, A roughened layer is formed on the conductive substrate. Next, when forming the intermediate layer (middle lower layer and intermediate upper layer) and the surface layer, the intermediate layer is formed on the roughened layer so as to have the thickness shown in Table 1 by the plating method under the conditions shown in Table 1 and below. , surface layer, etc. In this way, a lead frame material is obtained.
預處理條件如下。The pretreatment conditions are as follows.
[陰極電解脫脂] >溶液組成> 氫氧化鈉:60g/L 液溫:60°C 電流密度:2.5A/dm2 處理時間:60秒[Chodic electrolytic degreasing] >Solution composition> Sodium hydroxide: 60g/L Liquid temperature: 60°C Current density: 2.5A/dm 2 Processing time: 60 seconds
[酸洗] >溶液組成> 10%硫酸 液溫:室溫 處理時間:30秒[pickling] >Solution Composition> 10% sulfuric acid Liquid temperature: room temperature Processing time: 30 seconds
關於粗化層的形成,在內徑為80mm之筒狀電鍍槽中,投入直徑φ為5mm且長度為30mm之攪拌子,並置入1L的鍍液,利用磁攪拌器,在轉速為0~800r.p.m.內變化來調整攪拌狀態。粗化層的形成條件如下所示,而且,關於粗化鍍覆時的電壓(單位:V)及攪拌子的轉速(單位:r.p.m.),表示於表1中。Regarding the formation of the roughened layer, in a cylindrical electroplating tank with an inner diameter of 80mm, put a stirrer with a diameter of 5mm and a length of 30mm, and put 1L of plating solution, using a magnetic stirrer, at a speed of 0~ Change within 800r.p.m. to adjust the stirring state. The conditions for forming the roughened layer are as follows, and Table 1 shows the voltage (unit: V) and the rotation speed (unit: r.p.m.) of the stirrer during the roughening plating.
[粗化Cu之鍍覆] >溶液組成> 硫酸銅:作為銅濃度為5~10g/L 硫酸:30~120g/L 鉬酸銨:作為鉬(Mo)金屬為0.1~5.0g/L 液溫:20~60°C 電流密度:10~60A/dm2 [Coarse Cu plating] >Solution composition> Copper sulfate: 5-10g/L as copper concentration Sulfuric acid: 30-120g/L Ammonium molybdate: 0.1-5.0g/L as molybdenum (Mo) metal Liquid temperature : 20~60°C Current density: 10~60A/dm 2
[粗化Ni之鍍覆] >溶液組成> 硫酸鎳:10~50g/L 硼酸:10~30g/L 氯化鈉:30~g/L 25%氨水:10~30mL/L 浴溫:50°C 電流密度:4~10A/dm2 [Coarsening Ni plating] >Solution composition> Nickel sulfate: 10~50g/L Boric acid: 10~30g/L Sodium chloride: 30~g/L 25% ammonia water: 10~30mL/L Bath temperature: 50° C current density: 4~10A/ dm2
中間層的形成條件如下。The formation conditions of the intermediate layer are as follows.
[Ni之鍍覆] >溶液組成> 胺磺酸鎳:300~500g/L 氯化鎳:20~40g/L 硼酸:20~40g/L 液溫:50°C 電流密度:6~10A/dm2 [Ni plating] >Solution composition> Nickel sulfamate: 300~500g/L Nickel chloride: 20~40g/L Boric acid: 20~40g/L Liquid temperature: 50°C Current density: 6~10A/dm 2
[Pd之鍍覆] >溶液組成> 四氨基二氯化鈀(tetraammine palladium(Ⅱ)chloride):1~50g/L 胺磺酸銨:0.1~300g/L 乙醇酸(glycolic acid):0.001~100g/L 磷酸銨:0.1~50g/L 氯化銨:0.1~300g/L 液溫:30~70°C 電流密度:0.2~50A/dm2 [Pd Plating] >Solution Composition> Tetraammine palladium(Ⅱ)chloride: 1-50g/L Ammonium sulfamate: 0.1-300g/L Glycolic acid: 0.001-100g /L ammonium phosphate: 0.1~50g/L ammonium chloride: 0.1~300g/L liquid temperature: 30~70°C current density: 0.2~50A/dm 2
[Rh之鍍覆] >溶液組成> 硫酸銠:2~10g/L 硫酸:50~90g/L 液溫:50°C 電流密度:0.1~5A/dm2 [Rh plating] >Solution composition> Rhodium sulfate: 2~10g/L Sulfuric acid: 50~90g/L Liquid temperature: 50°C Current density: 0.1~5A/dm 2
[Ru之鍍覆] >溶液組成> 亞硝基氯化釕:2~20g/L 胺磺酸:10~30g/L 液溫:60°C 電流密度:0.1~50A/dm2 [Plating of Ru] >Solution composition> Nitroso ruthenium chloride: 2~20g/L Ammonium sulfonic acid: 10~30g/L Liquid temperature: 60°C Current density: 0.1~50A/dm 2
表面層的形成條件如下。The conditions for forming the surface layer are as follows.
[Au之衝擊電鍍(strike plating)] >溶液組成> 金氰化鉀:1~5g/L 檸檬酸:10~60g/L 檸檬酸鉀:50~100g/L 液溫:40°C 電流密度:0.1~1A/dm2 [Strike plating of Au] >Solution composition> Potassium gold cyanide: 1~5g/L Citric acid: 10~60g/L Potassium citrate: 50~100g/L Liquid temperature: 40°C Current density: 0.1~1A/ dm2
[AuCo之鍍覆] >溶液組成> 金氰化鉀:6~20g/L 檸檬酸:60~120g/L 磷酸氫二鉀:10~30g/L 碳酸鈷:0.1~2g/L 液溫:40°C 電流密度:0.1~5A/dm2 [AuCo plating] >Solution composition> Potassium gold cyanide: 6~20g/L Citric acid: 60~120g/L Dipotassium hydrogen phosphate: 10~30g/L Cobalt carbonate: 0.1~2g/L Liquid temperature: 40 °C Current density: 0.1~5A/dm 2
[Au之鍍覆] >溶液組成> 金氰化鉀:8~20g/L 檸檬酸:10~100g/L 磷酸氫二鉀:10~150g/L 液溫:60°C 電流密度:0.1~10A/dm2 [Au plating] >Solution composition> Potassium gold cyanide: 8~20g/L Citric acid: 10~100g/L Dipotassium hydrogen phosphate: 10~150g/L Liquid temperature: 60°C Current density: 0.1~10A /dm 2
[Ag之衝擊電鍍] >溶液組成> 氰化銀鉀:1~5g/L 氰化鉀:50~150g/L 液溫:30°C 電流密度:1~5A/dm2 [Ag impact plating] >Solution composition> Potassium silver cyanide: 1~5g/L Potassium cyanide: 50~150g/L Liquid temperature: 30°C Current density: 1~5A/dm 2
[Ag之鍍覆] >溶液組成> 氰化銀:10~100g/L 氰化鉀:20~150g/L 液溫:30°C 電流密度:0.1~5A/dm2 [Ag plating] >Solution composition> Silver cyanide: 10~100g/L Potassium cyanide: 20~150g/L Liquid temperature: 30°C Current density: 0.1~5A/dm 2
[Sn之鍍覆] >溶液組成> 硫酸錫:20~120g/L 硫酸:30~150g/L 甲酚磺酸:10~100g/L 液溫:20°C 電流密度:0.1~6A/dm2 [Sn plating] >Solution composition> Tin sulfate: 20~120g/L Sulfuric acid: 30~150g/L Cresolsulfonic acid: 10~100g/L Liquid temperature: 20°C Current density: 0.1~6A/dm 2
[Cu之鍍覆] >溶液組成> 硫酸銅:200g/L 硫酸:50g/L 液溫:40°C 電流密度:5A/dm2 [Cu plating] >Solution composition> Copper sulfate: 200g/L Sulfuric acid: 50g/L Liquid temperature: 40°C Current density: 5A/dm 2
Au之衝擊電鍍在實施例3~15及比較例3~4中進行,Au鍍覆在實施例15及比較例5中進行。另外,Ag之衝擊電鍍及Ag鍍覆在實施例16~17中進行。進一步,Sn鍍覆在實施例18~19中進行。實施例1形成Cu鍍覆之粗化層,實施例2形成Ni鍍覆之粗化層,且不進行中間層及表面層的形成。比較例1不形成粗化層及中間層而僅進行Cu鍍覆的表面層的形成。比較例2形成Cu鍍覆之粗化層,而不進行中間層及表面層的形成。比較例5不形成粗化層而進行中間層及表面層的鍍覆。The strike plating of Au was performed in Examples 3-15 and Comparative Examples 3-4, and Au plating was performed in Example 15 and Comparative Example 5. In addition, Ag strike plating and Ag plating were performed in Examples 16-17. Furthermore, Sn plating was performed in Examples 18-19. In Example 1, a roughened layer of Cu plating was formed, and in Example 2, a roughened layer of Ni plating was formed, and no intermediate layer and surface layer were formed. In Comparative Example 1, only the Cu-plated surface layer was formed without forming a roughened layer and an intermediate layer. In Comparative Example 2, a roughened layer of Cu plating was formed without forming an intermediate layer and a surface layer. In Comparative Example 5, plating of the intermediate layer and the surface layer was performed without forming a roughened layer.
>評估方法> 隨後,關於各層及引線框架材料的特性與評估,如下述般地進行。結果表示於表1及表2中。並且,針對各層的特性,在引線框架材料之製作中隨時作測定。>Assessment method> Then, the characteristics and evaluation of each layer and lead frame material were performed as follows. The results are shown in Table 1 and Table 2. In addition, the characteristics of each layer are measured at any time during the production of the lead frame material.
(晶界數量) 藉由聚焦離子束掃描式離子顯微鏡(FIB-SIM),將製作出的引線框架材料的粗化層作剖面觀察。在剖面觀察中,平行於導電性基體表面且將預定長度L設為4μm來作測定時,測量存在於粗化層的表面中的粗化層的晶界數量,而算出上述的每1μm長度的晶界數量(單位:個/μm)。(number of grain boundaries) The roughened layer of the produced lead frame material was observed in section by focused ion beam scanning ion microscope (FIB-SIM). In the cross-sectional observation, when measuring parallel to the surface of the conductive substrate and setting the predetermined length L to 4 μm, the number of grain boundaries of the roughened layer existing on the surface of the roughened layer is measured, and the above-mentioned number per 1 μm of length is calculated. The number of grain boundaries (unit: piece/μm).
(中間層及表面層的厚度) 中間層及表面層的厚度,其藉由根據JIS H8501:1999之螢光X射線式試驗方法來測定。具體而言,使用螢光X射線膜厚計(SFT 9400,SII NanoTechnology Inc.製),將準直器(collimator)直徑設為0.5mm,測定各層的任意10處,並算出這些測定值的平均值,藉此獲得中間層及表面層的厚度。另外,在表面層是銅時,藉由根據JIS H8501:1999之電解式試驗方法來測定厚度。具體而言,使用電解式膜厚計(CT-4,Densoku Instruments Co.,Ltd.製),對1cm2 區域(任意五處)分別作測定,並算出平均值(n=5),而獲得表面層的厚度。並且,在電解式試驗方法中使用的電解液設為Densoku Instruments Co.,Ltd.製的K52。(Thickness of Intermediate Layer and Surface Layer) The thickness of the intermediate layer and the surface layer is measured by a fluorescent X-ray test method based on JIS H8501:1999. Specifically, using a fluorescent X-ray film thickness meter (SFT 9400, manufactured by SII NanoTechnology Inc.), with a collimator (collimator) diameter of 0.5 mm, arbitrary 10 points of each layer were measured, and the average of these measured values was calculated. value, thereby obtaining the thickness of the middle layer and the surface layer. In addition, when the surface layer is copper, the thickness is measured by the electrolytic test method based on JIS H8501:1999. Specifically, using an electrolytic film thickness meter (CT-4, manufactured by Densoku Instruments Co., Ltd.), each measurement was performed on a 1 cm 2 area (arbitrary five locations), and the average value (n=5) was calculated to obtain The thickness of the surface layer. In addition, the electrolytic solution used in the electrolytic test method was K52 manufactured by Densoku Instruments Co., Ltd.
(粗化層的高度) 將製作出的引線框架材料的剖面作切片加工,使用SEM並以20000倍作觀察。測定從粗化層的觀察圖像中隨機選擇的10個凸部的高度,將這些測定值的平均值作為粗化層的高度。在從剖面SEM圖像無法觀察到10個凸部的情況下,使用2~3張拍攝位置不同的剖面SEM圖像來觀察凸部。(coarsening layer height) The section of the produced lead frame material was sliced and observed at 20,000 magnifications using an SEM. The height of 10 convex parts randomly selected from the observation image of a roughened layer was measured, and the average value of these measured values was made into the height of a roughened layer. When 10 protrusions cannot be observed from the cross-sectional SEM image, the protrusions are observed using two to three cross-sectional SEM images having different imaging positions.
(引線框架材料的最外表面的比表面積) 引線框架材料的最外表面的比表面積,其使用三維白光干涉型顯微鏡(Contour GT-K,BRUKER公司製)來測定三維表面積相對於二維表面積之百分率((三維表面積/二維表面積)×100(%))(測定條件為測定倍率10倍且使用高解析度感光耦合元件(CCD)相機,且在測定後不加上特別濾鏡而作量化),並將其平均值(n=5)作為比表面積(%)。(specific surface area of the outermost surface of the lead frame material) The specific surface area of the outermost surface of the lead frame material, which was measured using a three-dimensional white light interference microscope (Contour GT-K, manufactured by BRUKER) as a percentage of the three-dimensional surface area to the two-dimensional surface area ((three-dimensional surface area/two-dimensional surface area) × 100 (%)) (the measurement conditions are 10 times the measurement magnification and use a high-resolution photosensitive coupling device (CCD) camera, and quantify without adding a special filter after the measurement), and the average value (n=5) as specific surface area (%).
(共位晶界) 在粗化層剖面中的共位晶界的分析中,使用EBSD。並且,在EBSD測定中,為了獲得清晰的菊池線繞射圖像,需要去除附著在測定面上之異物而且需要將測定面作鏡面最終處理。因此,在樹脂填埋測定試料後,進行剖面研磨(cross-section polisher,CP)加工,並施行粗化層剖面的研磨加工,而獲得觀察面。(colocated grain boundary) In the analysis of the colocalized grain boundaries in the roughened layer profile, EBSD was used. In addition, in EBSD measurement, in order to obtain a clear Kikuchi line diffraction image, it is necessary to remove foreign matter attached to the measurement surface and to perform a mirror finish on the measurement surface. Therefore, after the resin is embedded in the measurement sample, cross-section polisher (CP) processing is performed, and polishing of the cross-section of the roughened layer is performed to obtain an observation surface.
關於EBSD測定,將6μm×16μm的範圍以25nm的步長(step)作掃描,並以能夠僅分析粗化層的方式,依據粗化層的厚度裁剪高度方向。使用分析用軟體(Orientation Imaging Microscopy v5,EDAX/TSL公司(現為AMETEK公司)製),分析粗化層的剖面。為了預先排除觀察範圍內的樹脂的影響,去除0.1μm以下的晶粒尺寸的數據,僅抽取粗化層的數據,藉此,算出Σ1~Σ49為止的共位晶界(Coincidence Site Lattice,CSL)。並且,在測定對象中,當相鄰像素(pixel)的方位差(偏差)是15°以上時,則判斷為晶界。表1表示了作為共位晶界,Σ5以下的共位晶界佔存在於粗化層中的粗化層的全部晶界的比率。For the EBSD measurement, a range of 6 μm×16 μm was scanned at a step size of 25 nm, and the height direction was clipped according to the thickness of the roughened layer so that only the roughened layer could be analyzed. The cross section of the roughened layer was analyzed using analysis software (Orientation Imaging Microscopy v5, manufactured by EDAX/TSL (currently AMETEK)). In order to exclude the influence of the resin within the observation range, the data of the grain size below 0.1 μm is removed, and only the data of the roughened layer is extracted, thereby calculating the Coincidence Site Lattice (CSL) from Σ1 to Σ49 . In addition, in the measurement object, when the orientation difference (deviation) of adjacent pixels (pixels) is 15° or more, it is determined to be a grain boundary. Table 1 shows the ratio of cosite grain boundaries below Σ5 to all grain boundaries in the roughened layer existing in the roughened layer as colocated grain boundaries.
(樹脂密接性) 使用轉移模具試驗裝置(Model FTS,KOHTAKI Corporation製),在製作出的引線框架材料的表面上射出成形具有直徑2.6mm之接觸面且由樹脂構成之布丁狀試驗片。針對密接於引線框架材料的最外表面之試驗片,進行測定剪切力之試驗,並評估引線框架材料與試驗片之間的樹脂密接性。評估試驗所使用的樹脂及裝置如下所示。(resin adhesion) Using a transfer die tester (Model FTS, manufactured by Kohtaki Corporation), a pudding-shaped test piece made of resin having a contact surface with a diameter of 2.6 mm was injection-molded on the surface of the produced lead frame material. A test for measuring shear force was performed on the test piece that was in close contact with the outermost surface of the lead frame material, and the resin adhesion between the lead frame material and the test piece was evaluated. The resins and devices used in the evaluation tests are shown below.
樹脂:SUMIKON G630L(商品名),Sumitomo Bakelite Co., Ltd.製 裝置:4000 Plus(商品名),Nordson Advanced Technology製Resin: SUMIKON G630L (trade name), manufactured by Sumitomo Bakelite Co., Ltd. Device: 4000 Plus (trade name), manufactured by Nordson Advanced Technology
另外,評估試驗的測定條件如下所示。 荷重元(load cell):S50KG 測定範圍:50kg 測試速度:100μm/s 測試高度:200μm 評估試驗次數:12次In addition, the measurement conditions of the evaluation test are as follows. Load cell: S50KG Measuring range: 50kg Test speed: 100μm/s Test height: 200μm Number of evaluation trials: 12
首先,針對已密接於引線框架材料上之試驗片,藉由上述測定條件來測定剪切力,並將其平均值(n=12)作為高溫高濕試驗前的樹脂密接強度。隨後,將已密接試驗片之引線框架材料投入至高溫高濕試驗(85℃,85%RH,168小時)後,藉由上述測定條件來測定剪切力,並將其平均值(n=12)作為高溫高濕試驗後的樹脂密接強度。然後,針對高溫高濕試驗前及試驗後的樹脂密接強度,分別將10kgf/mm2 以上排名為「A」(優良),將7kgf/mm2 以上且未滿10kgf/mm2 排名為「B」(良好),將0kgf/mm2 以上且未滿7kgf/mm2 排名為「C」(不可)。A及B排名為合格。另外,針對在高溫高濕試驗前後的樹脂密接強度的下降比率(樹脂密接強度的下降之抑制性),將(高溫高濕試驗後的樹脂密接強度/高溫高濕試驗前的樹脂密接強度)×100(%)的數值為80%以上排名為「A」(優良),70%以上且未滿80%排名為「B」(良好),未滿70%排名為「C」(不可)。A及B排名為合格。First, for the test piece that has been bonded to the lead frame material, the shear force was measured under the above measurement conditions, and the average value (n=12) was used as the resin bonding strength before the high-temperature and high-humidity test. Then, after putting the lead frame material that has been tightly bonded to the test piece into the high temperature and high humidity test (85°C, 85%RH, 168 hours), the shear force was measured by the above measurement conditions, and the average value (n=12 ) as the resin adhesion strength after the high temperature and high humidity test. Then, for the resin adhesion strength before and after the high-temperature and high-humidity test, rank 10kgf/mm2 or more as "A" (excellent), and rank 7kgf/mm2 or more and less than 10kgf/ mm2 as "B" (Good), 0kgf/mm 2 or more and less than 7kgf/mm 2 is ranked as "C" (impossible). A and B ranks are qualified. In addition, for the decrease ratio of the resin adhesion strength before and after the high-temperature and high-humidity test (suppression of the decrease in the resin adhesion strength), (resin adhesion strength after the high-temperature and high-humidity test/resin adhesion strength before the high-temperature and high-humidity test)× If the value of 100 (%) is more than 80%, it will be ranked as "A" (excellent), if it is more than 70% but less than 80%, it will be ranked as "B" (good), and if it is less than 70%, it will be ranked as "C" (impossible). A and B ranks are qualified.
隨後,目視觀察高溫高濕試驗後的引線框架材料與由樹脂構成之試驗片之間的剝離界面的狀態。然後,將引線框架材料上殘存有樹脂的情況作為「○」,將引線框架材料上沒有殘存樹脂的情況作為「×」。Subsequently, the state of the peeled interface between the lead frame material and the test piece made of resin after the high-temperature, high-humidity test was visually observed. Then, the case where the resin remained on the lead frame material was made "◯", and the case where the resin was not left on the lead frame material was made "X".
在實施例1~19中,觀察到樹脂殘存在引線框架材料上的狀態。這被推測是因為,藉由在樹脂密接性適合的狀態下形成粗化層,引線框架材料與樹脂之間的密接強度會上升,於是不會引起如同以往的引線框架材料與樹脂之間的界面剝離而產生樹脂的破壞。作為粗化鍍覆條件,在5~10V且將攪拌子轉速設為100~250r.p.m.之最佳條件下,控制電沉積時的結晶成長,藉此,能夠製造一種引線框架材料,其樹脂密接性相較於以往更加提升。In Examples 1 to 19, the state where the resin remained on the lead frame material was observed. This is presumed to be because, by forming the roughened layer in a state where the adhesiveness of the resin is suitable, the adhesion strength between the lead frame material and the resin increases, so that the interface between the lead frame material and the resin does not occur as in the past. Delamination of the resin due to peeling. As roughening plating conditions, under the optimal conditions of 5-10V and the stirring bar rotation speed set at 100-250r.p.m., crystal growth during electrodeposition can be controlled, thereby making it possible to manufacture a lead frame material whose resin is tightly bonded. Sex is more improved than before.
另一方面,在比較例1~5的引線框架材料中,特別是高溫高濕試驗後的樹脂密接性不合格,且在高溫高濕試驗後的剪切時,會從引線框架材料與樹脂(試驗片)之間的界面產生剝離,於是在引線框架材料上沒有觀察到樹脂。On the other hand, in the lead frame materials of Comparative Examples 1 to 5, the resin adhesiveness after the high-temperature and high-humidity test was unacceptable, and when shearing after the high-temperature and high-humidity test, the lead frame material and the resin ( The interface between the test pieces) was delaminated, and no resin was observed on the lead frame material.
[表1] [Table 1]
[表2] [Table 2]
10‧‧‧引線框架材料
20‧‧‧導電性基體
30‧‧‧粗化層
32‧‧‧晶界
40a、40b、40c‧‧‧凸部
41a、41b‧‧‧(凸部的)根部
42‧‧‧頂點部
B‧‧‧三角形的底邊
H‧‧‧三角形的高度
L‧‧‧預定長度10‧‧‧
第1圖是示意性表示根據本發明之引線框架材料且用於說明存在於粗化層的表面中的晶界的計數方式之圖。 第2圖是示意性表示根據本發明之引線框架材料且用於說明粗化層的高度之圖。Fig. 1 is a diagram schematically showing a lead frame material according to the present invention and for explaining how to count grain boundaries existing in the surface of a roughened layer. Fig. 2 is a diagram schematically showing a lead frame material according to the present invention and illustrating the height of a roughened layer.
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無Domestic deposit information (please note in order of depositor, date, and number) none
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無Overseas storage information (please note in order of storage country, organization, date, and number) none
10‧‧‧引線框架材料 10‧‧‧lead frame material
20‧‧‧導電性基體 20‧‧‧Conductive substrate
30‧‧‧粗化層 30‧‧‧roughening layer
32‧‧‧晶界 32‧‧‧grain boundary
L‧‧‧預定長度 L‧‧‧predetermined length
Claims (9)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018-055486 | 2018-03-23 | ||
| JP2018055486 | 2018-03-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201940743A TW201940743A (en) | 2019-10-16 |
| TWI788542B true TWI788542B (en) | 2023-01-01 |
Family
ID=67986214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW108109707A TWI788542B (en) | 2018-03-23 | 2019-03-21 | Lead frame material, manufacturing method thereof, and semiconductor package using the lead frame material |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP6667728B2 (en) |
| KR (1) | KR102589528B1 (en) |
| CN (1) | CN111557043B (en) |
| TW (1) | TWI788542B (en) |
| WO (1) | WO2019181924A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7608130B2 (en) * | 2020-11-27 | 2025-01-06 | Jx金属株式会社 | Plating materials and electronic parts |
| CN120569519A (en) * | 2023-01-19 | 2025-08-29 | 奥野制药工业株式会社 | Copper film |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW391042B (en) * | 1997-02-03 | 2000-05-21 | Nippon Denkai Ltd | Lead frame material |
| TW200636963A (en) * | 2005-04-15 | 2006-10-16 | Samsung Techwin Co Ltd | Lead frame for semiconductor package |
| JP2014204046A (en) * | 2013-04-08 | 2014-10-27 | 古河電気工業株式会社 | Lead frame for optical semiconductor device and manufacturing method therefor, and optical semiconductor device |
| TW201726983A (en) * | 2015-11-05 | 2017-08-01 | 古河電氣工業股份有限公司 | Lead frame material and method of manufacturing same |
| TW201803065A (en) * | 2016-04-12 | 2018-01-16 | 古河電氣工業股份有限公司 | Lead frame material and method of manufacturing same |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2543619Y2 (en) | 1991-08-27 | 1997-08-13 | 中部電力株式会社 | Mobile trolley pressing device |
| JPH06252311A (en) * | 1993-03-01 | 1994-09-09 | Mitsubishi Electric Corp | Lead frame, manufacturing method thereof, and semiconductor device using the lead frame |
| JPH1027873A (en) | 1996-07-11 | 1998-01-27 | Nippon Koujiyundo Kagaku Kk | Lead frame for semiconductor device |
| JP4628263B2 (en) * | 2005-12-05 | 2011-02-09 | 新光電気工業株式会社 | Package component, manufacturing method thereof, and semiconductor package |
| JP5057932B2 (en) * | 2007-10-31 | 2012-10-24 | Jx日鉱日石金属株式会社 | Rolled copper foil and flexible printed wiring board |
| JP5150597B2 (en) * | 2009-10-08 | 2013-02-20 | 新電元工業株式会社 | Semiconductor package and manufacturing method thereof |
| JP5700834B2 (en) * | 2011-12-09 | 2015-04-15 | 株式会社神戸製鋼所 | High strength copper alloy sheet with excellent oxide film adhesion |
| JP5863174B2 (en) * | 2012-03-01 | 2016-02-16 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| KR101626214B1 (en) * | 2013-10-22 | 2016-05-31 | 스미토모 긴조쿠 고잔 가부시키가이샤 | Two-layered flexible wiring substrate and flexible wiring board using the same |
| JP5766318B2 (en) * | 2014-02-17 | 2015-08-19 | 株式会社三井ハイテック | Lead frame |
| WO2016174998A1 (en) * | 2015-04-28 | 2016-11-03 | 三井金属鉱業株式会社 | Roughened copper foil and printed wiring board |
| JP3228789U (en) | 2020-08-03 | 2020-11-12 | 一広株式会社 | Cooling mask |
-
2019
- 2019-03-19 KR KR1020207020344A patent/KR102589528B1/en active Active
- 2019-03-19 JP JP2019536608A patent/JP6667728B2/en active Active
- 2019-03-19 WO PCT/JP2019/011407 patent/WO2019181924A1/en not_active Ceased
- 2019-03-19 CN CN201980007383.6A patent/CN111557043B/en active Active
- 2019-03-21 TW TW108109707A patent/TWI788542B/en active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW391042B (en) * | 1997-02-03 | 2000-05-21 | Nippon Denkai Ltd | Lead frame material |
| TW200636963A (en) * | 2005-04-15 | 2006-10-16 | Samsung Techwin Co Ltd | Lead frame for semiconductor package |
| JP2014204046A (en) * | 2013-04-08 | 2014-10-27 | 古河電気工業株式会社 | Lead frame for optical semiconductor device and manufacturing method therefor, and optical semiconductor device |
| TW201726983A (en) * | 2015-11-05 | 2017-08-01 | 古河電氣工業股份有限公司 | Lead frame material and method of manufacturing same |
| TW201803065A (en) * | 2016-04-12 | 2018-01-16 | 古河電氣工業股份有限公司 | Lead frame material and method of manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6667728B2 (en) | 2020-03-18 |
| JPWO2019181924A1 (en) | 2020-04-30 |
| WO2019181924A1 (en) | 2019-09-26 |
| KR102589528B1 (en) | 2023-10-13 |
| CN111557043B (en) | 2024-09-17 |
| CN111557043A (en) | 2020-08-18 |
| TW201940743A (en) | 2019-10-16 |
| KR20200135288A (en) | 2020-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW200536031A (en) | Fretting and whisker resistant coating system and method | |
| TWI762546B (en) | Lead frame material, method for manufacturing the same, and semiconductor package | |
| CN108026657B (en) | Lead frame material and method for producing same | |
| TWI788542B (en) | Lead frame material, manufacturing method thereof, and semiconductor package using the lead frame material | |
| TWI751150B (en) | Lead frame material and manufacturing method thereof | |
| TWI557750B (en) | Electrical contact material and manufacturing method thereof | |
| WO2020079904A1 (en) | Electroconductive material, molded article, and electronic component | |
| JP7178530B1 (en) | Lead frame material, manufacturing method thereof, and semiconductor package | |
| JP7366480B1 (en) | Lead frame material and its manufacturing method, and semiconductor package using lead frame material | |
| JP6805217B2 (en) | Conductive materials, molded products and electronic components | |
| WO2023286697A1 (en) | Lead frame material and method for producing same, and semiconductor package | |
| JP4887533B2 (en) | Silver plated metal member and manufacturing method thereof | |
| JP6623108B2 (en) | Lead frame material and manufacturing method thereof | |
| KR102918295B1 (en) | Lead frame material and its manufacturing method and semiconductor package | |
| JP7809883B1 (en) | Materials for electronic components and manufacturing method thereof, lead frame materials and manufacturing method thereof, and semiconductor packages | |
| WO2024257796A1 (en) | Lead frame material and method for producing same, and semiconductor package | |
| WO2026028551A1 (en) | Material for electronic component and method for producing same, lead frame material and method for producing same, and semiconductor package |