TWI787677B - Memory testing device and memory testing method - Google Patents

Abstract

A memory testing device and a memory testing method are provided. The memory test device includes a test board, a mainboard, and a processor. The test board carries at least one memory chip under test. The mainboard has a plurality of memory slots. At least one memory module and a test board are respectively inserted into the memory slots, so that the memory slots are fully loaded. The processor is set on the mainboard. The processor turns off the interleaved access mode to enter the sequential access mode, determines a test address range of the test board, and tests the at least one memory chip under test based on the test address range of the test board.

Description

Memory testing device and memory testing method

The invention relates to a memory testing device and a memory testing method, in particular to a memory testing device and a memory testing method for testing the memory when the mainboard is in a full state of memory.

In the current memory full load test, the memory to be tested is inserted into the slot of the motherboard, and the remaining vacant slots are filled with normal memory modules (commonly called golden modules). In this way, the full load test can test the actual performance of the memory to be tested when the socket of the motherboard is fully loaded.

However, the test program used tests all address ranges of the memory under test as well as normal memory modules. Since the test range includes the address range of normal memory modules, most of the test time is spent on testing normal memory modules. This test efficiency will be greatly reduced.

The invention is aimed at a memory testing device and a memory testing method, which can greatly improve the test efficiency of the full load test of the memory to be tested.

According to an embodiment of the present invention, a memory testing device includes a testing board, a motherboard, and a processor. The test board is configured to carry at least one memory chip to be tested. Motherboards have multiple memory slots. At least one memory module and a test board are respectively inserted into the plurality of memory slots, so that the plurality of memory slots are fully loaded. The processor is provided on the motherboard. The processor is configured to turn off the interleaved access mode to enter the sequential access mode, determine a test address range of the test board, and test at least one memory chip under test based on the test address range of the test board to obtain a first test result corresponding to the at least one memory chip to be tested.

According to an embodiment of the present invention, the memory testing method includes: making the test board carry at least one memory chip to be tested, and inserting at least one memory module and the test board into a plurality of memory slots of the motherboard respectively, so as to Make the plurality of memory slots present a full load condition; close the interleave access mode to enter the sequential access mode; determine the test address range of the test board; and based on the test address range of the test board for at least A memory chip to be tested is tested to obtain a first test result corresponding to the at least one memory chip to be tested.

Based on the above, when the plurality of memory slots are fully loaded, the memory testing device and memory testing method of the present invention will turn off the interleaved access mode to enter the sequential access mode, and determine the test position of the test board address range, and test at least one memory chip to be tested. The memory testing device and memory testing method of the present invention can only test the memory chip to be tested mounted on the test board in the sequential access mode. In this way, the present invention can greatly improve the test efficiency of the full load test of the memory to be tested.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Parts of the embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the referenced reference symbols in the following description, when the same reference symbols appear in different drawings, they will be regarded as the same or similar components. These embodiments are only a part of the present invention, and do not reveal all possible implementation modes of the present invention. Rather, these embodiments are merely examples of devices and methods within the scope of the present invention.

Please refer to FIG. 1 , which is a schematic diagram of a memory testing device according to an embodiment of the present invention. In this embodiment, the memory testing device 100 includes a motherboard 110 , a testing board 130 and a processor 140 . The motherboard 110 has four memory slots ST1 - ST4 . The test board 130 is equipped with 8 memory chips DUT1-DUT8 to be tested. The present invention is not limited to the number of memory slots ST1 - ST4 and the number of memory chips DUT1 - DUT8 to be tested that can be mounted on the test board 130 in this embodiment. The test board 130 of the present invention can carry one or more memory chips to be tested. The number of memory slots of the present invention can be multiple. In this embodiment, the memory modules 120_1 , 120_2 , 120_3 and the test board 130 are respectively inserted into the memory slots ST1 - ST4 , so that the memory slots ST1 - ST4 are fully loaded. For example, the test board 130 is inserted into the memory socket ST1. The memory module 120_1 is inserted into the memory slot ST2, and so on. When the memory slots ST1 - ST4 are fully loaded, the memory testing device 100 can perform a full load test.

In this embodiment, the processor 140 is disposed on the motherboard 110 . When performing the full load test, the processor 140 disables the interleave access mode of the memory to enter the sequence access mode. In this embodiment, the processor 140 can be controlled to select the sequential access mode, so the interleaving operation is disabled, and the memory testing device 100 enters the sequential access mode. In some embodiments, the processor 140 can be controlled to disable the interleaved access mode, so that the memory testing device 100 enters the sequential access mode. In this embodiment, the processor 140 determines the test address range ADDR of the test board 130 . The test address range ADDR of the test board 130 is equal to the test address range ADDR of the memory chips DUT1 - DUT8 mounted on the test board 130 . That is to say, the processor 140 determines the test address range ADDR of the memory chips DUT1-DUT8 to be tested, and tests the memory chips DUT1-DUT8 to be tested based on the test address range ADDR, so as to obtain the Test results of DUT1~DUT8. The processor 140 is, for example, a central processing unit (Central Processing Unit, CPU), or other programmable general purpose or special purpose microprocessor (Microprocessor), digital signal processor (Digital Signal Processor, DSP), programmable A controller, application specific integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD) or other similar devices or a combination of these devices, which can load and execute computer programs.

It is worth mentioning here that when the memory slots ST1-ST4 are fully loaded, the processor 140 will make the memory testing device 100 enter the sequential access mode, and the memory chip under test will be tested based on the test address range ADDR DUT1~DUT8 are tested. The processor 140 can only perform a full load test on the memory chips DUT1 - DUT8 mounted on the test board 130 . In this way, compared with the current memory full-load test (please refer to "Background Technology"), this embodiment can greatly shorten the test time of the full-load test and greatly improve the test efficiency of the full-load test.

An embodiment of the test board 130 is further illustrated. In this embodiment, the test board 130 and the memory modules 120_1 , 120_2 , 120_3 are arranged along the first direction D1 . Further, the test board 130 and the memory modules 120_1 , 120_2 , 120_3 are sequentially arranged in parallel according to the first direction D1 . Therefore, compared with the memory modules 120_1 , 120_2 , 120_3 , the test board 130 is closer to the edge E of the motherboard 110 . In addition, as shown in FIG. 1 , the main board 110 is set upright. Therefore, the test board 130 is located above the memory modules 120_1 , 120_2 , 120_3 .

In this embodiment, the test board 130 has a first surface P1 and a second surface. The second face is opposite to the first face P1. The plane direction of the first plane P1 is substantially equal to the second direction D2. The second direction D2 is opposite to the first direction D1. The second side faces the memory modules 120_1, 120_2, 120_3. In this embodiment, the memory chips DUT1-DUT8 to be tested are loaded on the first surface P1. Therefore, based on the above settings, the memory testing device 100 can load the memory chips DUT1-DUT8 to be tested on the first surface P1 along the first direction D1, and unload the memory chips DUT1-DUT8 to be tested along the second direction D2. . For example, the memory testing apparatus 100 further includes a wafer moving mechanism. The wafer moving mechanism loads the memory wafers DUT1 - DUT8 to be tested onto the first surface P1 sequentially or simultaneously. In addition, the chip moving mechanism also unloads the memory chips DUT1-DUT8 to be tested along the second direction D2.

In this embodiment, the wiring configuration of the test board 130 is different from that of the memory modules 120_1 , 120_2 , 120_3 . Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a schematic diagram of a test board and a carrier board of a memory module according to an embodiment of the present invention. In this embodiment, the carrier board 121 of the memory modules 120_1 , 120_2 , 120_3 may be a conventional carrier board. Therefore, when the memory modules 120_1, 120_2, 120_3 are inserted into the memory slots ST2~ST4, the memory chips on the memory modules 120_1, 120_2, 120_3 are set to face the processor 140 and face away from the motherboard. 110 Edge E. The wiring configuration of the test board 130 in the third direction D3 is opposite to the wiring configuration of the carrier board 121 in the third direction D3. The third direction D3 is equal to the extending direction of the long side of the test board 130 . For example, the wiring configuration of the metal connections on the test board 130 in the third direction D3 is opposite to the wiring configuration of the metal connections on the carrier board 121 in the third direction D3. The wiring configuration of the pins on the test board 130 in the third direction D3 is opposite to the wiring configuration of the pins on the carrier board 121 in the third direction D3. In addition, the wiring configuration of the pin openings of the test board 130 in the third direction D3 is opposite to the wiring configuration of the pin openings of the carrier board 121 in the third direction D3. Therefore, when the test board 130 is inserted into the memory slot ST1 , the first surface P1 faces the edge E of the motherboard 110 . In this way, the memory testing device 100 can load the memory chips DUT1-DUT8 to be tested on the first surface P1 along the first direction D1, and unload the memory chips DUT1-DUT8 to be tested along the second direction D2.

Please refer to FIG. 1 and FIG. 3 at the same time. FIG. 3 is a flow chart of a memory testing method according to an embodiment of the present invention. The memory testing method of this embodiment is applicable to the memory testing device 100 . In this embodiment, in step S110, the test board 130 is equipped with the memory chips DUT1-DUT8 to be tested, and the memory modules 120_1, 120_2, 120_3 and the test board 130 are respectively inserted into the memory slots of the motherboard 110. ST1~ST4, so that the memory slots ST1~ST4 are fully loaded. The implementation details of step S110 can be sufficiently taught or explained in the previous embodiments, so they will not be repeated here.

In step S120, the interleaved access mode is turned off to enter the sequential access mode. The access mode of the memory includes, for example, an interleaved access mode and a sequential access mode. In the interleaved access mode, multiple memory blocks of the memory are accessed in an interleaved manner. The interleaved access mode is the access mode normally used by the memory. In the sequential access mode, multiple memory blocks of the memory are accessed sequentially based on the address sequence of the multiple memory blocks.

In this embodiment, the memory testing device 100 further includes a working unit 150 . The job unit 150 may be an element implementing a function of a Basic Input Output System (BIOS). The operation unit 150 records the access modes and test procedures of the interleaved access mode and the sequential access mode. In step S120, the processor 140 controls the operation unit 150 to disable the interleaved access mode to enter the sequential access mode. In sequential access mode. The processor 140 can sequentially test the memory modules 120_1, 120_2, 120_3 and the memory chips DUT1-DUT8 based on the addresses of the memory modules 120_1, 120_2, 120_3 and the memory chips DUT1-DUT8 to be tested. .

In this embodiment, the processor 140 determines the test address range ADDR of the test board 130 (that is, the test address range of the memory chips DUT1 - DUT8 to be tested) in step S130 . Since the test board 130 is designated to be inserted into the memory slot ST1. Therefore, the processor 140 can, for example, determine the test address range ADDR of the test board 130 from the memory slot ST1. In step S140, the processor 140 tests the memory chips DUT1-DUT8 to be tested based on the test address range ADDR to obtain test results of the memory chips DUT1-DUT8 to be tested. In step S140, when the memory slots ST1-ST4 are fully loaded, the processor 140 can sequentially test the memory chips DUT1-DUT8 based on the test address range ADDR and the address sequence of the memory chips DUT1-DUT8 to be tested. The addresses of the memory chips under test DUT1-DUT8 are tested to obtain the test results. The processor 140 does not test the addresses of the memory modules 120_1 , 120_2 , 120_3 . That is to say, in the full load test, the memory testing device 100 can only test the memory chips DUT1 - DUT8 to be tested. Compared with the current full-load test method in which the memory to be tested and the normal memory module are tested together, the test time of this embodiment can be greatly shortened. In this way, the memory testing device 100 can greatly improve the test efficiency of the full load test of the memory chips DUT1 - DUT8 to be tested.

For an example to describe the implementation details of steps S130 and S140, please refer to FIG. 1 , FIG. 3 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of address ranges according to an embodiment of the invention. In this embodiment, FIG. 4 shows the address range ADDR1~ADDR4. In this embodiment, the address range ADDR1 is represented as the address range of the memory module 120_1 . The address range ADDR2 is represented as the test address range of the memory chips DUT1 ˜ DUT8 to be tested (ie, the test address range ADDR shown in FIG. 1 ). The address range ADDR3 is represented as the address range of the memory module 120_2. The address range ADDR4 is represented as the address range of the memory module 120_3.

In step S130 , the processor 140 can determine the test address range ADDR2 of the memory chips DUT1 ˜ DUT8 to be tested, for example, through the memory slot ST1 . Similarly, the processor 140 can also determine the address ranges ADDR1 , ADDR3 , ADDR4 of the memory modules 120_1 ˜ 120_3 through the memory slots ST2 ˜ ST4 . After determining the address range ADDR2 of the memory chips DUT1-DUT8 to be tested, the processor 140 will sequentially process the memory chips to be tested based on the address range ADDR2 and the address sequence of the memory chips DUT1-DUT8 to be tested in step S140. The addresses of the chips DUT1-DUT8 are tested to obtain the test results of the memory chips DUT1-DUT8 to be tested.

In some embodiments, at least one of the memory modules 120_1 - 120_3 may be a memory module to be tested. When the memory slots ST1 - ST4 are fully loaded, the processor 140 can also perform a test on the memory module to be tested. For example, the memory module 120_1 is a memory module to be tested. The processor 140 can determine the address range ADDR1 of the memory module 120_1 under the full load condition, and test the memory module 120_1 based on the address range ADDR1 of the memory module 120_1 to obtain the corresponding 120_1 test results. In addition, under the condition of full load, the processor 140 can also perform the memory module 120_1 and the memory chip DUT1 based on the address range ADDR1 of the memory module 120_1 and the address range ADDR2 of the memory chips DUT1-DUT8 to be tested. ~DUT8 is tested to obtain the test results of the memory module 120_1 and the test results of the memory chips DUT1-DUT8 to be tested.

In summary, under full load conditions, the memory testing device and memory testing method of the present invention will be controlled to enter the sequential access mode, determine the test address range of at least one memory chip to be tested, and At least one memory chip to be tested is tested. The memory testing device and memory testing method of the present invention can only test the memory chip to be tested mounted on the test board in the sequential access mode. In this way, the present invention can greatly improve the test efficiency of the full load test of the memory to be tested. In addition, the present invention makes the test board closer to the edge of the main board and allows the main board to be set upright. The wiring configuration of the test board is the opposite of that of a conventional carrier board. Therefore, the present invention can load the memory chip to be tested onto the test board along the first direction, and unload the memory chip to be tested from the test board.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100:Memory test device 110: Motherboard 120_1, 120_2, 120_3: memory module 121: carrier board 130: Test board 140: Processor 150: Operation unit D1: the first direction D2: Second direction D3: Third direction DUT1~DUT8: memory chips to be tested E: edge ST1~ST4: memory slot P1: the first side ADDR: test address range ADDR1~ADDR4: address range S110, S120, S130, S140: steps

FIG. 1 is a schematic diagram of a memory testing device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a test board and a carrier board of a memory module according to an embodiment of the invention. FIG. 3 is a flow chart of a memory testing method according to an embodiment of the present invention. FIG. 4 is a schematic diagram of address ranges according to an embodiment of the invention.

100:Memory test device

110: Motherboard

120_1, 120_2, 120_3: memory module

130: Test board

140: Processor

150: Operation unit

D1: the first direction

D2: Second direction

DUT1~DUT8: memory chips to be tested

E: edge

ST1~ST4: memory slot

P1: the first side

ADDR: test address range

Claims (6)

A memory testing device, comprising: a test board configured to carry at least one memory chip to be tested; a motherboard with a plurality of memory slots, wherein at least one memory module and the test board are respectively inserted into the among the plurality of memory slots, such that the plurality of memory slots are fully loaded; and a processor, disposed on the motherboard, is configured to: disable interleaved access mode to enter sequential access mode, determining the test address range of the at least one memory chip to be tested, and performing the test on the at least one memory chip under the full load condition based on the test address range of the at least one memory chip to be tested The chip is tested to obtain a test result corresponding to the at least one memory chip to be tested, wherein compared with the at least one memory module, the test board is closer to the edge of the motherboard, and the test The board has a first face and a second face opposite to the first face, the at least one memory chip to be tested is loaded on the first face, and the second face faces the at least one memory die group, wherein the test board and the at least one memory module are arranged along a first direction, wherein the memory testing device loads the at least one memory chip to be tested on the first direction along the first direction the first surface, and unload the at least one memory chip to be tested loaded on the first surface along a second direction opposite to the first direction. The memory testing device as claimed in claim 1, wherein the main board is set upright such that the testing board is located above the at least one memory module. The memory testing device according to claim 1, wherein: the wiring configuration of the test board in the third direction is opposite to the wiring configuration of the carrier board of the at least one memory module in the third direction, and the The third direction is equal to the extending direction of the long side of the test board. A memory testing method, comprising: making the test board carry at least one memory chip to be tested, and inserting at least one memory module and the test board into a plurality of memory slots of the motherboard, so that the A plurality of memory slots are fully loaded, wherein the test board and the at least one memory module are arranged along a first direction, wherein compared with the at least one memory module, the test board is smaller Close to the edge of the motherboard, the test board has a first face and a second face opposite to the first face, the at least one memory chip to be tested is loaded on the first face, and the The second face faces the at least one memory module; the at least one memory chip to be tested is loaded on the first face along the first direction; along the second direction opposite to the first direction Unloading the at least one memory chip under test loaded on the first surface; closing the interleaved access mode to enter the sequential access mode; determining the test address range of the at least one memory chip under test; and based on the test address range of the at least one memory chip to be tested in the full The at least one memory chip to be tested is tested under loading conditions to obtain a test result corresponding to the at least one memory chip to be tested. The memory testing method according to claim 4, further comprising: setting the motherboard upright so that the testing board is located above the at least one memory module. The memory testing method according to claim 4, further comprising: providing the test board, wherein the wiring configuration of the test board in the third direction is opposite to that of the carrier board of the at least one memory module in the first direction Wiring configurations in three directions, and wherein the third direction is equal to the extending direction of the long side of the test board.

Images