TWI786925B - Photo sensor device and method of manufacturing the same - Google Patents

Abstract

A photo sensor device is provided in the present invention, including a metal bottom gate, a gate dielectric layer on the metal bottom gate, a IGZO channel layer on the gate dielectric layer, a SnO capping layer on the IGZO channel layer, and source and drain respectively on two sides of the IGZO channel layer and not covering the SnO capping layer.

Description

Light sensing element and manufacturing method thereof

The present invention generally relates to a photo-sensing device and a manufacturing method thereof, and more particularly, to a photo-sensing device for visible light sensing and integrated with CMOS process.

With the rapid and continuous evolution in thin film transistors (TFTs) technology over the past few years, TFT display panels have developed applications other than screens, such as flexible electronics, biomedical sensors, non-volatile memory, Or a three-dimensional chip, etc. Among these innovative applications, the most interesting subject is TFT liquid crystal displays (TFT-LCDs) as light sensors. This type of sensor can be integrated into the display panel of a handheld consumer electronic product to realize light sensing functions such as ambient light sensing, image scanning, and touch panel. In recent years, the use of amorphous metal oxides as active layer materials in photo-sensing devices, especially amorphous indium gallium zinc oxide (α-IGZO), has attracted a lot of attention. Different from the poor carrier transport properties of traditional amorphous silicon (α-Si) TFTs or the poor large-area uniformity of polycrystalline silicon (poly-Si) TFTs, amorphous InGaZnO has high electron mobility High efficiency, good uniformity, low manufacturing cost, and low process temperature, etc., it is very suitable as a material for sensing arrays.

Nevertheless, the disadvantage of amorphous InGaZnO material is its wide energy gap, so in terms of light sensing, its absorption of visible light, infrared light or long-wavelength electromagnetic wave bands The efficiency is not good enough to meet the response of the ambient light sensing element to the visible spectrum. In addition, current photo-sensing devices using amorphous InGaZnO as the active layer are rarely integrated with CMOS logic processes. Therefore, how to improve the photoresponse of the amorphous InGaZn material to the visible light band, and integrate it with the CMOS process, so as to simplify the overall process and reduce the cost, and at the same time improve the control of the logic circuit to the photo-sensing array, is an important issue in this field. Technicians still need to continue to research and develop topics.

According to the above-mentioned state of the art, the present invention proposes a photo-sensing element, which is characterized in that the top metal layer in the CMOS process is used as the bottom electrode, and the photo-sensing array can be simply integrated into the CMOS process. Furthermore, a SnO covering layer is added to the photo-sensing element, which can effectively increase the responsivity of the photo-sensing element to the visible light band.

One aspect of the present invention is to provide a light sensing element, comprising a metal lower gate, a gate dielectric layer on the metal lower gate, an indium gallium zinc oxide channel layer on the gate dielectric layer, A SnO capping layer is located on the InGaZnO channel layer, and a source and a drain are respectively located on two sides of the InGaZnO channel layer without covering the SnO capping layer.

Another aspect of the present invention is to provide a method for manufacturing a light sensing element integrated with a complementary metal oxide semiconductor (CMOS) process, the steps of which include: providing a substrate, the substrate is provided with a transistor element, a dielectric layer, and a metal interconnection layer; forming a passivation layer on the metal interconnection layer; forming a first groove in the passivation layer, wherein the bottom of the first groove retains part of the passivation layer; An indium gallium zinc oxide channel layer and a tin oxide covering layer are sequentially formed on the passivation layer at the bottom of the groove; and a source electrode and a drain electrode are respectively formed on both sides of the indium gallium zinc oxide channel layer, and the The source and the drain are not covered by the SnO capping layer.

These and other objects of the present invention will become more apparent to the reader after reading the following detailed description of the preferred embodiment which is depicted in various drawings and drawings.

100: Light sensing element

102: metal lower gate

104: gate dielectric layer

106: Indium Gallium Zinc Oxide channel layer

108: Tin oxide covering layer

110: source/drain

200: light sensing element

201: Base

202: top metal layer

203: Intermetal dielectric layer

204: passivation layer

205: Groove

206: InGaZn channel layer

208: Tin oxide covering layer

210: source/drain

211: External structure

This specification contains drawings and constitutes a part of this specification, so that readers can have a further understanding of the embodiments of the present invention. The drawings depict some embodiments of the invention and together with the description herein explain its principles. In these illustrations: Figure 1 is a schematic cross-sectional view of a light sensing element according to a preferred embodiment of the present invention; and Figures 2 to 5 are diagrams of a light sensing element according to a preferred embodiment of the present invention Schematic cross-section of the fabrication process.

It should be noted that all the diagrams in this manual are illustrations in nature. For the sake of clarity and convenience of illustration, the size and proportion of each component in the diagram may be exaggerated or reduced. Generally speaking, the The same reference symbols will be used to designate corresponding or similar component features in modified or different embodiments.

Exemplary embodiments of the present invention will now be described in detail below, which will illustrate the described features with reference to the accompanying drawings for readers to understand and achieve technical effects. Readers will understand that the description herein is by way of illustration only and is not intended to limit the present case. Various embodiments of the present application and various features that do not conflict with each other in the embodiments can be combined or rearranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention will be understood by those skilled in the art and are intended to be included within the scope of the present invention.

Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad way so that "on" not only means "directly on "something "on" and also includes the meaning of being "on" something with an intervening feature or layer in between, And "on" or "over" not only means "on" something "on" or "above" but can also include its "on" something "on" or "above" and Meaning that there are no intervening features or layers in between (ie, directly on something). In addition, spatial relative terms such as "under", "beneath", "lower", "above", "upper", etc. may be used herein for convenience of description to describe the relationship between one element or feature and another. The relationship of one or more elements or features as shown in the drawings.

As used herein, the term "substrate" refers to a material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic or a sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers may extend horizontally, vertically and/or along sloped surfaces. A substrate can be a layer, can comprise one or more layers, and/or can have one or more layers thereon, above, and/or below. Layers may include multiple layers. For example, interconnect layers may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Readers can usually understand a term at least in part from its usage in context. For example, the term "one or more" as used herein may be used in the singular to describe any feature, structure or characteristic or may be used in the plural to describe a combination of features, structures or characteristics, depending at least in part on the context. Similarly, depending at least in part on the context, such as "one", "one Terms such as "a", "the" or "said" may likewise be read to convey singular usage or to convey plural usage. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on context.

Readers can better understand that when words such as "comprising" and/or "comprising" are used in this specification, it clearly states the existence of the stated features, regions, integers, steps, operations, elements and/or components, but does not The existence or addition of one or more other features, regions, integers, steps, operations, elements, components and/or combinations thereof is not excluded.

First, please refer to FIG. 1 , which is a schematic cross-sectional view of a light sensing element 100 according to a preferred embodiment of the present invention. As shown in the figure, the lowest layer of the light sensing element 100 is a metal lower gate 102 . In a preferred embodiment of the present invention, the material of the lower metal gate 102 is a conductive metal, such as copper (Cu). The advantage of using copper as the material of the metal lower gate 102 is that the metal interconnection structure made of copper has a simple manufacturing process and low cost, which is conducive to the miniaturization of the photo-sensing array, and the interconnection delay of the metal material is low, which is beneficial High-speed signal transmission. On the other hand, in a preferred embodiment of the present invention, the metal lower gate 102 can be a metal interconnection layer produced in the CMOS back-end process (BEOL), such as the top metal layer (top metal), which can receive the The signal from the logic circuit is used to control the operation of the photo-sensing element 100, which is beneficial to the process integration of the photo-sensing element and the CMOS logic circuit. A gate dielectric layer 104 is disposed above the lower metal gate 102 to isolate the conduction path between the lower metal gate 102 and the upper channel layer. The material of the gate dielectric layer 104 may be silicon nitride (Si ₃ N ₄ ). Silicon nitride has a high dielectric constant and a high breakdown voltage, which can effectively suppress the current breakdown of the light sensing element. In addition, silicon nitride has a high refractive index, which can also serve as an anti-reflection layer in the light sensing element. In a preferred embodiment of the present invention, the gate dielectric layer 104 may be a passivation layer covering the top metal layer in a CMOS back end of line (BEOL).

In a preferred embodiment of the present invention, the top of the gate dielectric layer 104 is a light sensing element 100 channel layers. The material of the channel layer is indium gallium zinc oxide (IGZO), especially amorphous indium gallium zinc oxide (α-IGZO), which has high electron mobility, good uniformity, low manufacturing cost, and Due to its advantages such as low process temperature, it is very suitable as a material for sensing arrays. However, the disadvantage of InGaZnO material is that it has a wide energy gap (usually greater than 3eV), so in terms of light sensing, its absorption rate for visible light, infrared light, or long-wavelength electromagnetic wave bands (less than 3eV) is not good. Good, but cannot meet the response of the ambient light sensing element to the visible spectrum.

For this, in the embodiment of the present invention, a capping layer 108 made of tin oxide (SnO) is further disposed on the InGaZn channel layer 106 . SnO is an excellent p-type oxide semiconductor material, which has good absorption properties for visible light. The SnO capping layer 108 serves as a light absorbing layer in the present invention, which can improve the response of the InGaZnO channel layer 106 to the visible light band. For example, the energy gap of the tin oxide material is about 0.7eV, and the energy gap of the amorphous indium gallium zinc oxide material is about 3.2eV (electron volts). On the zinc channel layer 106 , the indium gallium zinc oxide channel layer 106 can generate a photoelectric reaction to light with energy less than 3.2 eV. Furthermore, the conduction band energy level (4.3eV~5.6eV) of the tin oxide capping layer 108 is higher than the conduction band energy level (4.4eV~7.4eV) of the indium gallium zinc oxide channel layer 106, so the When the layer 108 absorbs light with a longer wavelength, the electron hole pairs generated by it can easily migrate to the conduction band of the indium gallium zinc oxide channel layer 106 via the conduction band of the tin oxide capping layer 108 to serve as indium oxide Carriers in the GaZn channel layer 106 . In addition, when there is no light, the photoexcited electrons accumulated between the SnO capping layer 108 and the InGaZn channel layer 106 interface can immediately recombine with the holes in the SnO capping layer 108, which can improve The state recovery speed of the light sensing element 100 makes the sensing of the light sensing element more sensitive.

Referring again to FIG. 1 , source/drain electrodes 110 are respectively disposed on the IGaZn channel layer 106 on both sides of the SnO capping layer 108 . The material of the source/drain 110 can be aluminum (Al) or molybdenum (Mo), so that Using such materials as electrodes, the device will have a smaller threshold voltage, a larger carrier mobility, and a larger current-on-off ratio. In the embodiment of the present invention, the source/drain 110 is only located on the IGaZn channel layer 106 and does not cover the SnO capping layer 108 . Disposing the aluminum source/drain electrodes 110 on both sides of the SnO capping layer 108 helps to concentrate the incident light on the two photoelectric layers to enhance the photoelectric effect. In addition, a titanium barrier layer or a titanium/titanium nitride barrier layer can be provided between the source/drain electrode 110 and the adjacent InGaZn channel layer 106, the Sn2O capping layer 108, and the gate dielectric layer 104. A barrier layer (not shown) prevents metal particles in the source/drain 110 from diffusing into these layer structures.

Now please refer to FIG. 2 to FIG. 5 , which are cross-sectional schematic diagrams of the manufacturing process of the light sensing element according to a preferred embodiment of the present invention. In a preferred embodiment of the present invention, the light-sensing element of the present invention is integrated in a CMOS process, and is characterized in that the metal interconnection layer, especially the top metal layer (top metal) produced in the CMOS back-end process is used. , used as the metal lower gate of the light sensing element, and a passivation layer (passivation) is used as the gate dielectric layer between the gate of the light sensing element and the channel layer.

Please refer to Figure 2 first. A substrate 201 is provided on which the fabrication of various components in the CMOS front-end process (FEOL) and back-end process (BEOL) has been completed, including transistor elements, interlayer dielectric layers, intermetal dielectric layers, and metal interconnection structures, etc. part. Since the CMOS front-end process and back-end process and the fabrication of these components are known technologies, the relevant details will be omitted here. After the top metal layer 202 is fabricated, a passivation layer 204 is then formed on the top metal layer 202 and the surrounding IMD layer 203 . The material of the passivation layer 204 can be silicon nitride (Si ₃ N ₄ ), which can use atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma assisted chemical vapor deposition ( PECVD) and other methods, among which the PECVD method is a low-temperature process, which is more suitable for use after the CMOS back-end process. In a preferred embodiment of the present invention, the passivation layer 204 is not only used as the passivation layer in the CMOS process, but also serves as the gate dielectric layer of the light sensing element of the present invention.

Then please refer to Figure 3. After the passivation layer 204 is formed, a photolithography process is performed to form a pattern of grooves 205 in the passivation layer 204 . In a preferred embodiment of the present invention, the groove 205 is not only used as the connecting opening of the top metal layer 202, but also serves as a space for setting the light sensing element of the present invention. A pattern of sensing arrays may appear in the viewing angle. It should be noted that since the passivation layer 204 is also used as the gate dielectric layer of the photo-sensing element in the present invention, a certain thickness of the passivation layer 204 will be left at the bottom of the part of the groove 205 as the space of the photo-sensing element, which will not be exposed. out of the top metal layer 202 below. Also because different grooves have different depths in embodiments, the grooves 205 can be formed using multiple photolithography processes.

Please refer to Figure 4. After the groove 205 is formed, an InGaZn-channel layer 206 and a SnO capping layer 208 are sequentially formed in the groove 205 as a space for the photo-sensing element. In the embodiment of the present invention, the channel layer 206 of indium gallium zinc oxide is preferably made of amorphous indium gallium zinc oxide (α-IGZO), which can be formed by using a low-temperature radio frequency sputtering (RF-sputter) process, so as to have a higher Great carrier mobility. The stannous oxide covering layer 208 can also be formed by using a low-temperature radio frequency sputtering (RF-sputter) process, using a tin target or a stannous oxide target. In this way, the stannous oxide covering layer 208 can have a lower energy gap. It helps to absorb the spectrum with longer wavelength (450~750nm). Spaces are reserved on the IGaZn channel layer 206 on both sides of the SnO capping layer 208 for disposing source/drain electrodes in subsequent manufacturing processes. No InGaZn channel layer 206 and Sn2O capping layer 208 are formed in the groove 205 as the opening of the top metal layer 202 .

Please refer to Figure 5. After the IGaZn channel layer 206 and the SnO capping layer 208 are formed, the source/drain 210 is then formed on the IGaZn channel layer 206 . The material of the source/drain 210 can be aluminum (Al) or molybdenum (Mo), which can also be formed by a low-temperature radio frequency sputtering process to improve conductivity. It should be noted that in the embodiment of the present invention, the source/drain 210 will not cover the SnO capping layer 208 therebetween, and the above-mentioned steps of forming the source/drain 210 can also be used as metal interconnects at the same time. An external connection structure 211 connected to the top metal layer 202, such as an aluminum pad, is formed in the groove 205 of the external opening of the connection layer, so that the material of the connection external structure 211 is the same as that of the source/drain electrode 210 . In addition, before forming the source/drain 210 and the external structure 211, a titanium barrier layer or a titanium/titanium nitride barrier layer (not shown) may be formed on the surface of the InGaZn channel layer 206. ), to prevent the metal particles in the source/drain 210 and the outer structure 211 from diffusing into the adjacent layer structure. Thus, the above-mentioned top metal layer 202 , passivation layer 204 , InGaZn channel layer 206 , Sn2O capping layer 208 and source/drain 210 together constitute the light sensing element 200 of the present invention.

Based on the description of the above-mentioned embodiments, the structure of the photo-sensing element and its manufacturing method proposed by the present invention are characterized in that the top metal layer in the CMOS process is used as the bottom electrode, and the photo-sensing array can be simply integrated into the CMOS process for fabrication, and Adding a SnO covering layer to the photo-sensing element can effectively increase the responsivity of the photo-sensing element to the visible light band, which is a novel and progressive invention.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Light sensing element

102: metal lower gate

104: gate dielectric layer

106: Indium Gallium Zinc Oxide channel layer

108: Tin oxide covering layer

110: source/drain

Claims (9)

A light sensing element, comprising: a metal lower gate, wherein the metal lower gate is a part of the top metal layer of a copper metal interconnection in a complementary metal oxide semiconductor (CMOS); a gate dielectric layer, located on the metal lower gate; an indium gallium zinc oxide channel layer located on the gate dielectric layer; a tin protooxide capping layer located on the indium gallium zinc oxide channel layer; and a source electrode and a drain electrode respectively located on the The two sides of the InGaZn channel layer are not covered by the SnO capping layer. The photo-sensing device according to claim 1, wherein the gate dielectric layer is a part of the passivation layer on the top metal layer in the complementary metal oxide semiconductor (CMOS). According to the photo-sensing element described in claim 2, the material of the gate dielectric layer includes silicon nitride. The photo-sensing device as described in item 1 of the scope of the present invention, wherein the material of the source and the drain is the same as that of an outer structure connected to the top metal layer in the complementary metal oxide semiconductor (CMOS). The light sensing element as described in claim 4, wherein the material includes aluminum. A method for manufacturing a photo-sensing element integrated with a complementary metal oxide semiconductor (CMOS), comprising: providing a substrate on which a transistor element, a dielectric layer, and a metal interconnection layer are arranged; on the metal forming a passivation layer on the interconnection layer; forming a first groove in the passivation layer, wherein the bottom of the first groove retains part of the passivation layer; sequentially forming on the passivation layer at the bottom of the first groove An indium gallium zinc oxide channel layer and a tin oxide capping layer; and a source and a drain are respectively formed on both sides of the indium gallium zinc oxide channel layer, and the source and the drain do not cover the oxide Sn overlay. The method for manufacturing a photo-sensing element integrated with a complementary metal oxide semiconductor (CMOS) as described in item 6 of the scope of the patent application further includes: forming a second groove in the passivation layer, wherein the second groove The bottom of the metal interconnection layer is exposed; and an outer connection structure is formed in the second groove to connect the metal interconnection layer, wherein the material of the outer connection structure is the same as that of the source electrode and the drain electrode. According to the method for manufacturing a photo-sensing device integrated with a complementary metal oxide semiconductor (CMOS) as described in claim 7, the material of the connecting structure and the material of the source and the drain include aluminum. According to the method for manufacturing a photo-sensing element integrated with a complementary metal oxide semiconductor (CMOS) as described in item 6 of the scope of the patent application, the material of the passivation layer includes silicon nitride.

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