TWI786813B - Method of manufacturing floating gate - Google Patents

Abstract

A method of manufacturing a floating gate including the following steps is provided. A substrate is provided. First isolation structures are formed in the substrate. The top surface of the first isolation structure is higher than the top surface of the substrate. A dielectric layer is formed on the substrate between two adjacent first isolation structures. The top surface of the dielectric layer is flush with the top surface of the first isolation structure. A floating gate material layer is formed on the first isolation structure and the dielectric layer. The floating gate material layer is patterned to form a floating gate on the dielectric layer. The width of the floating gate is greater than the width of the top surface of the substrate between the two adjacent first isolation structures.

Description

Manufacturing method of floating gate

Embodiments of the present invention relate to a method of manufacturing a semiconductor structure, and in particular to a method of manufacturing a floating gate.

Because non-volatile memory (non-volatile memory) has the advantage that the stored data will not disappear after power failure, so many electrical products must have this kind of memory in order to maintain the normal operation of the electrical products when they are turned on. In a non-volatile memory that uses a floating gate to store charge, the shape of the floating gate will affect the electrical performance of the memory device. Therefore, how to form a floating gate with a better shape to improve the electrical performance of the memory device is a goal of continuous efforts.

The invention provides a method for manufacturing a floating gate, which can improve the electrical performance of a memory element.

The invention proposes a method for manufacturing a floating gate, which includes the following steps. Provide the base. A plurality of first isolation structures are formed in the substrate. The top surface of the first isolation structure is higher than the top surface of the base. A dielectric layer is formed on the substrate between two adjacent first isolation structures. The top surface of the dielectric layer is flush with the top surface of the first isolation structure. A floating gate material layer is formed on the first isolation structure and the dielectric layer. The layer of floating gate material is patterned to form a floating gate on the dielectric layer. The width of the floating gate is greater than the width of the top surface of the substrate between two adjacent first isolation structures.

According to an embodiment of the present invention, in the above method of manufacturing the floating gate, the method for forming the plurality of first isolation structures may include the following steps. A cushion layer is formed on the substrate. A plurality of trenches are formed in the pad and substrate. A plurality of first isolation structures are formed in the plurality of trenches.

According to an embodiment of the present invention, the above-mentioned manufacturing method of the floating gate may further include the following steps. After forming the plurality of first isolation structures, the pad layer is removed.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the floating gate, the height of the first isolation structure can be reduced simultaneously during the process of removing the pad layer.

According to an embodiment of the present invention, in the manufacturing method of the floating gate, the dielectric layer is formed by, for example, a thermal oxidation method.

According to an embodiment of the present invention, in the above method of manufacturing the floating gate, the floating gate can be further formed on a portion of the first isolation structure.

According to an embodiment of the present invention, in the manufacturing method of the floating gate, the floating gate may have a flat bottom surface.

According to an embodiment of the present invention, in the manufacturing method of the floating gate, the cross-sectional shape of the floating gate may be a rectangle.

According to an embodiment of the present invention, the above-mentioned manufacturing method of the floating gate may further include the following steps. Before patterning the floating gate material layer, a hard mask layer is formed on the floating gate material layer. The hard mask layer is patterned to form a patterned hard mask layer. After the hard mask layer is patterned, the floating gate material layer is patterned to form an opening exposing part of the first isolation structure.

According to an embodiment of the present invention, the above-mentioned manufacturing method of the floating gate may further include the following steps. A second isolation structure is formed in the opening, wherein the second isolation structure may be located on the first isolation structure. The height of the second isolation structure is reduced so that the top surface of the second isolation structure is lower than the top surface of the floating gate. Remove the patterned hardmask layer.

Based on the above, in the manufacturing method of the floating gate proposed by the present invention, since the top surface of the dielectric layer is flush with the top surface of the first isolation structure, the subsequently formed floating gate can have a flat bottom surface. In addition, the width of the floating gate is greater than the width of the top surface of the substrate between two adjacent first isolation structures, that is, the width of the floating gate can be greater than the width of the top surface of the substrate in the active region. Since the floating gate can have a flat bottom surface, and the width of the floating gate can be larger than the width of the top surface of the substrate in the active region, the floating gate can have a better shape, thereby improving the memory device. electrical performance. For example, leakage current can be reduced, and gate coupling ratio, operating speed, and reliability (eg, data retention capacity and endurance) can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

1A to 1G are cross-sectional views of a manufacturing process of a floating gate according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 100 is provided. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. Next, a pad layer 102 may be formed on the substrate 100 . The cushion layer 102 can be a single-layer structure or a multi-layer structure. The material of the pad layer 102 is, for example, silicon oxide, silicon nitride, polysilicon or a combination thereof. In this embodiment, the cushion layer 102 can be a multi-layer structure including the cushion layer 104 and the cushion layer 106 , but the invention is not limited thereto. For example, pad layer 104 may be a pad oxide layer, and pad layer 106 may be a pad nitride layer.

Then, a plurality of trenches T may be formed in the pad layer 102 and the substrate 100 . In some embodiments, the trench T is formed by, for example, removing a portion of the pad layer 102 and a portion of the substrate 100 through a lithography process and an etching process (eg, a dry etching process).

Next, a plurality of isolation structures 108 may be formed in the plurality of trenches T. Referring to FIG. Thereby, a plurality of isolation structures 108 can be formed in the substrate 100 . The top surface TS2 of the isolation structure 108 is higher than the top surface TS1 of the substrate 100 . In addition, the isolation structure 108 can define an active area AA in the substrate 100 . The isolation structure 108 may be a shallow trench isolation (STI). The material of the isolation structure 108 is silicon oxide, for example. The method for forming the isolation structure 108 may include the following steps. First, an isolation material layer (not shown) filling the trench T may be formed. Next, the pad layer 106 can be used as a termination layer to remove the isolation material layer outside the trench T to form the isolation structure 108 . The method for removing the isolation material layer outside the trench T is, for example, chemical mechanical polishing (CMP) method.

Referring to FIG. 1B , after the plurality of isolation structures 108 are formed, the pad layer 102 may be removed. In addition, during the process of removing the pad layer 102 , the height of the isolation structure 108 can be reduced simultaneously. In addition, after reducing the height of the isolation structure 108 , the top surface TS2 of the isolation structure 108 is higher than the top surface TS1 of the substrate 100 . The removal method of the pad layer 102 is, for example, a dry etching method, a wet etching method or a combination thereof. In some embodiments, the pad layer 106 may be removed by dry etching to reduce the height of the isolation structure 108, and then the pad layer 104 may be removed by wet etching to reduce the height of the isolation structure 108, but the present invention does not This is not the limit.

Referring to FIG. 1C , a dielectric layer 110 is formed on the substrate 100 between two adjacent isolation structures 108 . The top surface TS3 of the dielectric layer 110 is flush with the top surface TS2 of the isolation structure 108 . The dielectric layer 110 can be used as a tunneling dielectric layer. The material of the dielectric layer 110 is, for example, silicon oxide. The forming method of the dielectric layer 110 is, for example, a thermal oxidation method.

Referring to FIG. 1D , a floating gate material layer 112 is formed on the isolation structure 108 and the dielectric layer 110 . The material of the floating gate material layer 112 is, for example, doped polysilicon, undoped polysilicon or a combination thereof. The method for forming the floating gate material layer 112 is, for example, chemical vapor deposition.

Next, a hard mask layer 114 may be formed on the floating gate material layer 112 . The material of the hard mask layer 114 is, for example, silicon nitride. The hard mask layer 114 is formed by chemical vapor deposition, for example.

Referring to FIG. 1E , the hard mask layer 114 can be patterned to form a patterned hard mask layer 114 a. In addition, after the hard mask layer 114 is patterned, the floating gate material layer 112 is patterned to form the floating gate 112a on the dielectric layer 110, and a portion of the isolation structure 108 is exposed. Open OP. In addition, the floating gate 112 a can be further formed on part of the isolation structure 108 . In some embodiments, the floating gate 112a may be formed on portions of the isolation structures 108 on both sides of the floating gate 112a. In some embodiments, the hard mask layer 114 and the floating gate material layer 112 may be patterned by a lithography process and an etching process (eg, dry etching process).

The width W2 of the floating gate 112 a is greater than the width W1 of the top surface TS1 of the substrate 100 between two adjacent isolation structures 108 . That is, the width W2 of the floating gate 112 a may be greater than the width W1 of the top surface TS1 of the substrate 100 in the active area AA. In addition, since the top surface TS3 of the dielectric layer 110 is flush with the top surface TS2 of the isolation structure 108 , the floating gate 112 a may have a flat bottom surface BS1 . In some embodiments, the cross-sectional shape of the floating gate 112a may be a rectangle.

Referring to FIG. 1F , an isolation structure 116 may be formed in the opening OP, wherein the isolation structure 116 may be located on the isolation structure 108 . The width W4 of the bottom surface BS2 of the isolation structure 116 may be smaller than the width W3 of the top surface TS2 of the isolation structure 108 . The material of the isolation structure 116 is, for example, silicon oxide. The method for forming the isolation structure 116 may include the following steps. First, an isolation material layer (not shown) filling the opening OP may be formed. Next, the isolation structure 116 can be formed by removing the isolation material layer outside the opening OP by using the patterned hard mask layer 114 a as a termination layer. The removal method of the isolation material layer outside the opening OP is, for example, a chemical mechanical polishing method.

Referring to FIG. 1G , the height of the isolation structure 116 can be reduced so that the top surface TS5 of the isolation structure 116 is lower than the top surface TS4 of the floating gate 112 a. A method for reducing the height of the isolation structure 116 is, for example, performing a dry etching process on the isolation structure 116 .

Next, the patterned hard mask layer 114a may be removed. The removal method of the patterned hard mask layer 114 a is, for example, a wet etching method. In addition, subsequent steps for forming the memory device (eg, forming an interpolysilicon dielectric (IPD) (not shown) and a control gate (not shown) in the opening OP and on the floating gate 112a ) is well known to those with ordinary knowledge in the technical field, and will not be described here.

Based on the above-mentioned embodiments, it can be seen that in the manufacturing method of the floating gate 112a, since the top surface TS3 of the dielectric layer 110 is flush with the top surface TS2 of the isolation structure 108, it is subsequently formed on the dielectric layer 110 and the isolation structure 108. The floating gate 112a may have a flat bottom surface BS1. In addition, the width W2 of the floating gate 112a is greater than the width W1 of the top surface TS1 of the substrate 100 between two adjacent isolation structures 108, that is, the width W2 of the floating gate 112a may be greater than that of the substrate 100 in the active area AA. The width W1 of the top surface TS1. Since the floating gate 112a may have a flat bottom surface BS1, and the width W2 of the floating gate 112a may be larger than the width W1 of the top surface TS1 of the substrate 100 in the active area AA, the floating gate 112a may have a better shape, which in turn can improve the electrical performance of the memory device. For example, leakage current can be reduced, and gate coupling ratio, operating speed, and reliability (eg, data retention and endurance) can be improved.

To sum up, in the manufacturing method of the floating gate in the above embodiment, since the floating gate can have a flat bottom surface, and the width of the floating gate can be greater than the width of the top surface of the substrate in the active region, Therefore, the electrical performance of the memory device can be improved.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: base

102, 104, 106: Cushion

108,116: Isolation structure

110: dielectric layer

112: gate material layer

112a: floating gate

114: hard mask layer

114a: Patterned hard mask layer

AA: active area

BS1, BS2: bottom surface

OP: opening

T: Ditch

TS1~TS5: top surface

W1~W4: Width

1A to 1G are cross-sectional views of a manufacturing process of a floating gate according to an embodiment of the present invention.

100: base

108,116: Isolation structure

110: dielectric layer

112a: floating gate

AA: active area

BS1, BS2: bottom surface

OP: opening

TS1~TS5: top surface

W1~W4: Width

Claims (9)

A method for manufacturing a floating gate, comprising: providing a substrate; forming a plurality of first isolation structures in the substrate, wherein the top surfaces of the first isolation structures are higher than the top surfaces of the substrate; A tunnel dielectric layer is formed on the substrate between the two first isolation structures, wherein the top surface of the tunnel dielectric layer is flush with the top surface of the first isolation structure; forming a floating gate material layer on the isolation structure and the tunnel dielectric layer; and patterning the floating gate material layer to form a floating gate, wherein the floating gate has a flat bottom surface on the tunnel dielectric layer and the first isolation structure, and the width of the floating gate is greater than the width of the top surface of the substrate between two adjacent first isolation structures . The method for manufacturing a floating gate according to claim 1, wherein the method for forming a plurality of first isolation structures includes: forming a pad layer on the substrate; forming a plurality of pad layers in the pad layer and the substrate trenches; and forming a plurality of the first isolation structures in the plurality of trenches. The method for manufacturing a floating gate according to claim 2 further includes: removing the pad layer after forming a plurality of the first isolation structures. The method for manufacturing a floating gate according to claim 3, wherein the height of the first isolation structure is simultaneously reduced during the process of removing the pad layer. The method for manufacturing a floating gate according to Claim 1, wherein the method for forming the tunnel dielectric layer includes a thermal oxidation method. The method for manufacturing a floating gate as claimed in claim 1, wherein the floating gate is further formed on a part of the first isolation structure. The method for manufacturing a floating gate as claimed in claim 1, wherein the cross-sectional shape of the floating gate includes a rectangle. The method for manufacturing a floating gate according to claim 1, further comprising: forming a hard mask layer on the floating gate material layer before patterning the floating gate material layer; and patterning the hard mask layer to form a patterned hard mask layer, wherein after patterning the hard mask layer, patterning the floating gate material layer to form exposed part of the opening of the first isolation structure. The method for manufacturing a floating gate according to claim 8, further comprising: forming a second isolation structure in the opening, wherein the second isolation structure is located on the first isolation structure; lowering the first isolation structure the height of two isolation structures so that the top surface of the second isolation structure is lower than the top surface of the floating gate; and removing the patterned hard mask layer.

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