TWI785429B - semiconductor memory device - Google Patents

Abstract

The invention provides a semiconductor memory device capable of improving heat dissipation efficiency. The semiconductor memory device has a main body, a memory, a controller and a plurality of terminals. The plurality of terminals include a plurality of signal terminals for transmitting signals, and are exposed on the first surface of the body. A plurality of terminals form at least the first row and the second row. The first row includes a plurality of terminals, which are equal to the position closer to the first end edge than the second end edge of the body, and are arranged at intervals in the first direction. The second row includes a plurality of terminals, which are equal to the position closer to the second end edge than the first end edge of the body, and are arranged at intervals in the first direction. The area between the first row and the second row on the first surface of the main body includes a contact area with a heat conduction member electrically connected with a semiconductor memory device and configured on a substrate of a host machine.

Description

semiconductor memory device

Embodiments of the present invention relate to a semiconductor memory device.

In recent years, with the technical improvement of non-volatile memory such as NAND (Not-AND: NAND) flash memory, the memory capacity of non-volatile memory has increased. Accompanying this, the development of semiconductor memory devices such as removable memory devices has been progressing.

However, in a semiconductor memory device such as a removable memory device, a structure for improving heat dissipation efficiency is sought.

The problem to be solved by the invention is to provide a semiconductor memory device that can improve heat dissipation efficiency.

According to an embodiment, a semiconductor memory device includes a main body, a memory, a controller, and a plurality of terminals. The above-mentioned body has: a first surface; a second surface located on the opposite side of the above-mentioned first surface; a first edge extending in the first direction; a first edge located on the opposite side of the above-mentioned first edge and extending in the above-mentioned first direction 2 end edges; a first side edge extending in a second direction intersecting the above-mentioned first direction; and a second side edge located on the opposite side of the above-mentioned first side edge and extending in the above-mentioned second direction. The above-mentioned memory is arranged inside the above-mentioned main body. The above-mentioned controller is arranged inside the above-mentioned main body to control the above-mentioned memory. The plurality of terminals include a plurality of signal terminals for transmitting signals, and are exposed on the first surface. The plurality of terminals described above form at least the first row and the second row. The first row includes a plurality of terminals, which are located closer to the first end edge than the second end edge, and are arranged at intervals in the first direction. The second row includes a plurality of terminals, which are equal to positions closer to the second end edge than the first end edge, and are arranged at intervals in the first direction. The area between the first row and the second row of the first surface includes a contact area with a heat conduction member electrically connected to the semiconductor memory device and disposed on the substrate of the host device.

Hereinafter, embodiments will be described with reference to the drawings.

A semiconductor memory device includes a non-volatile memory and a controller for controlling the non-volatile memory. A semiconductor memory device is a storage device that writes data into a non-volatile memory and reads data from the non-volatile memory. The semiconductor memory device can also be realized, for example, as a solid state drive (SSD: Solid State Drive). In this case, the SSD is used as a storage device for various information processing devices that function as host devices, such as personal computers, mobile devices, video recorders, and vehicle-mounted devices.

(first embodiment) The semiconductor memory device of the first embodiment has a card shape and can function as a detachable SSD that can be mounted on a connector in a host device. The connector for mounting the semiconductor memory device of this embodiment may be a push-type connector, a push-pull type connector, or a hinge-type connector. In this embodiment, it is assumed that the connector on which the semiconductor memory device is mounted is a hinge-type connector.

According to the detachable feature of the semiconductor memory device, the capacity can be upgraded and maintenance is easy. Hereinafter, the semiconductor memory device is referred to as a memory device (or a removable memory device).

FIG. 1 is a diagram showing an example of the external shape of a memory device 10 according to the first embodiment. FIG. 1(A) is a top view showing a surface of a memory device 10 . FIG. 1(B) is a side view showing the side of the memory device 10 . FIG. 1(C) shows a top view of one surface of the memory device 10, that is, shows a top view of another surface on the opposite side of one surface shown in FIG. 1(A).

As shown in FIGS. 1(A) to 1(C), in this specification, an X axis, a Y axis, and a Z axis are defined. The X axis, the Y axis and the Z axis are orthogonal to each other. The X axis is along the width of the memory device 10 . The Y axis is along the length (height) of the memory device 10 . The Z axis is along the thickness of the memory device 10 . In this specification, viewing the memory device 10 and the connector for mounting the memory device 10 from the negative direction of the Z axis is referred to as a top view.

The memory device 10 is a semiconductor memory device configured to operate with a power supply voltage supplied from the outside.

As shown in FIG. 1 , a memory device 10 includes a main body (frame) 11 having a thin-plate semiconductor package shape. The memory device 10 and the main body 11 are formed, for example, in a substantially rectangular plate shape extending in the Y-axis direction. The Y-axis direction is the long side direction of the memory device 10 and the main body 11 .

As shown in FIG. 1 , the main body 11 is plate-shaped and has a first surface 21 , a second surface 22 and an outer edge 23 . The first surface 21 and the second surface 22 are formed in a substantially square (rectangular) shape extending in the Y-axis direction. That is, the Y-axis direction is also the longitudinal direction of the first surface 21 and the second surface 22 .

The first surface 21 is a substantially flat surface facing the positive direction of the Z-axis. The second surface 22 is a substantially flat surface located on the opposite side to the first surface 21 and facing the negative direction of the Z-axis.

The outer edge 23 is disposed between the first surface 21 and the second surface 22 and connected to the edge of the first surface 21 and the edge of the second surface 22 . As shown in Figure 1, the outer edge 23 has a first edge 31, a second edge 32, a third edge 33, a fourth edge 34, a first corner 35, a second corner 36, a third corner 37 and a fourth corner. Corner 38.

The first edge 31 extends in the X-axis direction and faces the positive direction of the Y-axis. The X-axis direction is the short-side direction of the main body 11 , the first surface 21 and the second surface 22 , including the positive direction of the X-axis and the negative direction of the X-axis.

The second edge 32 extends in the Y-axis direction and faces the negative direction of the X-axis. The third edge 33 is located on the opposite side of the second edge 32, extends in the Y-axis direction, and faces the positive direction of the X-axis. The fourth edge 34 is located on the opposite side of the first edge 31, extends in the X-axis direction, and faces the negative direction of the Y-axis.

The length of each of the second edge 32 and the third edge 33 is longer than the length of each of the first edge 31 and the fourth edge 34 . The first edge 31 and the fourth edge 34 form the short side of the substantially rectangular memory device 10 , and the second edge 32 and the third edge 33 form the long side (side) of the substantially rectangular memory device 10 .

The first corner portion 35 is a corner portion between the first edge 31 and the second edge 32 , and connects the end of the first edge 31 in the negative direction of the X-axis and the end of the second edge 32 in the positive direction of the Y-axis.

The first corner portion 35 extends linearly between the end of the first edge 31 in the negative direction of the X-axis and the end of the second edge 32 in the positive direction of the Y-axis. The corner between the first edge 31 and the second edge 32 is set as a so-called C1.1 chamfer (also referred to as C chamfer), whereby the first corner portion 35 is set. In other words, the first corner portion 35 is a chamfered portion C formed between the first edge 31 and the second edge 32 .

The second corner portion 36 is a corner portion between the first edge 31 and the third edge 33 , and connects the end of the first edge 31 in the positive direction of the X-axis and the end of the third edge 33 in the positive direction of the Y-axis. The second corner portion 36 extends in an arc shape between the end of the first edge 31 in the positive direction of the X-axis and the end of the third edge 33 in the positive direction of the Y-axis. The corner between the first edge 31 and the third edge 33 is set to a so-called R0.2 round chamfer (also called R chamfer), thereby setting the second corner portion 36 . Thus, the shape of the first corner portion 35 and the shape of the second corner portion 36 are different from each other.

The third corner portion 37 connects the end of the second edge 32 in the negative direction of the Y-axis and the end of the fourth edge 34 in the negative direction of the X-axis. The fourth corner portion 38 connects the end of the third edge 33 in the negative direction of the Y-axis and the end of the fourth edge 34 in the positive direction of the X-axis. The third corner portion 37 and the fourth corner portion 38 each extend in an arc shape similarly to the second corner portion 36 .

The length of the main body 11, the first surface 21 and the second surface 22 in the Y-axis direction is set to be about 18±0.10 mm, and the length in the X-axis direction is set to be about 14±0.10 mm. That is, the distance between the first edge 31 and the fourth edge 34 in the Y-axis direction is set to about 18±0.1 mm, and the distance between the second edge 32 and the third edge 33 in the X-axis direction is set to about 14±0.10 mm. In addition, the lengths of the main body 11, the first surface 21, and the second surface 22 in the X-axis direction and the Y-axis direction are not limited to this example.

The thickness of the body 11 and the outer edge 23 in the Z-axis direction is set to be about 1.4±0.10 mm. That is, the distance between the first surface 21 and the second surface 22 in the Z-axis direction is set to be about 1.4±0.10 mm. In addition, the length of the outer edge 23 in the Z-axis direction is not limited to this example because the inclined portion 39 may be formed or chamfered. In order to securely fit the connector, the Z-axis direction must be specified with a plane tolerance, and the thickness of the entire surface must be within the tolerance.

As shown in FIG. 1(B), the main body 11 further has an inclined portion 39 . The inclined portion 39 is a corner portion between the first surface 21 and the first edge 31 , and extends linearly between the end of the first surface 21 in the positive direction of the Y-axis and the end of the first edge 31 in the positive direction of the Z-axis.

As shown in FIG. 1(A), on the first surface 21 of the memory device 10, a plurality of terminals may be arranged in three rows of row R1, row R2, and row R3. Signal terminals for 2 channels for a high-speed serial interface such as PCI Express (registered trademark) (PCIe) are arranged in row R1. The signal terminals corresponding to one channel include receiving differential signal pair 2 terminals and transmitting differential signal pair 2 terminals. Also, the two differential terminals are surrounded by ground terminals. Although not shown, a PCIe channel can also be added between the row R1 and the row R2.

The signal terminal for any optional signal different from each product can be configured on row R2. As an optional signal terminal, for example, a sideband signal (signal terminal for SMBus signal, WAKE# signal, and PRSNT# signal) according to the PCIe standard, or a ground terminal are listed as examples. The control signal and power supply terminals shared by the product are arranged on row R3. As the sideband signal according to the PCIe specification, for example, a CLKREF signal pair, a CLKREQ# signal, a PERST# signal, and the like are listed. A plurality of power supply terminals and ground terminals for supplying the power supply voltage from the host machine are arranged in the row R3.

In addition, there is a case where the row R1 is called the first row. Also, there is a case where the row R3 is called the second row. Furthermore, there is also a case where the row R2 is called the third row.

FIG. 2 shows a configuration example of the memory device 10 .

As shown in FIG. 2 , inside the body 11 of the memory device 10 , a printed circuit board 12 , a NAND flash memory 13 , and a controller 14 are arranged. The printed circuit board 12 , the NAND flash memory 13 , and the controller 14 can be housed in the box-shaped body 11 , or embedded in the body 11 . NAND type flash memory 13 and controller 14 are mounted on the surface of printed circuit board 12 .

In addition, the printed circuit board 12 may constitute a part of the main body 11 in such a manner that the back surface of the printed circuit board 12 is exposed. In this case, the back surface of the printed circuit board 12 can function as the first surface 21 .

The NAND flash memory 13 may also include a plurality of stacked NAND flash memory chips. Usually, the plurality of NAND flash memory chips are interleaved. The controller 14 is an LSI. The controller 14 controls the NAND flash memory 13 and the entire memory device 10 including the NAND flash memory 13 . For example, the controller 14 can control the reading/writing of the NAND flash memory 13 and control the communication with the outside. In addition, the memory device 10 has a PCIe interface as a system interface, and communication control is performed in the memory device 10 in accordance with the protocol of the PCIe specification.

The memory device 10 is realized as a package (memory package) having a card shape, and the NAND type flash memory 13 and the controller 14 are covered with a molding resin 40 shaped so as to form the main body (body 11) of the memory device 10 and seal.

FIG. 3 is a top view showing the shape of the memory device 10 and an arrangement example of a plurality of terminals P. Referring to FIG.

As shown in FIG. 3 , the memory device 10 has a plurality of terminals P. As shown in FIG. There are also cases where the terminal P is called a pin or a pad. In FIG. 3 , a case where the memory device 10 has 32 terminals P is shown as an example, but the number of terminals P is an example and is not limited to this example. That is, the number of terminals P may be less than 32 or more than 32. A plurality of terminals P are provided, for example, on the back surface of the printed circuit board 12 . A plurality of terminals P are formed on the printed circuit board 12 and exposed on the first surface 21 . In this embodiment, the terminal P is not provided on the second surface 22, and it can be used, for example, on the printed surface.

A plurality of terminals P are arranged in three rows to form a row R1, a row R2, and a row R3. The terminal group belonging to the row R1 is used as a signal terminal for transmitting a differential signal pair corresponding to 2 channels of the PCIe specification. The terminal group belonging to row R2 can be configured with signal terminals for any optional signal different from each product. Since the signal terminal is an unnecessary signal terminal for the memory device 10 (in other words, it is an optional signal terminal for the memory device 10), the number of terminals belonging to this row R2 can also be less than those belonging to other rows. The number of terminals. In the terminal group belonging to row R3, the control signal and power supply terminals common to each product are arranged. This terminal is mainly used as a signal terminal for differential clock signals, a signal terminal for shared PCIe sideband signals, a power supply terminal and other terminals.

As shown in FIG. 3 , the row R1 includes: 13 terminals P101 to P113 , which are arranged at intervals in the X-axis direction at a position closer to the first edge 31 than the fourth edge 34 . The terminal P101 to the terminal P113 are located in the vicinity of the first edge 31 , and are aligned in the X-axis direction along the first edge 31 .

Row R2 includes: six terminals P114 to P119 , which are arranged at intervals in the X-axis direction at a position closer to the fourth edge 34 than the first edge 31 . The terminals P114 to P116 are arranged in parallel in the X-axis direction along the fourth edge 34 at a position closer to the second edge 32 than the third edge 33 . Terminals P117 to P119 are arranged in parallel in the X-axis direction along the fourth edge 34 at a position closer to the third edge 33 than the second edge 32 . In other words, terminals P114 to P116 are arranged between the center line of the memory device 10 and the main body 11 in the X-axis direction (shown by a chain line) and the second edge 32, and terminals P117 to P119 are arranged in the memory device in the X-axis direction Between the center line of the device 10 and the body 11 and the third edge 33 . The distance between the terminal P116 and the terminal P117 belonging to the row R2 is greater than the distance between other terminals adjacent to the row R2 in the X-axis direction (specifically, the distance between the terminal P114 and the terminal P115, the distance between the terminal P115 and the terminal P116 interval, interval between terminal P117 and terminal P118, interval between terminal P118 and terminal P119) is wider.

The row R3 includes: 13 terminals P120 - P132 , which are arranged at intervals in the X-axis direction at a position closer to the fourth edge 34 than the first edge 31 . The terminals P120 to P132 belonging to the row R3 are arranged in parallel at a position closer to the fourth edge 34 than the terminals P114 to P119 belonging to the row R2.

When the length between the second edge 32 and the third edge 33 is specified, the distance between adjacent terminals P in the X-axis direction is determined by, for example, the number of terminals P. Furthermore, the maximum number of terminals P paralleled in the X-axis direction is determined according to the width of the adjacent terminals P in the X-axis direction and the minimum distance between adjacent terminals P. Taking into account the deviation of the contact part with the connector contact, determine the pad width and the distance between adjacent pads that can be reliably contacted. The distances between the plurality of terminals P in the X-axis direction may be equal or different. In this embodiment, since the number of terminals P belonging to row R1 and row R3 is the same, and the number of terminals P belonging to row R2 is less than that of other rows, the terminal spacing of row R2 can also be different from that of row R1 and row R3 .

As shown in FIG. 3 , the distance D1 between the row R1 and the row R3 in the Y-axis direction is longer than the distance D2 between the row R1 and the first edge 31 in the Y-axis direction, and the distance between the row R3 and the fourth edge 34 in the Y-axis direction. Distance D3.

In the example of FIG. 3, the length of the Y-axis direction of the terminal P of row R1, row R2, and row R3 is set to be the same. That is, the terminals P of each of the row R1, the row R2, and the row R3 are aligned so that the ends of the terminals P in the negative direction of the Y-axis and in the positive direction of the Y-axis are aligned at the same time.

FIG. 4 shows the external shape of the memory device 10, the external shape of the connector 100 in the host machine where the memory device 10 is installed, and the area where a thermally conductive member (TIM: Thermal Interface Material: Thermal Interface Material) 107 is attached. The top view of the configuration example. Fig. 4 (A) is a top view showing the shape of the memory device 10 and the area (hereinafter referred to as the contact area) A1 that is in contact with the area where the TIM107 is attached. The top view of the area with TIM107 (hereinafter referred to as the attachment area) A2. The memory device 10 is mounted from above the connector 100 shown in FIG. 4(B) with the terminal surface shown in FIG. 4(A) set downward. FIG. 5 is a side view showing a state where the memory device 10 is mounted on the connector 100 .

The connector 100 for mounting the memory device 10 shown in FIG. 4(A), as shown in FIG. The lead frames are arranged in three rows of row r1, row r2, and row r3. There are also cases where the lead frame is called a spring lead. Thirteen lead frames 101 corresponding to the thirteen terminals P101 to P113 arranged in the row R1 of the memory devices 10 are arranged in the row r1. Similarly, 6 lead frames 102 corresponding to the 6 terminals P114 to P119 of the row R2 of the memory device 10 are arranged on the row r2, and 13 lead frames 102 corresponding to the row R3 of the memory device 10 are arranged on the row r3. The 13 lead frames 103 correspond to the terminals P120 - P132 .

In FIG. 4(B), the lengths in the Y-axis direction of the lead frames 101 to 103 forming the row r1 , the row r2 , and the row r3 are the same. However, the lengths in the Y-axis direction of the lead frames 101 to 103 are not limited to this example. For example, the lengths of the lead frames 101 to 103 in the Y-axis direction may also be different from each other.

As shown in FIG. 4(B) , lead frames 101 to 103 each have lead frame terminals 104 and mounting portions 105 . The lead frame terminal 104 is a portion in contact (point contact) with each of the plurality of terminals P forming the row R1 , row R2 , and row R3 of the memory device 10 . The mounting portion 105 is a portion that is in contact with the printed circuit board in the host device when the lead frames 101 to 103 are mounted on the printed circuit board. In other words, the mounting part 105 is a part fixed on the printed circuit board of the host device when the lead frames 101 - 103 are mounted on the printed circuit board.

If the memory device 10 is mounted on the connector 100 , the lead frame terminals 104 of the lead frames 101 to 103 of the connector 100 are in contact with each of the plurality of terminals P forming the rows R1 , R2 and R3 .

If the lead frame terminals 104 of the lead frames 101 to 103 are in contact with the terminal P, the host control unit disposed on the system substrate of the host machine is electrically connected to the controller 14 of the memory device 10 .

In addition, in FIG. 4(B), the lead frame terminal 104 of the lead frame 101 forming the row r1 faces the negative direction of the Y axis. The lead frame terminals 104 of the lead frames 102 forming the row r2 face the negative direction of the Y axis. The lead frame terminal 104 of the lead frame 103 forming the row r3 faces the positive direction of the Y axis. In addition, the lead frame terminals 104 forming the row r1, the row r2, and the row r3 may face the opposite side.

As shown in FIG. 4(B), the connector 100 has a connector frame 106 that supports the memory device 10 when the memory device 10 is installed therein. In other words, the connector 100 has a connector frame 106 for accommodating the memory device 10 when the memory device 10 is installed. As shown in FIG. 4(B), the connector frame 106 has a first edge 111 , a second edge 112 , a third edge 113 , a fourth edge 114 , a connecting portion 115 , and a notch 116 .

The first edge 111 extends in the X-axis direction and faces the negative direction of the Y-axis. The first edge 111 is in contact with the first edge 31 of the memory device 10 when the memory device 10 is mounted. The first edge 111 overlaps the mounting portion 105 of the lead frame 101 forming the row r1 in a plan view, and is connected to (bonded to) the mounting portion 105 .

The second edge 112 extends in the Y-axis direction and faces the negative direction of the X-axis. The second edge 112 is in contact with the third edge 33 of the memory device 10 when the memory device 10 is mounted. The third edge 113 extends in the Y-axis direction and faces the positive direction of the X-axis. The third edge 113 is in contact with the second edge 32 of the memory device 10 when the memory device 10 is mounted.

The fourth edge 114 extends in the X-axis direction and faces the positive direction of the Y-axis. The fourth edge 114 is in contact with the fourth edge 34 of the memory device 10 when the memory device 10 is mounted. The fourth edge 114 overlaps the mounting portion 105 of the lead frame 103 forming the row r3 in a plan view, and is connected to (bonded to) the mounting portion 105 .

The connecting portion 115 extends in the X-axis direction, is located between the first edge 111 and the fourth edge 114 , and connects the second edge 112 and the third edge 113 . The connecting portion 115 overlaps the mounting portion 105 of the lead frame 102 forming the row r2 in plan view, and is connected to (adhered to) the mounting portion 105 .

The notches 116 are respectively formed on the second edge 112 and the third edge 113 . As shown in FIG. 5 , when the memory device 10 is mounted on the connector 100 , the claws of the cover 120 for fixing the memory device 10 are fastened to the notches 116 .

TIM107 is attached to the attaching area A2 indicated by oblique lines in FIG. 4(B). More specifically, as shown in FIG. 4(B), in the connector 100, in the region between the row r1 and the row r2, and in the lead frame 102 forming the row r2, corresponding to the terminal P116 of the memory device 10 The TIM 107 is attached to the lead frame 102 and the area between the lead frame 102 corresponding to the terminal P117 of the memory device 10 . TIM107 is attached to the printed circuit board in the host machine.

In Fig. 4 (A), the contact area A1 surrounded by dotted lines and the attaching area A2 shown by oblique lines in Fig. 4 (B) with TIM107 attached, when the memory device 10 is mounted on the connector 100, in a top view Lower overlap. In other words, when the memory device 10 is mounted on the connector 100 , the memory device 10 faces and contacts the TIM 107 attached to the attachment area A2 of the connector 100 in the contact area A1 .

By arranging the terminal P of the memory device 10 as shown in FIG. Attached area A2. In general, in removable memory devices, conventionally, by using the arranged terminals as terminals for heat dissipation, a heat dissipation path to a printed circuit board in a host machine is ensured and heat dissipation is performed. However, since the terminals disposed on the memory device and the lead frame terminals of the lead frame are only in point contact, the heat dissipation area is small and the heat dissipation efficiency is poor. Also, since the lead frame terminals of the lead frame are not welded to the printed circuit board in the host machine, it will be affected by the thermal resistance of the length from the lead frame terminals of the lead frame to the mounting portion of the lead frame, resulting in poor heat dissipation efficiency.

In contrast, in the memory device 10 of this embodiment, since the number of terminals P forming the row R2 is reduced to be less than the number of terminals P forming the row R1 or R3, the contact region A1 shown in FIG. 4(A) is realized. Therefore, the attachment area A2 for attaching the TIM107 can be set on the connector 100. Thereby, as shown in FIG. 5, when the memory device 10 is mounted on the connector 100, the memory device 10 is in surface contact with the TIM 107 in the contact area A1, so that the heat dissipation area can be expanded compared with the point contact above. , which can improve the cooling efficiency.

Here, referring to FIG. 6 , a case where at least one of the terminals P forming the row R3 of the memory device 10 of this embodiment is used as an SCS (Sideband Signal Configuration Select) terminal will be described.

FIG. 6 is a diagram illustrating the use of the terminal P of the memory device 10 as the SCS terminal. In FIG. 6(A), it is assumed that the terminal P132 belonging to the row R3 of the memory device 10 is used as the SCS terminal. In addition, in FIG. 6(A), it is assumed that the terminal P132 belonging to the row R3 of the memory device 10 is used as the SCS terminal, but it is not limited to this example, and the terminal P132 belonging to the row R3 of the memory device 10 can also be used. Different terminals P (terminal P120 to terminal P131) are used as SCS terminals. In addition, in FIG. 6(A), the case where there is one SCS terminal is assumed, but it is not limited to this example, and a plurality of SCS terminals may be provided.

Also, in FIG. 6(A), it is envisaged to use four terminals P115 to P118 among the six terminals P114 to P119 belonging to the row R2 of the memory device 10 as signal terminals for sideband signals of the PCIe standard, and use The two terminals P114 and P119 are used as signal terminals (ground terminals) for GND (Ground). However, the distribution of the six terminals P114 to P119 belonging to the row R2 of the memory device 10 is not limited to this example, and any terminal P among the six terminals P114 to P119 belonging to the row R2 of the memory device 10 can also be used. As a signal terminal for sideband signals, an arbitrary terminal P is used as a signal terminal for GND.

The SCS terminal is a signal terminal for transmitting a signal (hereinafter referred to as a selection signal) for changing (selecting) a sideband signal from a host device. Input the selection signal of High (high) level or the selection signal of Low (low) level to the SCS terminal from the host machine.

As shown in FIG. 6(B), when the selection signal of High (high) level is input to the SCS terminal, the terminal P115 belonging to the row R2 of the memory device 10 is used as the terminal for transmitting the first sideband signal SB1. Signal terminals, use terminal P116 as the signal terminal for transmitting the second sideband signal SB2, use terminal P117 as the signal terminal for transmitting the third sideband signal SB3, and use terminal P118 as the signal terminal for transmitting the fourth sideband signal SB4 the signal terminal. In other words, when a selection signal of a High (high) level is input to the SCS terminal, the terminals P115 to P118 belonging to the row R2 of the memory device 10 are used as the sideband signals SB1 to SB1 for transmitting the first configuration. Signal terminal with signal SB4.

On the other hand, as shown in FIG. 6(B), when the selection signal of Low (low) level is input to the SCS terminal, the terminal P115 belonging to the row R2 of the memory device 10 is used as the terminal P115 for transmitting the fifth side. For the signal terminal with signal SB5, use terminal P116 as the signal terminal for transmitting the sixth sideband signal SB6, use terminal P117 as the signal terminal for transmitting the seventh sideband signal SB7, and use terminal P118 as the signal terminal for transmitting the eighth sideband signal Signal terminal for sideband signal SB8. In other words, when a selection signal of a Low (low) level is input to the SCS terminal, the terminals P115 to P118 belonging to the row R2 of the memory device 10 are used as the sideband signals SB5 to SB5 for transmitting the second configuration. Signal terminal with signal SB8.

In addition, in FIG. 6 , the case of transmitting different sideband signals in the first configuration and the second configuration is illustrated, but the present invention is not limited to this example, and sideband signals that are partly common to the first configuration and the second configuration may be transmitted. For example, the terminal P115 and the terminal P116 can also be used to transmit the first selection signal regardless of whether the selection signal of the High (high) level is input to the SCS terminal or the selection signal of the Low (low) level is input. The sideband signal SB1 and the second sideband signal SB2, and the terminal P117 and terminal P118 are used to transmit the third sideband signal SB3 and the fourth sideband when the selection signal of the High (high) level is input to the SCS terminal The signal SB4 is used to transmit the fifth sideband signal SB5 and the sixth sideband signal SB6 when the selection signal of Low level is input to the SCS terminal.

FIG. 7 shows the host control unit 201 and the switch 202 arranged on the substrate of the host machine.

The switch 202 on the substrate of the host machine is connected to the terminal 103 in the connector 100 through the pull-up resistor 202A, and further connected to the SCS terminal P132 of the memory device 10 . The level of the SCS terminal can be selected by turning on or off the fixed switch 202 .

As a method not shown, it is also possible to select the SCS by the host control unit 201 by directly connecting the GPIO (General-purpose input/output) output of the host control unit 201 to the terminal 103 in the connector 100 terminal level. Furthermore, when the level of the SCS terminal is not selected, the level can also be fixed by a pull-up resistor or a pull-down resistor.

As shown in FIG. 7 , one end of the switch 202 is grounded, and the other end is connected to the pull-up resistor 202A and the lead frame 103 in contact with the SCS terminal. When the switch 202 is turned off, a selection signal of High level is input to the SCS terminal of the memory device 10 through the lead frame 103 . If the selection signal of High (high) level is input to the SCS terminal, as shown in Figure 6(B), the terminals P115-P118 belonging to the row R2 are used to transmit the first sideband signals SB1-SB of the first configuration. The signal terminal of the 4 sideband signal SB4 functions. On the other hand, when the switch 202 is turned on, a selection signal of Low level is input to the SCS terminal of the memory device 10 through the lead frame 103 . If the selection signal of Low (low) level is input to the SCS terminal, as shown in Figure 6(B), terminals P115 to P118 belonging to row R2 are used to transmit the fifth sideband signal SB5 to the eighth sideband signal The signal terminal of SB8 functions.

Next, the power supply voltage supplied to the memory device 10 of this embodiment will be described with reference to FIG. 8 .

FIG. 8 is a top view showing the external shapes of the first-generation memory device 10a and the second-generation memory device 10b. The first-generation memory device 10a is configured to operate with n types (where n≧2) of power supply voltages supplied from the outside. On the other hand, the second-generation memory device 10b is configured to operate with m types of (where n>m≧1, n and m are natural numbers) power supply voltages supplied from the outside. Therefore, there is a possibility that the first-generation memory device 10a and the second-generation memory device 10b are mixed in the market. Hereinafter, assuming that the first-generation memory device 10a is a memory device configured to operate with two power supply voltages, the memory device 10a is referred to as a two-power supply memory device. On the other hand, the memory device 10b is referred to as a 1-power supply memory device.

When a period of time has elapsed since the start of manufacturing and shipping of the first-generation memory device such as the 2-power supply memory device 10a, and the start of the manufacture and shipment of the second-generation memory device such as the 1-power supply memory device 10b, As described above, there is an environment where first-generation memory devices and second-generation memory devices having different specifications are mixed.

Therefore, for example, in a product manufacturing line that manufactures a host device such as an information processing device, there are manufacturing and operation tests of a first-type host configured to supply two power supply voltages, and a configuration configured to supply a single power supply voltage. The manufacture and operation test of the Type 2 host.

The first type host is an information processing device configured to supply two types of power supply voltages to a 2-power supply memory device 10a mounted on a connector in the host machine. On the other hand, the type 2 host is an information processing device configured to supply one power supply voltage to one power supply memory device 10b mounted on a connector in the host device.

When the 2-power supply memory device 10a and the 1-power supply memory device 10b have the same memory device shape, in the product manufacturing line, the state that the 1-power supply memory device 10b may be wrongly mounted on the connector of the first type host , the example of carrying out the action test of the first type host, or the example of carrying out the action test of the second type host with the state that the 2-power supply memory device 10a is wrongly installed in the connector of the second type host.

In the operation test of the host machine, the host machine is powered on, whereby the host machine supplies several power supply voltages corresponding to the type of the host machine to the memory device. If the power supply voltage supplied from the host machine does not match the power supply configuration of the memory device, and the operation test of the host machine is performed, there will be a large current flowing through the memory device that is damaged by applying a voltage other than the operation guarantee and causing fire. The so-called risk of bad.

Therefore, in order to suppress the occurrence of such defects, it is conceivable to make the memory device shapes of the 2-power supply memory device 10a and the 1-power supply memory device 10b different, so that the 2-power supply memory device 10a and the 1-power supply memory device can be distinguished. Device 10b. For example, consider that, as shown in FIG. 8(A), in the 2-power supply memory device 10a, the first corner 35 is formed like a chamfered portion C. On the other hand, in the 1-power supply memory device 10b, as shown in FIG. 8 As shown in (B), the second corner portion 36 is formed like the chamfered portion C. As shown in FIG. Thereby, since the 1-power supply memory device 10b cannot be mounted on the connector of the first-type mainframe, and the 2-power supply memory device 10a cannot be mounted on the connector of the second-type mainframe, the occurrence of the above-mentioned defects can be suppressed.

In FIG. 8 , by making the memory device shapes of the 2-power supply memory device 10a and the 1-power supply memory device 10b different from each other, it is possible to prevent the 1-power supply memory device 10b from being wrongly mounted on the first type host. The situation that the device and the memory device 10a of the 2 power supply are incorrectly installed in the connector of the second type host will be described. On the other hand, it is conceivable to use at least one of the terminals P forming the row R3 of the memory device 10 as a PCD (Power Configuration Detect: Power Configuration Detect) terminal, thereby suppressing the occurrence of the above-mentioned problems. Hereinafter, a case where at least one of the terminals P forming the row R3 of the memory device 10 of the present embodiment is used as a PCD terminal will be described with reference to FIG. 9 .

FIG. 9 is a diagram illustrating the use of the terminal P of the memory device 10 as a PCD terminal. In FIG. 9(A), it is assumed that the terminal P131 belonging to the row R3 of the memory device 10 is used as a PCD terminal. In addition, in FIG. 9(A), it is assumed that the terminal P132 belonging to the row R3 of the memory device 10 is used as the SCS terminal, as in the case of FIG. 6(A). In addition, in FIG. 9(A), it is envisaged to use the terminal P131 belonging to the row R3 of the memory device 10 as the PCD terminal, but it is not limited to this example, and the terminal P131 belonging to the row R3 of the memory device 10 can also be used. Terminal P (terminal P120 to terminal P130 ) different from terminal P132 is used as a PCD terminal. Moreover, in FIG. 9(A), the case where there is one PCD terminal is assumed, but it is not limited to this example, and a plurality of PCD terminals may be provided.

The PCD terminal is a signal terminal for transmitting a signal for detecting the power supply configuration of the memory device 10 (hereinafter referred to as a detection signal). Output a High (high) level detection signal or a Low (low) level detection signal to the host machine from the PCD terminal.

As shown in FIG. 9(B), when a detection signal of High level is output from the PCD terminal, the host device recognizes that the power supply of the memory device 10 is configured as two power supplies. In other words, when the detection signal of High level is output from the PCD terminal, the host device recognizes the memory device mounted on the connector 100 as the 2-power supply memory device 10a. On the other hand, when the detection signal of the Low level is output from the PCD terminal, the host device recognizes that the power supply configuration of the memory device 10 is 1 power supply. In other words, when the detection signal of Low level is output from the PCD terminal, the host machine recognizes that the memory device mounted on the connector 100 is the 1-power memory device 10b.

FIG. 10 shows the internal circuit connected to the PCD terminal of the 1-power memory device 10b and the internal circuit connected to the 2-power memory device 10a.

As shown in FIG. 10(A), the PCD terminal of the power supply memory device 10b is connected to GND in the device 10b. Therefore, under the control of the host control unit 201, when the first power supply voltage is supplied to the first power supply memory device 10b, GND is grounded, and a Low (low) level is output from the PCD terminal of the first power supply memory device 10b. the detection signal.

On the other hand, as shown in FIG. 10(B), the PCD terminal of the 2-power supply memory device 10a is turned on. Therefore, input High (high) to the host machine through the pull-up resistor on the substrate of the host machine.

According to the structure shown in FIG. 10, the host device (host control unit 201) can identify the power supply configuration of the memory device 10 according to the level of the detection signal that can be output at the point when the first power supply voltage is supplied, and can determine the second power supply. Whether the voltage is supplied or not, so the occurrence of the above-mentioned defects can be suppressed.

Here, referring to FIG. 11, a case where one terminal P of the memory device 10 of this embodiment is used as an SCS terminal or as a PCD terminal will be described. FIG. 11 is a diagram illustrating the use of one terminal P of the memory device 10 as an SCS terminal or as a PCD terminal.

As described above, the SCS terminal is a signal terminal used to input a selection signal, and the PCD terminal is a signal terminal used to output a detection signal. Therefore, as long as the timing of the input selection signal and the timing of the output detection signal do not overlap, one terminal P can have the functions of both the SCS terminal and the PCD terminal.

In order to make one terminal P have the functions of both the SCS terminal and the PCD terminal, as shown in FIG. A tri-state buffer 203 is provided between the lead frames 103 . The tri-state buffer 203 can also be included in the host control unit 201 .

As shown in FIG. 11(B), when making one terminal P function as an SCS terminal, a switching signal of a Low level is input to the tri-state buffer 203 from the host controller 201 . In this case, since the tri-state buffer 203 directly outputs the selection signal output from the host control unit 201 to the memory device 10, one terminal P can function as an SCS terminal.

In addition, under the control of the host control unit 201, if the second power supply voltage is supplied to the two-power supply memory device 10a, the switch 15 is turned off, and the connection between the wiring for supplying the first power supply voltage and the pull-up resistor can also be disconnected. open. Alternatively, if an unshown disconnection circuit is provided to supply the second power supply voltage to the two-power supply memory device 10a and execute the initialization sequence, the wiring for supplying the first power supply voltage can be disconnected by the disconnection circuit. The connection to the pull-up resistor is disconnected. Thereby, unnecessary power consumption caused by the pull-up resistor after outputting the detection signal from the PCD terminal can be suppressed.

On the other hand, when making one terminal P function as a PCD terminal, as shown in FIG. If the switching signal of High (high) level is input from the host control unit 201, the tri-state buffer 203 will be in a high-impedance state and will be in an electrically disconnected state, so no output will be output from the tri-state buffer 203 to the memory device 10. signal, one terminal P can function as a PCD terminal.

FIG. 12 is a timing chart showing an example of the operation when one terminal P of the memory device 10 of this embodiment is used as the SCS terminal or as the PCD terminal.

As shown in FIG. 12 , at the first timing T1 , the host control unit 201 starts to output the High (high) level switching signal to the tri-state buffer 203 . Thereby, the specific terminal P of the memory device 10 functions as a PCD terminal. Next, at the second time sequence T2 , under the control of the host control unit 201 , the first power supply voltage starts to be supplied to the memory device 10 . When the supply of the first power supply voltage to the memory device 10 starts, at the third timing T3, the detection signal output from the PCD terminal of the memory device 10 is input to the host control unit 201 . Thereby, the host control unit 201 can identify the power supply configuration of the memory device 10 and determine whether the second power supply voltage is supplied or not.

At the fourth timing T4 after identifying the power supply configuration of the memory device 10, the host control unit 201 switches the level of the switching signal output to the tri-state buffer 203 from High (high) level to Low (low) level . Thereby, the above-mentioned specific terminal P of the memory device 10 functions as an SCS terminal. Hereinafter, the selection signal of High (high) level or Low (low) level is output from the host control unit 201 to the memory device 10, and the sideband signal terminal disposed on the memory device 10 serves as a terminal for transmitting the signal corresponding to the High level. The signal terminal of the sideband signal of the first configuration of the (high) level selection signal, or the signal terminal of the sideband signal of the second configuration corresponding to the Low (low) level selection signal.

Hereinafter, a modification example of the arrangement of the plurality of terminals P provided in the memory device 10 will be described. In addition, below, basically only the parts different from the terminal arrangement shown in FIG. 4 are mentioned, and the description of the same parts as in FIG. 4 is omitted. In addition, the distance between the row R1 and the row R3 in the Y-axis direction of any terminal arrangement is longer than the distance between the row R1 in the Y-axis direction and the first edge 31, and the distance between the row R3 in the Y-axis direction and the fourth edge 34. distance.

(1st modification example) 13 is a plan view showing the shape of the memory device 10A of the first variation, the shape of the connector 100A in the host machine on which the memory device 10A is mounted, and the arrangement of the area where the TIM 107 is attached. Fig. 13(A) is a top view showing the shape of the memory device 10A and the contact area A11 in contact with the TIM107, and Fig. 13(B) is a top view showing the shape of the connector 100A and the attachment area A21 attached with the TIM107 .

The terminals shown in FIG. 13(A) are arranged at the point where the positions of the six terminals P114-P119 forming the row R2 are closer to the first edge 31 than the fourth edge 34, which is different from the terminal arrangement shown in FIG. 4(A) .

Therefore, in the connector 100A for mounting the memory device 10A shown in FIG. 13(A), as shown in FIG. 13(B), the lead frame terminal 104 of the lead frame 101 forming the row r1 faces the negative direction of the Y axis, The lead frame terminals 104 of the lead frames 102 forming the row r2 face the positive direction of the Y axis, and the lead frame terminals 104 of the lead frames 103 forming the row r3 face the positive direction of the Y axis.

As shown in FIG. 13(B), in the connector 100A, in the region between the row r1 and the row r2, and in the lead frame 102 forming the row r2, the lead frame 102 corresponding to the terminal P116 of the memory device 10A is connected to the lead frame 102 corresponding to the terminal P116 of the memory device 10A. The TIM 107 is attached to the area between the lead frames 102 of the terminal P117 of the memory device 10A. The TIM 107 is attached to the attached area A21 indicated by oblique lines in FIG. 13(B).

The contact area A11 surrounded by dotted lines in FIG. 13(A) and the attaching area A21 shown by oblique lines in FIG. 13(B) with TIM107 are overlapped when the memory device 10A is mounted on the connector 100A when viewed from above. . In other words, when the memory device 10A is mounted on the connector 100A, the contact area A11 of the memory device 10A faces and contacts the TIM 107 attached to the attachment area A21 of the connector 100A.

As explained above, by arranging the terminal P of the memory device 10A as shown in FIG. Attached area A21 of TIM107. In other words, since the number of terminals P forming the row R2 of the memory device 10A is less than the number of terminals P forming the row R1 or R3, the terminal arrangement for setting the contact area A11 shown in FIG. The device 100A is provided with an attaching area A21 for attaching the TIM 107. Thereby, when the memory device 10A is mounted on the connector 100A, the memory device 10A is in surface contact with the TIM 107 in the contact area A11, so that heat dissipation efficiency can be improved as in the case of the terminal arrangement shown in FIG. 4 .

(the second modification example) 14 is a top view showing the shape of the memory device 10B of the second modification, the shape of the connector 100B in the host machine on which the memory device 10B is mounted, and the arrangement of the region where the TIM 107 is attached. Figure 14(A) is a top view showing the shape of the memory device 10B and the contact area A12 contacting with the TIM107, and Figure 14(B) is a top view showing the shape of the connector 100B and the attachment area A22 attached with the TIM107 .

The terminal arrangement shown in FIG. 14(A) differs from the terminal arrangement shown in FIG. 4(A) at the point where the number of terminals P forming the row R2 is reduced from six to three. Specifically, the terminal arrangement shown in FIG. 14(A) is different from the terminal arrangement shown in FIG. 4(A) at a point where the terminal P114 to the terminal P116 shown in FIG.

Of the three terminals P117 to P119 forming row R2 shown in Fig. 14(A), two terminals P117 and P118 are used as signal terminals for sideband signals of the PCIe standard, and one terminal P119 is used as a signal terminal for GND. . However, the allocation of the three terminals P117 to P119 belonging to the row R2 of the memory device 10B is not limited to this example, and any terminal P among the three terminals P117 to P119 belonging to the row R2 of the memory device 10B can be used. As a signal terminal for sideband signals, an arbitrary terminal P is used as a signal terminal for GND.

As shown in FIG. 14(B), in the connector 100B, between the region between the row r1 and the row r2, and between the lead frame 102 corresponding to the terminal P117 of the memory device 10B and the third edge 113 of the connector frame 106 area, with TIM107 attached. In FIG. 14(B), the sticking area A22 indicated by oblique lines has the TIM 107 stuck thereto.

The contact area A12 surrounded by dotted lines in FIG. 14(A) and the attaching area A22 shown by oblique lines in FIG. 14(B) with TIM107 attached thereto overlap when the memory device 10B is mounted on the connector 100B when viewed from above. . In other words, when the memory device 10B is mounted on the connector 100B, the memory device 10B is in the contact area A12, facing and in contact with the TIM 107 attached to the attachment area A22 of the connector 100B.

As explained above, by arranging the terminal P of the memory device 10B as shown in FIG. Attachment area A22 of TIM107. In other words, since the number of terminals P forming the row R2 of the memory device 10B is less than the number of terminals P forming the row R1 or R3, and the terminal configuration of the contact area A12 shown in FIG. 14(A) is realized, it can be used in The connector 100B is provided with an attaching area A22 for attaching the TIM 107 . In addition, the contact area A12 provided according to the terminal configuration shown in FIG. 14 is larger than the contact area A1 and the contact area A11 provided according to the terminal configuration shown in FIG. 4 and FIG. The number of terminals is reduced from 6 to 3. Therefore, compared with the terminal configuration shown in FIG. 4 and FIG. 13 , the terminal configuration shown in FIG. 14 can expand the surface contact area with the TIM 107 and further improve the heat dissipation efficiency.

In addition, Fig. 14 shows that the terminal P114 to the terminal P116 shown in Fig. 4 are not arranged as the terminals P that form the row R2, but the terminal P117 to the terminal P119 are arranged as the terminals P that form the row R2. However, the arrangement of the terminals Not limited to this. For example, instead of disposing the terminals P117 to P119 shown in FIG. 4 as the terminals P forming the row R2, terminals P114 to 116 may be arranged as the terminals P forming the row R2. Also in this terminal arrangement, the same effect as that of the terminal arrangement shown in FIG. 14 can be obtained.

In addition, in FIG. 14 , it is shown that the terminal P117 to the terminal P119 forming the row R2 are arranged at a position closer to the fourth edge 34 than the first edge 31 of the memory device 10B, but it is not limited to this, and it may be, for example, The terminals P117 to P119 forming the row R2 are arranged in a terminal arrangement that is located closer to the first edge 31 than the fourth edge 34 of the memory device 10B. Also in this terminal arrangement, the same effect as that of the terminal arrangement shown in FIG. 14 can be obtained.

Moreover, the memory device 10 of FIG. 4(A) can also be mounted on the connector 100B of FIG. 14(B). In this case, terminals P114 to P116 of row R2 are in contact with TIM107, but an insulating TIM is used to avoid a short circuit, or the unconnected terminals P114 to P116 are set to be connected in the default state, which will not become Output mode, and the input is also an I/O cell of the through-current prevention type.

(3rd modification example) 15 is a top view showing the external shape of the memory device 10C of the third modification, the external shape of the connector 100C in the host machine on which the memory device 10C is mounted, and the arrangement example of the region where the TIM 107 is attached. Fig. 15(A) is a top view showing the shape of the memory device 10C and the contact area A13 in contact with the TIM107, and Fig. 15(B) is a top view showing the shape of the connector 100C and the attachment area A23 attached with the TIM107 .

The terminal arrangement shown in FIG. 15(A) is different from the terminal arrangement shown in FIG. 4(A) in that the terminal P not forming the row R2 is provided. That is, the terminal arrangement shown in FIG. 15(A) is a terminal arrangement in which signal terminals for sideband signals of the PCIe standard are not provided.

In this case, as shown in FIG. 15(B), in the connector 100C, the TIM 107 is attached to the region between the row r1 and the row r3. In other words, the TIM 107 is attached to the attaching area A23 indicated by oblique lines in FIG. 14(B).

In Fig. 15(A), the contact area A13 surrounded by dotted lines and the attaching area A23 shown by oblique lines in Fig. 15(B) with the TIM107 attached, when the memory device 10C is mounted on the connector 100C, it is viewed from above time overlap. In other words, when the memory device 10C is mounted on the connector 100C, the memory device 10C is in the contact area A13, facing and in contact with the TIM 107 attached to the attachment area A23 of the connector 100C.

As explained above, by arranging the terminal P of the memory device 10C as shown in FIG. Attached area A23 of TIM107. In other words, the memory device 10C realizes the terminal configuration of setting the contact area A13 shown in FIG. 15(A) by not setting the terminal P forming the row R2, so the attachment area for the TIM107 can be set on the connector 100C A23. In addition, the contact area A13 provided by the terminal arrangement shown in FIG. 15 is larger than the contact area A1 and A11 shown in FIG. 4 and FIG. 13 , and the contact area A12 shown in FIG. 14 . Corresponds to the part where the terminal P of the row R2 is not formed. Therefore, compared with the terminal configurations shown in FIG. 4 , FIG. 13 and FIG. 14 , the terminal configuration shown in FIG. 15 can expand the surface contact area with the TIM 107 , and further improve heat dissipation efficiency.

Furthermore, the memory device 10 and the memory device 10A shown in FIG. 4(A) or FIG. 13(A) can also be mounted on the connector 100C shown in FIG. 15(B). In this case, although the terminals P114~P116 and P117~P119 of the row R2 will be in contact with the TIM107, an insulating TIM is used to avoid short circuits, or the unconnected terminals P114~P116 and P117~P119 are in contact with the TIM107. In the default state, it can be turned on, but not in the output mode, and the input is also an I/O cell of the through-current prevention type.

(4th modification example) 16 is a top view showing the shape of the memory device 10D in the fourth variation, the shape of the connector 100D in the host machine on which the memory device 10D is mounted, and the arrangement of the region where the TIM 107 is attached. Figure 16(A) is a top view showing the shape of the memory device 10D and the contact area A14 in contact with the TIM107, and Figure 16(B) is a top view showing the shape of the connector 100D and the attachment area A24 where the TIM107 is attached The top view.

The terminal configuration shown in FIG. 16(A) is different from the terminal configuration shown in FIG. 4(A) in the following points, that is, due to the Y-axis direction of the lead frame 103 of the connector 100 shown in FIG. 16(B) The length is longer than the length in the Y-axis direction of the lead frame 103 shown in FIG. 4(B), so the position of R3 in the Y-axis direction becomes closer to the first edge 31. Specifically, in the case of the terminal arrangement shown in FIG. 16(A), the position of the row R3 in the Y-axis direction is closer to the first edge 31 by about one row compared with the terminal arrangement shown in FIG. 4(A). Quantity (equivalent to the length of terminal P in the Y-axis direction).

In this case, as shown in FIG. 16(B), in the connector 100D, the TIM 107 is attached to the region between the row r1 and the row r3. TIM 107 is attached to the attaching area A24 indicated by oblique lines in FIG. 16(B).

The contact area A14 surrounded by dotted lines in FIG. 16(A) and the attaching area A24 shown by oblique lines in FIG. 16(B) are attached with TIM107, when the memory device 10D is mounted on the connector 100D, under the top view overlapping. In other words, when the memory device 10D is mounted on the connector 100D, the memory device 10D is in the contact area A14, facing and in contact with the TIM 107 attached to the attachment area A24 of the connector 100D.

As explained above, even if the length of the lead frame 103 in the Y-axis direction is longer than that shown in FIG. 4(B), if the terminals P of the memory device 10D are arranged as shown in FIG. The connector 100D on which the memory device 10D is mounted is provided with an attaching area A24 for attaching the TIM 107 as shown in FIG. 16(B). The terminal arrangement shown in FIG. 16 can also improve the heat dissipation efficiency compared with the above point contact.

As shown in an example of the fourth modification example, the memory device 10 of this embodiment tries to carry out the terminal arrangement of a plurality of terminals P regardless of the length of the lead frame 103 of the connector 100 in the Y-axis direction, so that it can be arranged with the TIM 107 The contact area A1 can improve the heat dissipation efficiency of the memory device 10 .

In addition, in this embodiment, the terminal P is not arranged in the contact area A1 provided in the memory device 10 , but not limited to this example, the terminal P may be arranged in the contact area A1 provided in the memory device 10 . However, when the memory device 10 is mounted on the connector 100, the terminal P disposed in the contact area A1 is in contact with the TIM 107 attached to the attachment area A2, so the terminal P cannot be used as a signal terminal for sideband signals or Signal terminal for GND. However, in this case, the memory device 10 can also be in surface contact with the TIM 107, so that the heat dissipation efficiency of the memory device 10 can be improved.

Also, the sideband signal in this embodiment can also be referred to as a selectable signal.

According to the first embodiment described above, the memory device 10 ( 10C) includes a plurality of signal terminals for transmitting signals, and includes a plurality of terminals P exposed on the first surface 21 of the main body 11 . The plurality of terminals P at least form a row R1 and a row R3. The row R1 includes: a plurality of signal terminals P, which are arranged at intervals in the X-axis direction at positions closer to the first edge 31 than the fourth edge 34 of the main body 11 . The row R3 includes: a plurality of signal terminals P, which are arranged at intervals in the X-axis direction at a position closer to the fourth edge 34 than the first edge 31 of the main body 11 . The area between the row R1 and the row R3 of the first surface 21 of the body 11 includes a contact area A1 ( A13 ) that is in contact with the TIM 107 disposed on the printed circuit board of the electrically connected host machine. Therefore, when the memory device 10 ( 10C) is mounted on the connector 100 ( 100C), it can be in surface contact with the TIM 107 in the contact area A1 ( A13 ), so the heat dissipation efficiency of the memory device 10 ( 10C) can be improved.

(Second Embodiment) Next, a second embodiment will be described. In addition, the detailed description of the matters already described in the above-mentioned first embodiment will be omitted, and the following will mainly describe the matters different from the above-mentioned first embodiment.

FIG. 17 is a diagram showing an example of the pin assignment of the terminal group P101 to P113 belonging to the row R1 of the memory device 10 . The terminal group P101 to P113 belonging to the row R1 are used as signal terminals for transmitting a differential signal pair corresponding to 2 channels of the PCIe specification, and as ground terminals for noise protection.

As shown in FIG. 17, the terminals P101, P104, P107, P110, and P113 belonging to the row R1 are used as ground terminals (GND terminals) for noise protection, and are assigned a ground potential. Terminals P102 and P103, P105 and P106, P108 and P109, P111 and P112 belonging to row R1 are used as signal terminals for transmitting differential signal pairs according to the PCIe specification.

To terminals P102 and P103, distribute the received differential signal Rx0 output from the host machine. More specifically, the reception differential signal Rx0+ on the positive side is allocated to the terminal P102, and the reception differential signal Rx0- on the negative side is allocated to the terminal P103. To terminals P105 and P106, distribute the receive differential signal Rx1 output from the host machine. More specifically, the reception differential signal Rx1+ on the positive side is allocated to the terminal P105, and the reception differential signal Rx1- on the negative side is allocated to the terminal P106.

As mentioned above, for the terminals used as the signal terminals for transmitting the differential signal pair according to the PCIe specification, that is, the terminals P102, the terminals P102, P103, P105, P106, allocate the differential signal pair on the receiving side.

The transmission differential signal Tx0 output from the memory device 10 is distributed to the terminals P108 and P109. More specifically, the positive-side transmission differential signal Tx0+ is allocated to the terminal P108, and the negative-side transmission differential signal Tx0- is allocated to the terminal P109. The transmission differential signal Tx1 output from the memory device 10 is allocated to the terminal P111 and the terminal P112. More specifically, the positive-side transmission differential signal Tx1+ is allocated to the terminal P111, and the negative-side transmission differential signal Tx1- is allocated to the terminal P112.

As mentioned above, for the terminals used as the signal terminals for transmitting the differential signal pair according to the PCIe specification, that is, the terminals P108, the terminals P108, P109, P111, P112, allocate the differential signal pair on the sending side.

In the PCIe specification, a differential signal pair on the receiving side and a differential signal pair on the transmitting side constitute one channel. In Fig. 17, one channel is formed by receiving differential signal pair Rx0+ and Rx0-, and transmitting differential signal pair Tx0+ and Tx0-, and one channel is also composed of receiving differential signal pair Rx1+ and Rx1- and transmitting differential signal pair Tx1+ and Tx1-. channel. Thereby, as described above, it is possible to transmit a differential signal pair corresponding to 2 channels of the PCIe standard.

As shown in FIG. 17 , the terminals P102 and P103 assigned to receive differential signal pairs Rx0+ and Rx0 − are located between the terminals P101 and P104 used as ground terminals. Moreover, as shown in FIG. 17, the terminals P105 and P106 to which the reception differential signal pair Rx1+ and Rx1- are allocated are located between the terminals P104 and P107 used as ground terminals. Furthermore, as shown in FIG. 17, the terminals P108 and P109 to which the transmission differential signal pair Tx0+ and Tx0- are allocated are located between the terminals P107 and P110 used as ground terminals. Moreover, as shown in FIG. 17, the terminals P111 and P112 to which the transmission differential signal pair Tx1+ and Tx1- are assigned are located between the terminals P110 and P113 used as ground terminals.

According to the pin assignment shown in Figure 17, the influence of crosstalk can be reduced. Crosstalk refers to a phenomenon that affects adjacent signal wirings or is affected by adjacent signal wirings, resulting in degradation of the signal quality of these signal wirings. In this embodiment, the influence of the transmitted differential signal pair with stronger signal strength on the received differential signal pair with weaker signal strength to degrade the signal quality of the received differential signal pair is considered.

Hereinafter, the effect of the pin assignment of the present embodiment will be described in more detail by taking the stitch assignment shown in FIG. 18 as a comparative example. In addition, the comparative example is used to illustrate some of the effects that can be exerted by the pin allocation of the present embodiment, that is, it is not intended to exclude the common effects of the comparative example and the present embodiment.

Fig. 18 is a diagram showing an example of pin assignment in a comparative example. As shown in Figure 18, the pin allocation of the comparative example is at the point where the differential signal pair Tx0+ and Tx0- are allocated to the terminals P105 and P106, and the differential signal pair Rx1+ and Rx1- are allocated to the terminals P108 and P109. The pin assignments are different.

According to the pin assignment shown in Figure 18, the received differential signal pair Rx0+ and Rx0- assigned to terminals P102 and P103 is affected by the transmitted differential signal pair Tx0+ and Tx0- assigned to terminals P105 and P106, which degrades the signal quality situation. In addition, there are receiving differential signal pairs Rx1+ and Rx1- allocated to terminals P108 and P109, receiving differential transmitting signal pairs Tx0+ and Tx0- allocated to terminals P105 and P106, and transmitting differential signal pairs Tx1+ and Tx1 allocated to terminals P111 and P112. - The impact of the signal degrades the quality of the signal.

On the other hand, according to the pin assignment of this embodiment, as shown in FIG. 17, there are no terminals assigned to send differential signal pairs near the terminals P102 and P103 assigned to receive differential signal pairs Rx0+ and Rx0-, so the receive differential signal The signal pair Rx0+ and Rx0- are hardly affected by crosstalk, which can suppress the degradation of signal quality. Also, as shown in FIG. 17 , near the terminals P105 and P106 assigned to receive differential signal pairs Rx1+ and Rx1-, there are terminals P108 and P109 assigned to transmit differential signal pairs Tx0+ and Tx0-, as terminals P108 and P109 allocated to transmit differential signal pairs. However, as shown in the comparison example, since the receiving differential signal pair Rx1+ and Rx1- is not affected by both the transmitting differential signal pair Tx0+ and Tx0-, and the transmitting differential signal pair Tx1+ and Tx1-, it can be compared In the case of the comparative example, the deterioration of the signal quality was further suppressed.

In addition, in FIG. 17, the receiving differential signal pair Rx0+ and Rx0- have been allocated to the terminals P102 and P103, the receiving differential signal pair Rx1+ and Rx1- have been allocated to the terminals P105 and P106, and the transmitting differential signal pair has been allocated to the terminals P108 and P109. Tx0+ and Tx0-, terminals P111 and P112 are assigned the pin assignments of Tx1+ and Tx1- to transmit differential signals, but the pin assignments that can suppress signal quality degradation due to crosstalk are not limited to this. For example, it is also possible to allocate the transmission differential signal pair Tx1+ and Tx1- to the terminals P102 and P103, the transmission differential signal pair Tx0+ and Tx0- to the terminals P105 and P106, and the reception differential signal pair Rx1+ and Rx1- to the terminals P108 and P109. The terminals P111 and P112 are assigned to receive the differential signal pair Rx0+ and Rx0−. Also in this case, as in the case of FIG. 17 , it is possible to suppress the degradation of signal quality due to crosstalk.

That is, if the terminals on the left and right sides are allocated with the differential signal pairs on the receiving side and the terminals on the other left and right sides are allocated with the differential signal pairs on the transmitting side, then similar to the situation in FIG. The resulting signal quality is degraded.

In addition, in FIG. 17 , the case where the number of terminals belonging to the row R1 is 13 has been described, but the number of terminals belonging to the row R1 is not limited to this, and more terminals than 13 terminals may be arranged in the row R1. When the number of terminals belonging to the row R1 is more than 14 terminals, as shown in FIG. Between the terminals P109 and P110 (in other words, between the terminals assigned to receive differential signal pairs and the terminals assigned to transmit differential signal pairs, the closest terminal), arrange more than two ground terminals P107 and P108, Therefore, the influence of the received differential signal pair Rx1+ and Rx1 − on the transmitted differential signal pair Tx0+ and Tx0 − can be reduced, and the degradation of signal quality can be suppressed.

FIG. 20 is a diagram showing an example of pin assignments of the terminal group P114 to P119 belonging to the row R2 of the memory device 10 and the terminal group P120 to P132 belonging to the row R3. The terminal group P114-P119 belonging to the row R2 is used as signal terminals for any optional signal different from each product. Terminal group P120 to P132 belonging to row R3 are used as signal terminals for control signals and power supply terminals common to each product.

As shown in FIG. 20, terminals P114, P115, P118, and P119 belonging to row R2 are used as ground terminals (GND terminals) for return current. In other words, among the terminal groups P114-P119 belonging to the row R2, a plurality of terminals P114 and P115 arranged between the center line of the memory device 10 and the main body 11 in the X-axis direction and the second edge 32 are used as ground terminals for return current, Furthermore, a plurality of terminals P118 and P119 disposed between the center line of the memory device 10 and the main body 11 in the X-axis direction and the third edge 33 are used as ground terminals for return current.

Terminals P116 and P117 belonging to row R2 are used as spare terminals (RSVD terminals), eg for distributing sideband signals.

Moreover, as shown in FIG. 20, to the terminals P121, P122, P125, and P129 belonging to the row R3, for example, signals of the PCIe standard are assigned. More specifically, the differential signal pair REFCLK+ and REFCLK− are assigned to the terminals P121 and P122. The PERST# signal (reset signal) is assigned to the terminal P125. The CLKREQ# signal is assigned to the terminal P129.

Furthermore, as shown in FIG. 20, terminals P120 and P123 belonging to row R3 are used as ground terminals for noise protection. The terminals P121 and P122 to which the differential signal pair REFCLK+ and REFCLK- are assigned are located between the terminals P120 and P123 used as ground terminals for noise protection.

Also, as shown in FIG. 20, the terminal P124 belonging to the row R3 is used as a ground terminal for return current. Terminals P126 to P128 belonging to row R3 are used as power supply terminals for supplying a second power supply voltage (for example, 1.2 V). The terminals P130 to P132 belonging to the row R3 are used as power supply terminals for supplying the first power supply voltage (for example, 2.5 V).

According to the pin assignment shown in FIG. 20, it is possible to cope with an increase in the amount of current as the performance of the memory device 10 improves. For example, when a PCIe 3.0-compliant device is compared with a PCIe 4.0-compliant device, the PCIe 4.0-compliant device exhibits approximately twice the performance of the PCIe 3.0-compliant device, but consumes more current. According to the pin allocation of this embodiment, it is possible to cope with such an increase in consumption current.

Hereinafter, the effect of the pin assignment of the present embodiment will be described in more detail by taking the pin assignment shown in FIG. 21 as a comparative example. In addition, the comparative example is used to illustrate some of the effects that can be exerted by the pin allocation of the present embodiment, that is, it is not intended to exclude the common effects of the comparative example and the present embodiment.

Fig. 21 is a diagram showing an example of pin assignment in a comparative example. As shown in FIG. 21 , the pin allocation of the comparative example is different from the pin allocation of the present embodiment at the point where the terminals P115 and P118 of the row R2 are used as spare terminals instead of ground terminals for return current. In addition, in the comparative example, the terminal P132 assigned to the row R3 is used as an NC terminal, and the return current ground terminal is not arranged at the point of the row R3, which is different from the assignment of the pins of the present embodiment. Furthermore, the pin assignment of the comparative example is different from the pin assignment of the present embodiment at the point where the terminal P124 adjacent to the terminal P123 used as the ground terminal for noise protection is used as a power supply terminal in the row R3.

According to the pin distribution shown in FIG. 21 , when the consumption current increases with the improvement of the performance of the memory device 10, there is no ground terminal for the return current except the terminals P114 and P119, so it is necessary to make the increased part of the return current in Terminals P120 and P123, which are used as ground terminals for noise protection, flow to cope with an increase in consumption current. If a return current flows through the terminals P120 and P123 used as ground terminals for noise protection, the signal quality of the differential signal pair REFCLK+ and REFCLK- allocated to the terminals P121 and P122 located between these terminals may deteriorate.

On the other hand, according to the pin distribution of this embodiment, as shown in FIG. 20, since the terminals P115 and P118 belonging to the row R2 and the terminal P124 belonging to the row R3 are used as ground terminals for the return current, it is possible to make the additional part The return current flows through the terminals P115 , 118 , and 124 to cope with the increase in consumption current as the performance of the memory device 10 improves. Also, according to the pin assignment of the present embodiment, as described above, since the path for the return current flowing in the increased part can be ensured, the signal quality degradation of the differential signal pair REFCLK+ and REFCLK- can be suppressed. Furthermore, according to the pin assignment of the present embodiment, as shown in the comparative example, since the ground terminal and the power terminal are not adjacently arranged, it is possible to prevent the lead frame corresponding to the ground terminal of the connector 100 from being misaligned due to, for example, vibration. contact with power terminals, etc.

FIG. 22 is a perspective view showing the outer and inner layers of the memory device 10 . As shown in FIG. 22 , on the outer layer of the memory device 10, there are: terminal groups P101-P113 belonging to row R1; terminal groups P114-P119 belonging to row R2; terminal groups P120-P132 belonging to row R3; and through holes VA1～VA12 are used to connect terminals P101, P104, P107, P110, P113, P114, P115, P118, P119, P120, P123, P124 used as grounding terminals and the inner layer.

As shown in FIG. 22, on the inner layer of the memory device 10, a ground plane GP1 is provided, which is electrically connected to the terminals P101, P104, P107, P110, and P113 used as ground terminals for noise protection in the row R1. Hot connect. In the inner layer of the memory device 10, a ground plane GP2 is provided, which is connected with the terminals P114, P115, P118, and P119 used as the ground terminals for the return current in the row R2, and the ground terminals used as the return current in the row R3. The terminal P124 used is electrically and thermally connected. On the inner layer of the memory device 10, there is provided a ground plane GP3, which is electrically and thermally connected to the terminals P120 and P123 used as ground terminals for noise protection in the row R3. The ground planes GP1 to GP3 are formed of copper foil, for example. The ground planes GP1 - GP3 are not electrically connected to each other. In addition, in the inner layer of the memory device 10, through holes VB1-VB12 corresponding to the through holes VA1-VA12 arranged in the outer layer are provided.

The terminals P101 , P104 , P107 , P110 , and P113 provided on the outer layer of the memory device 10 and used as ground terminals are electrically and thermally connected to the ground plane GP1 through the via holes VA1 - VA5 and VB1 - VB5 . The terminals P114, P115, P118, P119, and P124, which are arranged on the outer layer of the memory device 10 and used as ground terminals for return current, are connected to the ground plane GP2 through the through holes VA6-VA9 and VA12 and the through holes VB6-VB9 and VB12. permanent and thermally connected. The terminals P120 and P123 provided on the outer layer of the memory device 10 and used as ground terminals for noise protection are electrically and thermally connected to the ground plane GP3 through the through holes VA10 and VA11 and the through holes VB10 and VB11 .

In addition, in FIG. 22, the case where the ground planes GP1-GP3 are formed in the same layer was illustrated, but it is not limited to this, Each of the ground planes GP1-GP3 may be formed in a different layer.

According to the configuration shown in FIG. 22 (in other words, the pin assignment shown in FIG. 20 ), compared with the configuration of the comparative example shown in FIG. 21 , the heat dissipation effect can be improved. More specifically, compared with the configuration of the comparative example shown in FIG. 21, the configuration shown in FIG. 22 has more terminals used as ground terminals, and more terminals can be electrically and thermally connected to the ground plane GP2. Therefore, the cooling effect can be improved more than that of the comparative example.

According to the second embodiment described above, the memory device 10 includes a pair of terminals (for example, terminals P102 and P103, P105 and P106) to which a differential signal pair for reception is allocated, and a pair of terminals (for example, terminals P102 and P103, P105 and P106) to which a differential signal pair for transmission is allocated For example, terminals P108 and P109, P111 and P112), and between the center line of the main body 11 in the X-axis direction and one side edge (the second edge 32), a pair of terminals assigned to receive a differential signal pair in a complex group is positioned, and in X Between the centerline of the main body 11 in the axial direction and the other side edge (the third edge 33 ), a pair of terminals allocated with a pair of sending differential signals is positioned in a complex group. Thereby, crosstalk can be suppressed, and degradation of signal quality can be suppressed.

Also, according to the second embodiment described above, the memory device 10 includes a plurality of ground terminals (such as terminals P114 and P115) for return currents arranged between the center line of the main body 11 in the X-axis direction and the second edge 32, It also includes a plurality of ground terminals (for example, terminals P118 and P119 ) for return current arranged between the center line of the main body 11 in the X-axis direction and the third edge 33 . Thereby, more of the terminals belonging to the row R2 can be electrically and thermally connected to the ground plane GP2, so the heat dissipation effect can be improved.

(third embodiment) Next, a third embodiment will be described. In addition, the detailed description of the matters already described in the above-mentioned first embodiment and the second embodiment will be omitted, and the following will mainly describe the matters different from the above-mentioned first embodiment and the second embodiment.

23 is used to use the terminals P116 and P117 belonging to the row R2 of the memory device 10 as signal terminals for transmitting sideband signals, and also use the terminals P116 and P117 as SCS terminals and PCD terminals. (That is, a diagram explaining the common use of signal terminals for transmitting sideband signals, SCS terminals, and PCD terminals).

As mentioned above, the SCS terminal is a signal terminal used to input a selection signal before the memory device 10 is activated, and the PCD terminal is a signal terminal used to output a detection signal before the memory device 10 is activated. In contrast, since the sideband signal is a signal input after the memory device 10 is activated, the signal terminal, SCS terminal, and PCD terminal for transmitting the sideband signal can be shared. In addition, before the memory device 10 is activated, it corresponds to the situation that the reset signal is activated, and after the memory device 10 is activated, it corresponds to the situation that the reset signal has been released.

In FIG. 23(A), it is assumed that the terminal P116 belonging to the row R2 of the memory device 10 is shared by the signal terminal for transmitting the sideband signal and the SCS terminal. More specifically, it is assumed that the terminal P116 is used as an SCS terminal before the memory device 10 is activated, and is used as a signal terminal for transmitting sideband signals after the memory device 10 is activated. In addition, in FIG. 23(A), it is assumed that the terminal P117 belonging to the row R2 of the memory device 10 is shared by the signal terminal for transmitting the sideband signal and the PCD terminal. More specifically, it is assumed that the terminal P117 is used as a PCD terminal before the memory device 10 is activated, and is used as a signal terminal for transmitting sideband signals after the memory device 10 is activated.

As shown in Figure 23(B), before the device is started, the terminal P116 used as the SCS terminal is input with a high (High) level selection signal. After the device is started, the terminal P116 is used to transmit the first side The signal terminal with the signal SB1 is used, and the terminal P117 is used as the signal terminal for transmitting the second sideband signal SB2. In other words, before the device is started, if a high-level selection signal is input to the terminal P116 used as the SCS terminal, after the device is started, the terminals P116 and P117 are used to transmit the sideband signal SB1 of the first configuration And the signal terminal of SB2 is used.

On the other hand, as shown in Figure 23(B), before the device is started, if a low (Low) level selection signal is input to the terminal P116 used as the SCS terminal, after the device is started, the terminal P116 is used as the SCS terminal. The signal terminal for transmitting the third sideband signal SB3 is used, and the terminal P117 is used as a signal terminal for transmitting the fourth sideband signal SB4. In other words, before the device is started, if a low (Low) selection signal is input to the terminal P116 used as the SCS terminal, after the device is started, the terminals P116 and P117 are used to transmit the sideband signal SB3 of the second configuration And the signal terminal of SB4 is used.

As shown in FIG. 23(C), when a detection signal of High level is output from the terminal P117 used as a PCD terminal before the device is started, the host machine recognizes that the power supply of the memory device 10 is composed of 2 power supplies. On the other hand, as shown in FIG. 23(C), before the device is started, when the detection signal of the low (Low) level is output from the terminal P117 used as the PCD terminal, the host machine recognizes the power supply of the memory device 10 as follows: 1 power supply.

Here, an example of the operation of the memory device 10 having the structure shown in FIG. 23 will be described with reference to the timing chart of FIG. .

As shown in FIG. 24 , at the first timing T1 , under the control of the host device (the host control unit 201 ), supply of the first power supply voltage to the memory device 10 starts. When the first power supply voltage is started to be supplied to the memory device 10, a detection signal is output from the PCD terminal of the memory device 10 (ie, the terminal P117 before device startup) to the host machine in the second timing T2. In the third timing T3, the host device reads the detection signal output by the memory device 10, identifies the power supply configuration of the memory device 10, and determines whether to supply the second power supply voltage. Also, in the third timing T3, the host device establishes the terminal P116 used as the SCS terminal, and then outputs a selection signal to the memory device 10 .

In the fourth timing T4 after identifying the power source configuration of the memory device 10 , the reset signal of low (low) level is deasserted. Thereby, the terminal P117 used as the PCD terminal is used as a signal terminal for transmitting a sideband signal having a configuration corresponding to the level of the selection signal input to the SCS terminal in a subsequent period. Thereafter, in the fifth timing T5, the host device deasserts the terminal P116 used as the SCS terminal, and the terminal P116 is used as a sideband for transmitting a configuration corresponding to the level of the selection signal input to the SCS terminal in the following period The signal terminal of the signal is used.

According to the structure shown in FIG. 23 and FIG. 24, since the signal terminal for transmitting the sideband signal, the SCS terminal, and the PCD terminal can be shared, the design freedom of the pin assignment of the memory device 10 can be improved. For example, as shown in FIG. 20 and FIG. 22 , the number of terminals used as ground terminals for return current can be increased.

According to the third embodiment described above, the memory device 10 includes at least two signal terminals (such as terminals P116 and P117) assigned sideband signals. A selection signal is input, and a detection signal is output from another signal terminal (for example, terminal P117 ). After the memory device 10 is activated, sideband signals are input to these two signal terminals. Thereby, the signal terminal for transmitting the sideband signal, the SCS terminal, and the PCD terminal can be shared, and the design freedom of the pin assignment of the memory device 10 can be improved.

According to at least one embodiment described above, a memory device 10 capable of improving heat dissipation efficiency can be provided.

In addition, in this embodiment, a NAND type flash memory is exemplified as a nonvolatile memory. However, the functions of this embodiment can also be applied to, for example, MRAM (Magnetoresistive Random Access Memory: Magnetic Random Access Memory), PRAM (Phase change Random Access Memory: Phase Change Random Access Memory), ReRAM (Resistive Random Access Memory : Resistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory: Ferroelectric Random Access Memory) and various other non-volatile memories.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or variations thereof are included in the scope or gist of the invention, and are included in the inventions described in the scope of the patent application and their equivalents.

This application is based on Japanese Patent Application No. 2020-033519 (Filing Date: 2/28/2020) and Japanese Patent Application No. 2020-126444 (Filing Date: 7/27/2020). The priority interest of other applications. This application incorporates the entire contents of the same applications by reference to these applications.

10: Memory device 10a: 1st Generation Memory Devices 10A: memory device 10b: 2nd Generation Memory Devices 10B: memory device 10C: memory device 10D: memory device 11: Ontology 12: Printed circuit substrate 13: NAND flash memory 14: Controller 15: switch 21: Side 1 22: Side 2 23: outer edge 31: The first edge 32: The second edge 33: The third edge 34: The 4th Edge 35: 1st corner 36: the second corner 37: 3rd corner 38: 4th corner 39: Inclined part 40: Molding resin 100: Connector 100A: Connector 100B: connector 100C: connector 100D: connector 101～103: lead frame 104: Lead frame terminal 105: Installation department 106:Connector frame 107: TIM 111: The first edge 112: The second edge 113: The third edge 114: The fourth edge 115: connection part 116: Gap 120: cover 201: Host control department 202: switch 202A: pull-up resistor 203: Tri-state buffer A1: Contact area A2: Attachment area A11: Contact area A12: Contact area A13: Contact area A14: Contact area A21: Attachment area A22: Attachment area A23: Attachment area A24: Attachment area C: chamfer CLKREQ#: signal D1: distance D2: distance D3: Distance GP1: ground plane GP2: ground plane GP3: ground plane P: terminal P101～P132: terminals PCD: terminal PERST#: signal r1: row R1: row r2: row R2: Row r3: row R3: Row REFCLK+: differential signal pair REFCLK-: differential signal pair RSVD: terminal Rx0+: Receive differential signal Rx0-: Receive differential signal Rx1+: Receive differential signal Rx1-: Receive differential signal SB1: 1st sideband signal SB2: 2nd sideband signal SB3: 3rd sideband signal SB4: 4th sideband signal SB5: 5th sideband signal SB6: 6th sideband signal SB7: 7th sideband signal SB8: The 8th sideband signal SCS: terminal T1: the first timing T2: the second timing T3: The third timing T4: The 4th timing T5: The fifth timing Tx0+: send differential signal Tx0-: Send differential signal Tx1+: send differential signal Tx1-: send differential signal VA1～VA12: Through hole VB1～VB12: Through hole

1(A) to (C) are diagrams showing examples of the external shape of the memory device according to the first embodiment. Fig. 2 is a diagram showing a configuration example of a memory device of the same embodiment. Fig. 3 is a top view showing the outline shape and arrangement example of a plurality of terminals of the memory device of the same embodiment. Fig. 4 (A), (B) is the top view showing the outline shape of the memory device of the same embodiment, the outline shape of the connector for mounting the memory device, and the configuration example of the region where the TIM is attached. Fig. 5 is a side view showing a state in which a memory device of the same embodiment is installed in a connector. 6(A) and (B) are diagrams for explaining the case where the terminals of the memory device of the same embodiment are used as SCS terminals. FIG. 7 is a diagram showing a host control unit and switches arranged on a substrate of a host device using the memory device of the same embodiment. 8(A) and (B) are top views showing the external shapes of the memory devices of the same embodiment, that is, the memory devices with 2 power supplies and the memory devices with 1 power supply. 9(A) and (B) are diagrams for explaining the situation where the terminals of the memory device of the same embodiment are used as PCD terminals. 10(A) and (B) are diagrams showing internal circuits of memory devices of the same embodiment, that is, memory devices with 2 power supplies and memory devices with 1 power supply. 11(A) and (B) are diagrams for explaining the case where one terminal of the memory device of the same embodiment is used as an SCS terminal or as a PCD terminal. Fig. 12 is a timing chart showing an example of the operation when one terminal of the memory device of the same embodiment is used as the SCS terminal or as the PCD terminal. 13(A) and (B) are top views showing the shape of the memory device of the first modification, the shape of the connector for mounting the memory device, and the configuration example of the area where the TIM is attached. Fig. 14 (A), (B) is the top view showing the outline shape of the memory device of the second variation example, the outline shape of the connector for mounting the memory device, and the configuration example of the region where the TIM is attached. 15(A) and (B) are top views showing the external shape of the memory device of the third modification, the external shape of the connector for mounting the memory device, and the arrangement example of the region where the TIM is attached. 16(A) and (B) are top views showing the shape of the memory device of the fourth variation, the shape of the connector for mounting the memory device, and the configuration example of the area where the TIM is attached. Fig. 17 is a diagram showing an example of the pin assignment of the memory device according to the second embodiment. FIG. 18 is a diagram showing pin assignments of a comparative example with respect to the configuration of FIG. 17 . Fig. 19 is a diagram showing another example of pin allocation of the memory device of the same embodiment. Fig. 20 is a diagram showing an example of the pin assignment of the memory device of the same embodiment. FIG. 21 is a diagram showing pin assignments of a comparative example with respect to the configuration of FIG. 20 . Fig. 22 is a perspective view showing the outer layer and inner layer of the memory device of the same embodiment. 23(A) to (C) are diagrams for explaining how the terminals of the memory device according to the third embodiment share a signal terminal for transmitting sideband signals, an SCS terminal, and a PCD terminal. FIG. 24 is a timing chart showing an example of the operation in the case where the terminals of the memory device of the same embodiment share a signal terminal for transmitting sideband signals, an SCS terminal, and a PCD terminal.

10: Memory device

11: Ontology

21: Side 1

22: Side 2

23: outer edge

31: The first edge

32: The second edge

33: The third edge

34: The 4th Edge

35: 1st corner

36: the second corner

37: 3rd corner

38: 4th corner

39: Inclined part

C: chamfer

R2: Row

R3: Row

Claims (20)

A semiconductor memory device, comprising: a body, which has: a first surface; a second surface located on the opposite side of the first surface; a first edge extending in a first direction; located on the opposite side of the first edge And the second end edge extending in the above-mentioned first direction; the first side edge extending in the second direction intersecting the above-mentioned first direction; and the second edge located on the opposite side of the above-mentioned first side edge and extending in the above-mentioned second direction 2 side edges; a memory, which is arranged inside the above-mentioned body; a controller, which is arranged inside the above-mentioned body to control the above-mentioned memory; and a plurality of terminals, including a plurality of signal terminals for transmitting signals, and in The above-mentioned first surface is exposed; and the above-mentioned plurality of terminals form at least the first row and the second row; the above-mentioned first row contains a plurality of terminals, which are equal to the position closer to the above-mentioned first end edge than the above-mentioned second end edge, and are spaced apart from each other Arranged in the above-mentioned first direction; the above-mentioned second row contains a plurality of terminals, which are equal to the position closer to the above-mentioned second end edge than the above-mentioned first end edge, and are arranged at intervals in the above-mentioned first direction; the above-mentioned first side of the above-mentioned first surface The area between the first row and the second row includes a contact area that is in contact with a thermally conductive member that is disposed on a substrate of a host machine that can be electrically connected to the above-mentioned semiconductor memory device. The semiconductor memory device according to claim 1, wherein the distance between the first row and the second row in the second direction is longer than the distance between the first row in the second direction and the first edge, and is longer than the The 2nd row above in the 2nd direction The distance from the above-mentioned second edge. The semiconductor memory device according to claim 1 or 2, wherein the plurality of terminals forming the first row include at least one pair of differential data signal terminals assigned to differential data signals; the plurality of terminals forming the second row, Contains a power supply terminal assigned to supply the power supply voltage from the above-mentioned host machine. The semiconductor memory device according to claim 3, wherein the above-mentioned differential data signal is based on the PCIe standard; the above-mentioned plurality of terminals forming the above-mentioned first row includes a plurality of pairs of the above-mentioned differential data signal terminals that are allocated to a plurality of channels of the above-mentioned differential data signal . The semiconductor memory device according to claim 1 or 2, wherein the plurality of terminals further form a third row; the third row includes: a plurality of terminals, which are equal to the position between the first row and the second row, and are arranged at intervals in the above The first direction: the number of terminals forming the above-mentioned third row is less than the number of terminals forming the above-mentioned first row or the above-mentioned second row; the above-mentioned contact area includes a space equivalent to the number of terminals forming the above-mentioned third row than the number of terminals forming the above-mentioned first row The area where the number of terminals is the smallest. The semiconductor memory device according to claim 5, wherein the third row is located closer to the second edge than the first edge, and is located closer to the second edge than the first edge 2 rows are farther away from the above-mentioned 2nd end edge. The semiconductor memory device according to claim 5, wherein the third row is located closer to the first edge than the second edge, and is further away from the first edge than the first row. The semiconductor memory device according to claim 6, wherein the third row includes the same number of terminals between the center line of the body in the first direction and the first side edge, and between the center line and the second side edge . The semiconductor memory device according to claim 6, wherein the third row includes different numbers of terminals between the center line of the body and the first side edge, and between the center line and the second side edge in the first direction. . The semiconductor memory device according to claim 9, wherein the third row includes the plurality of terminals between the center line and the first side edge, and between the center line and the second side edge. The semiconductor memory device according to claim 5, wherein the plurality of terminals forming the third row include at least one ground terminal assigned to a ground line, and at least one sideband signal terminal assigned to a sideband signal of the PCIe specification. The semiconductor memory device according to claim 11, wherein The above-mentioned plurality of terminals forming the above-mentioned second row include a first terminal, which is assigned to a selection signal for selecting the configuration of the above-mentioned sideband signal; when the above-mentioned first terminal is input with the above-mentioned When the signal is selected, the first sideband signal is assigned to the at least one sideband signal terminal. When the first terminal is input with the selection signal of Low (low) level, the at least one sideband signal terminal is A second sideband signal different from the above-mentioned first sideband signal is distributed. The semiconductor memory device according to claim 11, wherein the plurality of terminals forming the second row include a second terminal assigned to a detection signal, the detection signal being used by the host machine to detect the power supply of the semiconductor memory device; When the power supply configuration of the semiconductor memory device is configured to operate with multiple power supply voltages, the controller outputs the detection signal of High (high) level to the host device through the second terminal. When the power supply configuration of the semiconductor memory device is configured to operate with one power supply voltage, the controller outputs the detection signal of Low level to the host device through the second terminal. The semiconductor memory device according to claim 1, wherein the plurality of terminals forming the first row include a pair of terminals assigned to receive differential data signals and a pair of terminals assigned to transmit differential data signals Sending differential data signal terminals; the above-mentioned pair of receiving differential data signal terminals in a complex group is located between the center line of the above-mentioned body in the first direction and one side edge, and the above-mentioned pair of sending differential data signal terminals in a complex group is located in the above-mentioned between the center line and the other side edge. The semiconductor memory device according to claim 14, wherein the pair of terminals for receiving differential data signals and the pair of terminals for transmitting differential data signals are arranged between ground terminals for noise protection. The semiconductor memory device according to claim 14, wherein the plurality of terminals further form a third row; the third row includes: a plurality of terminals, which are equal to the position between the first row and the second row, and are arranged at intervals in the first row 1 direction: the plurality of terminals forming the third row include a plurality of ground terminals for return current arranged between the center line and the first side edge, and include a plurality of ground terminals arranged between the center line and the second side edge A plurality of ground terminals for the above return current. The semiconductor memory device according to claim 16, wherein said plurality of terminals forming said second row includes at least one ground terminal for said return current. The semiconductor memory device according to claim 17, further comprising: a first ground plane connected to the ground terminal for noise protection; and a second ground plane connected to the ground terminal for return current in the above-mentioned main body ; and the first ground plane is not electrically connected to the second ground plane. The semiconductor memory device according to claim 16, wherein the plurality of terminals forming the third row include at least two signal terminals assigned to sideband signals; Select the selection signal for the composition of the above-mentioned sideband signal, and output a detection signal from the other signal terminal for the above-mentioned host machine to detect the power supply of the above-mentioned semiconductor memory device; after the above-mentioned semiconductor memory device is started, the above-mentioned two signals The terminal inputs the above-mentioned sideband signal. The semiconductor memory device according to claim 19, wherein the plurality of terminals forming the second row include a signal terminal assigned to a reset signal; when the reset signal acts, the selection signal is input to the one signal terminal, And the detection signal is output from the other signal terminal; when the reset signal is released, the sideband signal is input to the two signal terminals.

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