TWI784806B - Bias circuit and signal amplification device - Google Patents

Abstract

A bias circuit includes a current mirror circuit, an operational amplifier, and a bias signal generating circuit. The current mirror circuit includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to a base current, and the at least one mirror branch circuit generates at least one mirrored current according to the reference current. The operational amplifier is coupled to the reference branch circuit and the at least one mirror branch circuit, receives a first voltage and a second voltage, and adjusts the first voltage by generating a control voltage according to the second voltage. The bias signal generating circuit is coupled to the at least one mirror branch circuit and generates a bias signal according to the at least one mirrored current. The first voltage is a voltage on the reference branch circuit. The second voltage is a voltage on the at least one mirror branch circuit or an adjusted version of the voltage on the at least one mirror branch circuit.

Description

Bias circuit and signal amplifier

The invention relates to a bias circuit, in particular to a bias circuit capable of generating a stable bias signal according to mirror current.

Ideally, the voltage source is used to provide a reference voltage with a fixed voltage value, so that the bias circuit can generate a bias signal according to the reference voltage. However, due to uncontrollable variations in the manufacturing process or other factors, the voltage value of the reference voltage may be offset, which affects the stability of the bias signal.

An embodiment of the present invention provides a bias circuit, which includes a current mirror circuit, an operational amplifier, and a bias signal generating circuit. The current mirror circuit includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to the reference current, and at least one mirror branch circuit generates at least one mirror current according to the reference current. The operational amplifier is coupled to the reference branch circuit and at least one mirror branch circuit, receives the first voltage and the second voltage, and generates a control voltage according to the second voltage to adjust the first voltage. The bias signal generating circuit is coupled to at least one mirror branch circuit, and generates a bias signal according to at least one mirror current. The first voltage is the voltage on the reference branch circuit, and the second voltage is the voltage on at least one mirroring branch circuit or the adjusted voltage on at least one mirroring branch circuit.

Another embodiment of the present invention provides a signal amplifying device. The signal amplifying device includes partial Pressure circuit, input terminal, output terminal and amplifier. The bias circuit includes a current mirror circuit, an operational amplifier and a bias signal generating circuit. The current mirror circuit receives a reference voltage and includes a reference branch circuit and at least one mirror branch circuit. The reference branch circuit generates a reference current according to the reference current, and at least one mirror branch circuit generates at least one mirror current according to the reference current. The operational amplifier is coupled to the reference branch circuit and at least one mirror branch circuit, receives the first voltage and the second voltage, and generates a control voltage according to the reference second voltage to adjust the first voltage. The bias signal generating circuit is coupled to at least one mirror branch circuit, and generates a bias signal according to at least one mirror current. The first voltage is the voltage on the reference branch circuit, and the second voltage is the voltage on at least one mirroring branch circuit or the adjusted voltage on at least one mirroring branch circuit. The input terminal receives the radio frequency signal, and the output terminal outputs the amplified radio frequency signal. The amplifier is coupled between the input terminal of the signal amplifying device and the output terminal of the signal amplifying device, receives the bias voltage signal and amplifies the radio frequency signal.

10, 20: Signal amplification device

100 to 500, 1001 to 1003, 2001 to 2003: bias circuit

110, 510: current mirror circuit

112, 512: reference branch circuit

114, 514, 516: mirror branch circuits

120, 520: operational amplifier

130, 530: bias signal generation circuit

132, 532, 560: regulator circuit

240, 440, 540: start circuit

350, 450, 550: voltage selection circuit

671 to 673, 771, 772: Low Dropout Regulators

AMP, AMP1 to AMP3: Amplifiers

C1A, C2A, C1B to C4B, C0: capacitance

CSA, CSB: current source

D1A, D2A, D1B to D4B: Diodes

IB: Reference current

Im1, Im2: mirror current

Iref: reference current

Is: starting current

N1 to N3: nodes

NB, NB1 to NB3: Bias terminals

P1: external pin

R1A to R3A, R1B to R4B: Resistors

RFIN: input terminal

RFOUT: output terminal

Sbias, Sbias1 to Sbias3: Bias signal

Srf1, Srf2: RF signal

T1A to T5A, T1B to T6B: Transistors

V1: first voltage

V2: second voltage

Vctrl: control voltage

VDD1, VDD2: operating voltage terminal

VN1 to VN3: voltage

VR1 to VR3: Reference voltage

Vref, Vref1 to Vref3: reference voltage terminals

Vset1: the first preset voltage

Vset2: the second preset voltage

VSP: supply voltage terminal

VSS: reference voltage terminal

Fig. 1 is a schematic diagram of a bias circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

Fig. 3 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

Fig. 5 is a schematic diagram of a bias circuit according to another embodiment of the present invention.

Fig. 6 is a schematic diagram of a signal amplifying device according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of a signal amplifying device according to another embodiment of the present invention.

FIG. 1 is a schematic diagram of a bias circuit 100 according to an embodiment of the present invention. The bias circuit 100 includes a current mirror circuit 110 , an operational amplifier 120 and a bias signal generating circuit 130 .

The current mirror circuit 110 can include a reference branch circuit 112 and a mirror branch circuit 114 . The reference subcircuit 112 can generate the reference current Iref according to the reference current IB, and the mirror subcircuit 114 can generate the mirror current Im1 according to the reference current Iref.

The operational amplifier 120 can be coupled to the reference branch circuit 112 and the mirror branch circuit 114 to receive the first voltage V1 and the second voltage V2, and can be used to generate the control voltage Vctrl according to the second voltage V2 to adjust the first voltage V1, so that The first voltage V1 and the second voltage V2 tend to be equal. In some embodiments, the first voltage V1 may be the voltage on the reference sub-circuit 112 , and the second voltage V2 may be the voltage on the mirroring sub-circuit 114 or the voltage on the regulated mirroring sub-circuit 114 . The bias signal generating circuit 130 can be coupled to the mirror branch circuit 114 and can generate a bias signal Sbias according to the mirror current Im1.

In some embodiments, the bias signal generating circuit 130 can provide the bias signal Sbias to the amplifier AMP. For example, the amplifier AMP can amplify the radio frequency signal Srf1 received from the input terminal RFIN to output the amplified radio frequency signal Srf2 from the output terminal RFOUT, and the bias signal generating circuit 130 can output the bias signal Sbias to the bias signal of the amplifier AMP. The voltage terminal NB enables the amplifier AMP to operate at a proper bias voltage to maintain the performance of the amplifier AMP. In some embodiments, the bias signal Sbias can be a current signal.

In FIG. 1 , the current mirror circuit 110 may further include a current source CSA and a transistor T3A, and the reference branch circuit 112 may include a node N1 , transistors T1A and T4A. The current source CSA can be coupled to the operating voltage terminal VDD1 for generating the reference current IB. The transistor T3A has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T3A can be coupled to the current source CSA to receive the reference current IB, the second terminal of the transistor T3A can be coupled to the reference voltage terminal VSS, and the control terminal of the transistor T3A can be coupled to the transistor The first end of T3A. The node N1 can be disposed between the transistors T1A and T4A. The transistor T1A may have a first terminal, a second terminal and a control terminal. The first terminal of the transistor T1A can be coupled to the reference voltage terminal Vref, and the second terminal of the transistor T1A can be coupled to the node N1. The transistor T4A has a first terminal, a second terminal and a control terminal. The first end of the transistor T4A can be coupled to the node N1, the second end of the transistor T4A can be coupled to the reference voltage terminal VSS, and the transistor The control terminal of T4A can be coupled to the control terminal of transistor T3A. That is to say, the transistors T3A and T4A can form a current mirror structure for mirroring the reference current IB to generate the reference current Iref.

In addition, the mirror branch circuit 114 may include a node N2 and a transistor T2A. The node N2 can be disposed between the transistor T2A and the bias signal generating circuit 130 . The transistor T2A has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T2A can be coupled to the reference voltage terminal Vref, the second terminal of the transistor T2A can be coupled to the node N2, and the control terminal of the transistor T2A can be coupled to the control terminal of the transistor T1A. In this way, the voltage difference between the control terminal and the first terminal of the transistor T1A can be substantially equal to the voltage difference between the control terminal and the first terminal of the transistor T2A, and the transistors T1A and T2A can form a current mirror The structure of is used to mirror the reference current Iref to generate the mirror current Im1. In some embodiments, the designer can select the size of the transistors T1A and T2A (ie, the width-to-length ratio of the transistors T1A and T2A) to adjust the ratio between the reference current Iref and the mirror current Im1. For example, the size of the transistor T2A can be larger than that of the transistor T1A, so that the mirror current Im1 is larger than the reference current Iref.

In FIG. 1 , the operational amplifier 120 may have a first input terminal, a second input terminal and an output terminal. The first input terminal of the operational amplifier 120 can be coupled to the node N1, the second input terminal of the operational amplifier 120 can be coupled to the node N2, and the output terminal of the operational amplifier 120 can be coupled to the control terminal of the transistor T1A and the transistor T2A. the control terminal. In Fig. 1, the first voltage V1 is the voltage VN1 on the node N1 (ie, the voltage on the reference branch circuit 112), and the second voltage V2 is the voltage VN2 on the node N2 (ie, the voltage on the mirror branch circuit 114) As an example.

In some embodiments, the bias signal generating circuit 130 may include a voltage stabilizing circuit 132 , a transistor T5A, a resistor R1A, and a capacitor C1A. The voltage stabilizing circuit 132 has a first terminal and a second terminal. The first terminal of the voltage stabilizing circuit 132 can be coupled to the node N2, and the second terminal of the voltage stabilizing circuit 132 can be coupled to the reference voltage terminal VSS. The voltage stabilizing circuit 132 may include a resistor R2A, diodes D1A and D2A. The resistor R2A has a first terminal and a second terminal. The first end of the resistor R2A can be coupled to the first end of the voltage stabilizing circuit 132 . The diode D1A has a first end and a second end. The first terminal of the diode D1A can be coupled to the second terminal of the resistor R2A. Diode D2A has a first terminal and the second end. The first terminal of the diode D2A can be coupled to the second terminal of the diode D1A, and the second terminal of the diode D2A can be coupled to the second terminal of the voltage stabilizing circuit 132 . The transistor T5A has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T5A can be coupled to the operating voltage terminal VDD2, and the control terminal of the transistor T5A can be coupled to the second terminal of the resistor R2A. The resistor R1A has a first terminal and a second terminal. The first terminal of the resistor R1A can be coupled to the second terminal of the transistor T5A, and the second terminal of the resistor R1A can be coupled to the bias terminal NB of the amplifier AMP and can be used to output the bias signal Sbias. The capacitor C1A has a first terminal and a second terminal. The first terminal of the capacitor C1A can be coupled to the control terminal of the transistor T5A, and the second terminal of the capacitor C1A can be coupled to the reference voltage terminal VSS.

In some embodiments, in order to accurately mirror the reference current Iref to generate a stable mirror current Im1, not only the voltage difference between the control terminal and the first terminal of the transistor T1A and the control terminal of the transistor T2A need to be The voltage difference between the terminal and the first terminal is designed to be substantially equal, and the voltage difference between the second terminal and the first terminal of the transistor T1A is the same as the voltage difference between the second terminal and the first terminal of the transistor T2A They also need to be designed to be substantially equal. Furthermore, when the mirror current Im1 flows through the voltage stabilizing circuit 132 , the resistor R2A will generate a voltage drop and turn on the diodes D1A and D2A. In this case, the second voltage V2 (ie, the voltage VN2 ) can be regarded as the sum of the voltage drop of the resistor R2A and the turn-on voltages of the diodes D1A and D2A. The transistor T1A and the operational amplifier 120 can form a negative feedback loop, so the first input terminal and the second input terminal of the operational amplifier 120 can have a virtual short characteristic. That is to say, the control voltage Vctrl generated by the operational amplifier 120 can make the first voltage V1 follow the change of the second voltage V2, so that when the bias circuit 100 operates in the operation mode, the first voltage V1 and the second voltage V2 can be controlled. to be substantially equal. In this way, the voltage difference between the second terminal and the first terminal of the transistor T1A can be substantially equal to the voltage difference between the second terminal and the first terminal of the transistor T2A, so that the reference current Iref can be accurately measured. The ground is mirrored to generate a stable mirror current Im1, so that the bias signal generating circuit 130 can generate a stable bias signal Sbias accordingly.

In some embodiments, the bias signal generating circuit 130 and the amplifier AMP can be arranged in the first One die, and the current mirror circuit 110 and the operational amplifier 120 can be disposed on the second die.

In some embodiments, when the system is just powered on, the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS (such as 0V) or the voltage on the reference voltage terminal Vref (such as 3V), resulting in The current mirror circuit 110 cannot work normally. In order to solve the problem that the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS, the bias circuit 100 may further include a startup circuit, which is used to make the second voltage V2 has an appropriate operating potential, so as to adjust the first voltage V1 accordingly.

FIG. 2 is a schematic diagram of a bias circuit 200 according to another embodiment of the present invention. Bias circuits 200 and 100 have similar structures and operate according to similar principles. However, the bias circuit 200 may also include a startup circuit 240 . The start-up circuit 240 can be coupled to the reference voltage terminal Vref and the node N2, and can generate a start-up current Is to make the voltage VN2 reach a preset value when the bias circuit 200 operates in the start-up mode, and the second voltage V2 will also reach a predetermined value accordingly. Preset value with proper operating potential. That is to say, FIG. 2 takes the second voltage V2 as the adjusted voltage on the mirror branch circuit 114 as an example for illustration. In some embodiments, the starting current Is can be a pulse signal. In this way, the operational amplifier 120 can correspondingly output the control voltage Vctrl, so that the first voltage V1 changes from the initial value to follow the preset value of the second voltage V2, and when the bias circuit 200 enters the operation mode, the first The voltage V1 tends to be equal to the second voltage V2. Therefore, the current mirroring circuit 110 can operate normally, so that the reference current Iref can be accurately mirrored to generate a stable mirrored current Im1, so that the bias signal generating circuit 130 can generate a stable bias signal Sbias accordingly.

Not only that, since the start-up circuit 240 can raise the second voltage V2 to a preset value in advance when the bias circuit 200 starts up, it can shorten the time for the operational amplifier 120 to adjust the first voltage V1 and ensure that the current mirror circuit 110 Can operate in a stable state to provide a stable mirror current Im1. In addition, the temperature of the amplifier AMP will increase with the operation time, resulting in a decrease in gain. However, the start-up current Is generated by the start-up circuit 240 when the bias circuit 200 starts up can also be used to preheat the amplifier AMP, and there is It helps the amplifier AMP to maintain the gain within a predetermined range during subsequent operation.

FIG. 3 is a schematic diagram of a bias circuit 300 according to another embodiment of the present invention. Bias circuits 300 and 100 have a similar structure and operate according to similar principles. However, the bias circuit 300 may also include a voltage selection circuit 350 . The voltage selection circuit 350 can be coupled to the second input terminal of the operational amplifier 120 and the node N2. The voltage selection circuit 350 can set the second voltage V2 according to the voltage VN2. For example, when the voltage VN2 is greater than an upper limit voltage, the voltage selection circuit 350 can set the second voltage V2 to a first preset voltage Vset1 that is less than or equal to the upper limit voltage. In some embodiments, the upper limit voltage may be lower than the voltage on the reference voltage terminal Vref, and the first preset voltage Vset1 may be, for example but not limited to, 2.8V. Alternatively, when the voltage VN2 is less than the lower limit voltage, the voltage selection circuit 350 can set the second voltage V2 to a second preset voltage Vset2 greater than or equal to the lower limit voltage. In some embodiments, the second preset voltage Vset2 may be, for example but not limited to, 2V. In some embodiments, the first predetermined voltage Vset1 and the second predetermined voltage Vset2 can be set to meet the operating voltage of the operational amplifier 120 and the operating voltage of the current mirror formed by the transistors T3A and T4A. Alternatively, when the voltage VN2 is between the upper limit voltage and the lower limit voltage, the voltage selection circuit 350 can set the second voltage V2 to be equal to the voltage VN2 . That is to say, FIG. 3 takes the second voltage V2 as the adjusted voltage on the mirroring branch circuit 114 or the voltage on the mirroring branch circuit 114 as an example for illustration. In some embodiments, the second voltage V2 can be set to a value enabling the transistors T1A and T2A to operate in a saturation region.

Since the voltage selection circuit 350 can adjust the second voltage V2 according to the magnitude of the voltage VN2, the second voltage V2 can be set to an appropriate voltage value when the bias circuit 300 starts, so that the operational amplifier 120 can adjust accordingly The first voltage V1, and when the bias circuit 300 enters the operation mode, the first voltage V1 will tend to be equal to the second voltage V2. In this way, it can not only solve the problem that the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS or the voltage on the reference voltage terminal Vref in the first figure, but also shorten the operation amplifier 120 to adjust the first voltage. A voltage V1, and ensure that the current mirror circuit 110 can operate in a stable state to provide a stable mirror current Im1.

FIG. 4 is a schematic diagram of a bias circuit 400 according to another embodiment of the present invention. bias circuit 400 with Bias circuits 200 and 300 have similar structures and operate according to similar principles. However, the bias circuit 400 may include a startup circuit 440 and a voltage selection circuit 450 . For example, in the startup mode, the bias circuit 400 can not only use the voltage selection circuit 450 to set the second voltage V2 according to the voltage VN2, but also use the startup circuit 440 to preheat the amplifier AMP. In this way, it can not only solve the problem that the first voltage V1 and the second voltage V2 may be the voltage on the reference voltage terminal VSS or the voltage on the reference voltage terminal Vref in the first figure, but also shorten the operation amplifier 120 to adjust the first voltage. A voltage V1, and ensure that the current mirror circuit 110 can operate in a stable state to provide a stable mirror current Im1. In addition, it also helps to maintain the gain of the amplifier AMP within a predetermined range. That is to say, FIG. 4 takes the second voltage V2 as the adjusted voltage on the mirroring branch circuit 114 or the voltage on the mirroring branch circuit 114 as an example for illustration.

In some embodiments, when the amplifier AMP is in operation, the radio frequency signal Srf1 may leak from the input terminal RFIN to the mirror branch circuit 114 through the bias signal generating circuit 130, causing the stability of the voltage VN2 to be affected, thereby affecting the second Stability of voltage V2. However, in the bias circuits 100 to 400, the resistor R2A and the capacitor C1A in the bias signal generating circuit 130 can be used as a low-pass filter to filter out the undesired radio frequency signal Srf1, so as to reduce the radio frequency signal Srf1 to the voltage The disturbance of VN2 maintains the stability of the second voltage V2. In addition, the bias circuits 100 to 400 may further include a resistor R3A and a capacitor C2A. The resistor R3A has a first terminal and a second terminal. The first terminal of the resistor R3A can be coupled to the second input terminal of the operational amplifier 120 , and the second terminal of the resistor R3A can be coupled to the node N2 . The capacitor C2A has a first terminal and a second terminal. The first terminal of the capacitor C2A can be coupled to the first terminal of the resistor R3A, and the second terminal of the capacitor C2A can be coupled to the reference voltage terminal VSS. The resistor R3A and the capacitor C2A can also be used as a low-pass filter to filter out the undesired radio frequency signal Srf1, so as to reduce the interference of the radio frequency signal Srf1 to the second voltage V2. In some embodiments, in order to improve the stability of the second voltage V2 , another mirror branch circuit can be added in the current mirror circuit 110 .

FIG. 5 is a schematic diagram of a bias circuit 500 according to another embodiment of the present invention. Bias circuits 500 and 400 have similar structures and operate according to similar principles. However, the current mirror of bias circuit 500 The mirror circuit 510 may include a reference branch circuit 512 , a mirror branch circuit 514 and a mirror branch circuit 516 . The mirroring branch circuit 514 can generate the mirroring current Im1 according to the reference current Iref, and the mirroring branch circuit 516 can generate the mirroring current Im2 according to the reference current Iref. In this case, the bias signal generating circuit 530 can generate the bias signal Sbias according to the mirror current Im1.

In FIG. 5, the current mirror circuit 510 may further include a current source CSB and a transistor T3B, and the reference branch circuit 512 may include a node N1, transistors T1B and T4B. The current source CSB can be coupled to the operating voltage terminal VDD1 for generating the reference current IB. The transistor T3B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T3B can be coupled to the current source CSB to receive the reference current IB, the second terminal of the transistor T3B can be coupled to the reference voltage terminal VSS, and the control terminal of the transistor T3B can be coupled to the transistor The first end of T3B. The node N1 can be disposed between the transistors T1B and T4B. The transistor T1B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T1B can be coupled to the reference voltage terminal Vref, and the second terminal of the transistor T1B can be coupled to the node N1. The transistor T4B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T4B can be coupled to the node N1, the second terminal of the transistor T4B can be coupled to the reference voltage terminal VSS, and the control terminal of the transistor T4B can be coupled to the control terminal of the transistor T3B. That is to say, the transistors T3B and T4B can form a current mirror structure for mirroring the reference current IB to generate the reference current Iref.

The mirror branch circuit 516 may include a node N2 , a transistor T2B and a voltage stabilizing circuit 560 . The node N2 can be disposed between the transistor T2B and the voltage stabilizing circuit 560 . The transistor T2B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T2B can be coupled to the reference voltage terminal Vref, the second terminal of the transistor T2B can be coupled to the node N2, and the control terminal of the transistor T2B can be coupled to the control terminal of the transistor T1B. The voltage stabilizing circuit 560 has a first terminal and a second terminal. The first terminal of the voltage stabilizing circuit 560 can be coupled to the node N2, and the second terminal of the voltage stabilizing circuit 560 can be coupled to the reference voltage terminal VSS. The voltage stabilizing circuit 560 may include a resistor R4B, a diode D3B, and a diode D4B. The resistor R4B has a first terminal and a second terminal. The first end of the resistor R4B can be coupled to the first end of the voltage stabilizing circuit 560 . The diode D3B has a first end and a second end. The first end of the diode D3B can be coupled to the second end of the resistor R4B. The diode D4B has a first end and a second end. Diode D4B's first One terminal can be coupled to the second terminal of the diode D3B, and the second terminal of the diode D4B can be coupled to the second terminal of the voltage stabilizing circuit 560 .

The operational amplifier 520 may have a first input terminal, a second input terminal and an output terminal. The first input terminal of the operational amplifier 520 can be coupled to the node N1, the second input terminal of the operational amplifier 520 can be coupled to the node N2, and the output terminal of the operational amplifier 520 can be coupled to the control terminal of the transistor T1B and the transistor T2B. the control terminal.

The mirror branch circuit 514 may include a node N3 and a transistor T6B. The node N3 can be disposed between the transistor T6B and the bias signal generating circuit 530 . The transistor T6B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T6B can be coupled to the reference voltage terminal Vref, the second terminal of the transistor T6B can be coupled to the node N3, and the control terminal of the transistor T6B can be coupled to the control terminal of the transistor T2B. In this way, the voltage difference between the control terminal and the first terminal of transistor T1B, the voltage difference between the control terminal and the first terminal of transistor T2B, and the voltage between the control terminal and the first terminal of transistor T6B The differences can be substantially equal, and the transistors T1B, T2B and T6B can form a current mirror structure for mirroring the reference current Iref to generate mirror currents Im2 and Im1 respectively.

In addition, the bias signal generating circuit 530 may include a voltage stabilizing circuit 532 , a transistor T5B, a resistor R1B and a capacitor C1B. The voltage stabilizing circuit 532 may have a first terminal and a second terminal. The first terminal of the voltage stabilizing circuit 532 can be coupled to the node N3, and the second terminal of the voltage stabilizing circuit 532 can be coupled to the reference voltage terminal VSS. In FIG. 5 , the voltage stabilizing circuit 532 and the voltage stabilizing circuit 560 may have similar structures. For example, the voltage stabilizing circuit 532 may include a resistor R2B, a diode D1B, and a diode D2B. The resistor R2B has a first terminal and a second terminal. The first end of the resistor R2B can be coupled to the first end of the voltage stabilizing circuit 532 . The diode D1B has a first end and a second end. The first end of the diode D1B can be coupled to the second end of the resistor R2B. The diode D2B has a first end and a second end. The first terminal of the diode D2B can be coupled to the second terminal of the diode D1B, and the second terminal of the diode D2B can be coupled to the second terminal of the voltage stabilizing circuit 532 . The transistor T5B has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T5B can be coupled to the operating voltage terminal VDD2, and the control terminal of the transistor T5B can be coupled to the voltage terminal VDD2. Block the second terminal of R2B. The resistor R1B has a first terminal and a second terminal. The first terminal of the resistor R1B can be coupled to the second terminal of the transistor T5B, and the second terminal of the resistor R1B can be coupled to the bias terminal NB of the amplifier AMP and can be used to output the bias signal Sbias. The capacitor C1B has a first terminal and a second terminal. The first terminal of the capacitor C1B can be coupled to the control terminal of the transistor T5B, and the second terminal of the capacitor C1B can be coupled to the reference voltage terminal VSS. In some embodiments, when the mirror current Im1 flows through the voltage stabilizing circuit 532 , the resistor R2B will generate a voltage drop and turn on the diodes D1B and D2B. In this case, the voltage VN3 on the node N3 can be regarded as the sum of the voltage drop of the resistor R2B and the conduction voltages of the diodes D1B and D2B.

In some embodiments, in order to accurately mirror the reference current Iref to generate stable mirrored currents Im2 and Im1 respectively, not only the voltage difference between the control terminal and the first terminal of the transistor T1B, the transistor The voltage difference between the control terminal and the first terminal of T2B and the voltage difference between the control terminal and the first terminal of the transistor T6B are designed to be substantially equal, and the voltage difference between the second terminal and the first terminal of the transistor T1B The voltage difference, the voltage difference between the second terminal and the first terminal of the transistor T2B, and the voltage difference between the second terminal and the first terminal of the transistor T6B also need to be designed to be substantially equal. Furthermore, when the mirror current Im2 flows through the voltage stabilizing circuit 560 , the resistor R4B will generate a voltage drop, which can turn on the diodes D3B and D4B. In this case, the voltage VN2 on the node N2 can be regarded as the sum of the voltage drop of the resistor R4B and the conduction voltages of the diodes D3B and D4B. The transistor T1B and the operational amplifier 520 can form a negative feedback loop, so the first input terminal and the second input terminal of the operational amplifier 520 can have a virtual short circuit characteristic. When FIG. 5 takes the first voltage V1 as the voltage VN1 on the node N1 (that is, the voltage on the reference branch circuit 512), and the second voltage V2 is the voltage VN2 (that is, the voltage on the mirror branch circuit 516) as an example , the control voltage Vctrl generated by the operational amplifier 520 can be used to make the first voltage V1 follow the change of the second voltage V2, so that when the bias circuit 500 operates in the operation mode, the first voltage V1 and the second voltage V2 can be substantially equal. In some embodiments, the transistor T6B and the transistor T2B may have the same electrical characteristics, and the voltage stabilizing circuit 532 may also have the same electrical characteristics as the voltage stabilizing circuit 560 , so the voltages VN3 and VN2 may be substantially equal. In this way, the voltage difference between the second terminal and the first terminal of the transistor T1B, the voltage difference between the second terminal and the first terminal of the transistor T2B and the transistor The voltage difference between the second terminal and the first terminal of T6B can be substantially equal, so that the reference current Iref can be accurately mirrored to generate stable mirror currents Im2 and Im1 respectively, and then the bias signal can be generated. Accordingly, the circuit 530 can output a stable bias signal Sbias.

Since the bias signal generating circuit 530 is coupled to the mirroring branch circuit 514, and the second voltage V2 is related to the voltage on the mirroring branch circuit 516, the RF signal leaked from the input terminal RFIN through the bias signal generating circuit 530 Srf1 will relatively not affect the stability of the second voltage V2.

In some embodiments, the bias circuit 500 may further include a capacitor C3B and a capacitor C4B. The capacitor C3B has a first terminal and a second terminal. A first terminal of the capacitor C3B can be coupled to the node N3, and a second terminal of the capacitor C3B can be coupled to the reference voltage terminal VSS. In Fig. 5, not only the resistor R2B and the capacitor C1B in the bias signal generating circuit 530 can be used as a low-pass filter, but the resistor R2B and the capacitor C3B can also be used as another low-pass filter to filter out unwanted The radio frequency signal Srf1 reduces the interference of the radio frequency signal Srf1 to the voltage VN3, thereby maintaining the stability of the voltage VN3. The capacitor C4B has a first terminal and a second terminal. A first terminal of the capacitor C4B can be coupled to the node N2, and a second terminal of the capacitor C4B can be coupled to the reference voltage terminal VSS. The resistor R4B and the capacitor C4B in the voltage stabilizing circuit 560 can be used as a low-pass filter to filter out the undesired radio frequency signal Srf1 and reduce the interference of the radio frequency signal Srf1 to the voltage VN2, thereby maintaining the stability of the second voltage V2. Furthermore, the bias circuit 500 may further include a start-up circuit 540 , a voltage selection circuit 550 , a resistor R3B, and a capacitor C2B. The circuit connections and operating principles thereof are similar to those described above, so details are not repeated here. In some embodiments, the start-up circuit 540 and/or the voltage selection circuit 550 can be selectively configured according to different applications or according to system requirements. When the bias circuit 500 includes the start-up circuit 540 and/or the voltage selection circuit 550 , the second voltage V2 can be the adjusted voltage on the mirrored sub-circuit 516 or the voltage on the mirrored sub-circuit 516 .

In some embodiments, the transistors T3A, T4A, T3B, and T4B can be N-type metal oxide semiconductor transistors (NMOS). Accordingly, the first ends of the transistors T3A, T4A, T3B, and T4B can be drains, and the first terminals of the transistors T3A, T4A, T3B, and T4B can be drains. The two terminals can be sources, and the control terminal can be gates. Transistors T1A, T2A, T1B and T2B can be P-type metal oxide semiconductor transistors (PMOS), accordingly, the first ends of transistors T1A, T2A, T1B and T2B can be source electrodes, The second end can be a drain, and the control end can be a gate. The transistors T5A and T5B can be bipolar junction transistors (BJT), and accordingly, the first ends of the transistors T5A and T5B can be collectors, the second ends can be emitters, and the control ends can be bases. pole.

In some embodiments, because the strength of the radio frequency signal is weak, the radio frequency signal may not be amplified to a sufficient strength by a single amplifier. In this case, multi-stage amplifiers are used to amplify the radio frequency signal. However, the RF signal may leak to the bias circuit of the last stage amplifier, and when the bias circuits of multi-stage amplifiers are all coupled to the same reference voltage terminal, the RF signal may further leak to the other stages of amplifiers, causing the linearity of each stage of amplifiers to be affected.

FIG. 6 is a schematic diagram of a signal amplifying device 10 according to an embodiment of the present invention. The signal amplifying device 10 may include bias circuits 1001 and 1002 , an input terminal RFIN, an output terminal RFOUT, and amplifiers AMP1 and AMP2 . In some embodiments, the bias circuits 1001 and 1002 may have the same structure as the bias circuits 100 , 200 , 300 , 400 or 500 and operate according to the same principle. The input terminal RFIN can receive the radio frequency signal Srf1, and the output terminal RFOUT can output the amplified radio frequency signal Srf2. The amplifier AMP1 can receive the bias signal Sbias1 generated by the bias circuit 1001 , and the amplifier AMP2 can receive the bias signal Sbias2 generated by the bias circuit 1002 . In FIG. 6 , the amplifiers AMP1 and AMP2 can be coupled between the input terminal RFIN and the output terminal RFOUT of the signal amplifying device 10 . Further, the amplifier AMP2 can be coupled between the input terminal RFIN of the signal amplifying device 10 and the amplifier AMP1 . That is to say, the signal amplifying device 10 may include two stages of amplifiers: the amplifiers AMP1 and AMP2, and the radio frequency signal Srf1 may be sequentially amplified by the two amplifiers.

In addition, the bias circuit 1001 can be coupled between the reference voltage terminal Vref1 and the bias terminal NB1 of the amplifier AMP1 for receiving the reference voltage VR1. The bias circuit 1002 can be coupled between the reference voltage terminal Vref2 and the bias terminal NB2 of the amplifier AMP2 for receiving the reference voltage VR2. The signal amplifying device 10 may also include a low dropout regulator (Low Dropout Regulator, LDO) 671 and a low dropout regulator 672. The low-dropout voltage regulator 671 can be used to generate the reference voltage VR1 to the reference voltage terminal Vref1 according to the supply voltage on the supply voltage terminal VSP, and the low-dropout voltage regulator 672 can be used to generate the reference voltage VR2 to the reference voltage terminal according to the supply voltage on the supply voltage terminal VSP. Reference voltage terminal Vref2. In some embodiments, in order to maintain the linearity of the amplifiers AMP1 and AMP2, the unwanted radio frequency signal Srf1 can be filtered out by setting the capacitor C0. Furthermore, the supply voltage terminal VSP can be further coupled to the external pin P1 of the signal amplifying device 10 , and the capacitor C0 can be coupled to the external pin P1 , that is, the capacitor C0 is disposed outside the signal amplifying device 10 . In this way, the capacitor C0 with larger capacitance can be selected to effectively filter the unwanted radio frequency signal Srf1 without increasing the area of the signal amplifying device 10 , making the design of the signal amplifying device 10 more flexible.

In some embodiments, the signal amplifying device 10 may further include an amplifier AMP3 , a bias circuit 1003 and a low dropout regulator 673 . That is to say, the signal amplifying device 10 can include more amplifiers, such as three stages of amplifiers: amplifiers AMP1 to AMP3, and can amplify the radio frequency signal Srf1 successively. The amplifier AMP3 can be disposed between the input terminal RFIN of the signal amplifying device 10 and the amplifier AMP2 , and can receive the bias signal Sbias3 generated by the bias circuit 1003 . The bias circuit 1003 can be coupled between the reference voltage terminal Vref3 and the bias terminal NB3 of the amplifier AMP3 for receiving the reference voltage VR3. The low dropout regulator 673 is used to generate the reference voltage VR3 to the reference voltage terminal Vref3 according to the supply voltage on the supply voltage terminal VSP. However, the present invention does not limit the number of LDOs included in the signal amplifying device 10. In some embodiments, the signal amplifying device 10 may include fewer LDOs according to system requirements, and The low dropout regulator 672 or 673 is omitted.

FIG. 7 is a schematic diagram of a signal amplifying device 20 according to another embodiment of the present invention. The signal amplifying device 20 may include bias circuits 2001 , 2002 and 2003 , an input terminal RFIN, an output terminal RFOUT, amplifiers AMP1 to AMP3 , and low dropout regulators 771 and 772 . The signal amplifying devices 20 and 10 have similar structures and operating principles, and the main difference lies in the bias circuit 2003 and the low-dropout regulators 771 and 772 in the signal amplifying device 20 .

In Figure 7, the bias circuit 2001 can be coupled to the reference voltage terminal Vref1 and the amplifier AMP1 Between the bias terminals NB1 for receiving the reference voltage VR1. The bias circuit 2002 can be coupled between the reference voltage terminal Vref2 and the bias terminal NB2 of the amplifier AMP2 for receiving the reference voltage VR2. The bias circuit 2003 can be coupled between the reference voltage terminal Vref2 and the bias terminal NB3 of the amplifier AMP3 for receiving the reference voltage VR2. The low-dropout voltage regulator 771 can be used to generate the reference voltage VR1 to the reference voltage terminal Vref1 according to the supply voltage on the supply voltage terminal VSP, and the low-dropout voltage regulator 772 can be used to generate the reference voltage VR2 to the reference voltage terminal according to the supply voltage on the supply voltage terminal VSP. Reference voltage terminal Vref2. That is to say, the bias circuit 2003 and the bias circuit 2002 can use the same low-dropout voltage regulator.

In some embodiments, in order to maintain the linearity of the amplifiers AMP1 to AMP3, the unwanted radio frequency signal Srf1 can be filtered out by setting the capacitor C0. Furthermore, the supply voltage terminal VSP can be further coupled to the external pin P1 of the signal amplifying device 20 , and the capacitor C0 can be coupled to the external pin P1 , that is, the capacitor C0 is disposed outside the signal amplifying device 20 . In this way, the capacitor C0 with larger capacitance can be selected to effectively filter the unwanted radio frequency signal Srf1 without increasing the area of the signal amplifying device 20 , making the design of the signal amplifying device 20 more flexible.

In summary, the bias circuit and signal amplifying device provided by the embodiments of the present invention can be designed so that the transistors of different branch circuits in the internal current mirror circuit can meet the required operating voltage conditions, thereby providing stable The mirror current enables the bias signal generating circuit to generate a stable bias signal, thereby maintaining the performance of the amplifier. In addition, when the signal amplifying device includes multi-stage amplifiers, the influence of undesired radio frequency signals on the amplifiers of each stage can also be reduced by setting external capacitors.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: bias circuit

110: current mirror circuit

112: Reference branch circuit

114: mirror branch circuit

120: Operational amplifier

130: Bias signal generating circuit

132: Regulator circuit

AMP: Amplifier

C1A, C2A: capacitance

CSA: current source

D1A, D2A: Diode

IB: Reference current

Im1: mirror current

Iref: reference current

N1, N2: nodes

NB: Bias terminal

R1A to R3A: Resistors

RFIN: input terminal

RFOUT: output terminal

Sbias: bias signal

Srf1, Srf2: RF signal

T1A to T5A: Transistors

V1: first voltage

V2: second voltage

Vctrl: control voltage

VDD1, VDD2: operating voltage terminal

VN1, VN2: Voltage

Vref: reference voltage terminal

VSS: reference voltage terminal

Claims (21)

A bias circuit, comprising: a current mirror circuit, including a reference branch circuit for generating a reference current according to a reference current mirror, and at least one mirror branch circuit for generating at least one mirror image according to the reference current Current; an operational amplifier, coupled to the reference branch circuit and the at least one mirror branch circuit, for receiving a first voltage and a second voltage, and for generating a control voltage according to the second voltage, the control voltage is used to adjust the first voltage; and a bias signal generating circuit, coupled to the at least one mirror branch circuit, for generating a bias signal according to the at least one mirror current; wherein the first voltage is the reference branch A voltage on the circuit, the second voltage being a voltage on the at least one mirrored sub-circuit or the regulated voltage on the at least one mirrored sub-circuit. The bias circuit as claimed in claim 1, wherein: the at least one mirroring branch circuit includes a first mirroring branch circuit, and the first mirroring branch circuit is used to generate a first mirroring current in the at least one mirroring current A mirror current; the bias signal generating circuit is used to generate the bias signal according to the first mirror current; the reference branch circuit includes: a first transistor having a first terminal coupled to a first reference voltage Terminal, a second terminal coupled to a first node, and a control terminal; and the first mirror branch circuit includes: a second transistor, with a first terminal coupled to the first reference voltage terminal, a first Two terminals are coupled to a second node, and a control terminal is coupled to the control terminal of the first transistor. The bias circuit as described in claim 2, wherein: the bias signal generating circuit includes a first voltage stabilizing circuit, has a first terminal coupled to the second node, and a second terminal coupled to a The reference voltage terminal, the first voltage stabilizing circuit also includes: a first resistor having a first end coupled to the first end of the first voltage stabilizing circuit, and a second end; a first diode , having a first end coupled to the second end of the first resistor, and a second end; and a second diode, having a first end coupled to the second end of the first diode Two terminals, and a second terminal coupled to the second terminal of the first voltage stabilizing circuit. The bias circuit according to claim 3, wherein the second voltage is the sum of the voltage drop of the first resistor and the conduction voltages of the first diode and the second diode. The bias circuit as described in claim 2, wherein the operational amplifier has a first input terminal coupled to the first node, a second input terminal coupled to the second node, and an output terminal coupled to the first the control end of the transistor and the control end of the second transistor. The bias circuit as described in claim 5, wherein a voltage difference between the control terminal and the first terminal of the first transistor is the same as that between the control terminal and the first terminal of the second transistor a voltage difference between the second terminal and the first terminal of the first transistor is substantially equal to a voltage difference between the second terminal and the first terminal of the second transistor The voltage differences are substantially equal. The bias circuit as described in claim 5, wherein when the bias circuit operates in an operation mode In the formula, the first voltage is substantially equal to the second voltage. The bias circuit as described in claim 5, further comprising a first start-up circuit for generating a first start-up current to make the second voltage reach a predetermined value when the bias circuit is operated in a start-up mode set value, and the first voltage changes from an initial value following the preset value of the second voltage. The bias circuit according to claim 5 further includes a voltage selection circuit for setting the second voltage according to a voltage on the second node. The bias circuit as described in claim 9, wherein when the voltage on the second node is greater than an upper limit voltage, the voltage selection circuit sets the second voltage to a first predetermined value less than or equal to the upper limit voltage Set the voltage. The bias circuit as described in Claim 9, wherein when the voltage on the second node is less than a lower limit voltage, the voltage selection circuit sets the second voltage to a second predetermined value greater than or equal to the lower limit voltage Set the voltage. The bias circuit as described in claim 9, wherein when the voltage on the second node is between an upper limit voltage and a lower limit voltage, the voltage selection circuit sets the second voltage to be equal to the second The voltages on the nodes are equal. The bias voltage circuit as described in claim 1, wherein the at least one mirror branch circuit includes a first terminal, a second terminal and a control terminal, and the bias signal generating circuit is coupled to the at least one mirror branch the second end of the circuit. A bias circuit, comprising: a current mirror circuit, comprising a reference branch circuit for generating a reference current according to a reference current, and at least one mirror branch circuit for generating at least one mirror current according to the reference current, The at least one mirroring branch circuit includes a first mirroring branch circuit and a second mirroring branch circuit, the first mirroring branch circuit is used to generate a first mirroring current in the at least one mirroring current, and The second mirror branch circuit is used to generate a second mirror current in the at least one mirror current; an operational amplifier, coupled to the reference branch circuit and the at least one mirror branch circuit, is used to receive a first voltage and a second voltage, and is used to generate a control voltage according to the second voltage, and the control voltage is used to adjust the first voltage; and a bias signal generating circuit, coupled to the first mirror branch circuit, the The bias signal generating circuit is used to generate the bias signal according to the first mirror current; wherein the first voltage is a voltage on the reference branch circuit, and the second voltage is a voltage on the second mirror branch circuit voltage or the regulated voltage on the second mirrored branch circuit. The bias circuit as described in claim 14, wherein: the reference branch circuit includes a third transistor, has a first terminal coupled to a second reference voltage terminal, and a second terminal coupled to a third node, and a control terminal; the second mirror branch circuit includes: a fourth transistor having a first terminal coupled to the second reference voltage terminal, a second terminal coupled to a fourth node, and a control terminal coupled connected to the control terminal of the third transistor; and a second voltage stabilizing circuit having a first terminal coupled to the fourth node and a second terminal coupled to a reference voltage terminal. The bias circuit as described in claim 15, wherein: the first mirror branch circuit includes a fifth transistor, with a first end coupled to the second reference voltage end, and a second end coupled to a The fifth node, and a control terminal coupled to the control terminal of the fourth transistor; the bias signal generating circuit includes a third voltage stabilizing circuit, having a first terminal coupled to the fifth node, and a second The terminal is coupled to the reference voltage terminal. The bias circuit as claimed in item 16, wherein the electrical characteristics of the fifth transistor are the same as the electrical characteristics of the fourth transistor, and the electrical characteristics of the third voltage stabilizing circuit are the same as those of the second voltage stabilizing circuit The characteristics are the same. The bias circuit as described in claim 15, wherein the operational amplifier has a first input terminal coupled to the third node, a second input terminal coupled to the fourth node, and an output terminal coupled to the third node the control end of the transistor and the control end of the fourth transistor. A signal amplifying device, comprising: a first bias circuit, including: a first current mirror circuit for receiving a first reference voltage, and comprising a first reference branch circuit and at least one first mirror branch circuit, the first reference branch circuit is used to generate a first reference current according to a first reference current mirror, and the at least one first mirror branch circuit is used to generate at least a first mirror image according to the first reference current Current; a first operational amplifier, coupled to the first reference sub-circuit and the at least one first mirror sub-circuit, for receiving a first voltage and a second voltage, and for receiving a first voltage and a second voltage according to the second a voltage to generate a first control voltage, wherein the first control voltage is used to adjust the first voltage; and a first bias signal generating circuit, coupled to the at least one first mirror branch circuit, for according to the at least one A first mirror current generates a first bias signal; wherein the first voltage is a voltage on the first reference sub-circuit, and the second voltage is a voltage on the at least one first mirror sub-circuit or The adjusted voltage on the at least one first mirror branch circuit; an input terminal for receiving a radio frequency signal; an output terminal for outputting the amplified radio frequency signal; and a first amplifier coupled to Between the input end of the signal amplifying device and the output end of the signal amplifying device is used for receiving the first bias signal and amplifying the radio frequency signal. The signal amplifying device as described in claim 19, further includes: a second bias circuit, including: a second current mirror circuit, used to receive the first reference voltage, and includes a second reference branch circuit and At least one second mirror branch circuit, the second reference branch circuit is used to generate a second reference current according to a second reference current, and the at least one second mirror branch circuit is used to generate at least A second mirror current; a second operational amplifier, coupled to the second reference sub-circuit and the at least one second mirror sub-circuit, for receiving a third voltage and a fourth voltage, and for receiving a third voltage and a fourth voltage according to the first four voltages to generate a second control voltage, wherein the second control voltage is used to adjust the third voltage; and a second bias signal generating circuit, coupled to the at least one second mirror branch circuit, for according to the At least one second mirror current generates a second bias signal; Wherein the third voltage is a voltage on the second reference sub-circuit, the fourth voltage is a voltage on the at least one second mirroring sub-circuit or the adjusted voltage on the at least one second mirroring sub-circuit the voltage; and a second amplifier coupled between the input terminal of the signal amplifying device and the first amplifier for receiving the second bias voltage signal and amplifying the radio frequency signal. The signal amplifying device as described in claim 19, further comprising: a third bias circuit comprising: a third current mirror circuit for receiving a second reference voltage, and comprising a third reference branch circuit and at least A third mirroring branch circuit, the third reference branch circuit is used to generate a third reference current according to a third reference current, and the at least one third mirroring branch circuit is used to generate at least one The third mirror current; a third operational amplifier, coupled to the third reference branch circuit and the at least one third mirror branch circuit, used to receive a fifth voltage and a sixth voltage, and used for receiving a fifth voltage and a sixth voltage according to the sixth a voltage to generate a third control voltage, wherein the third control voltage is used to adjust the fifth voltage; and a third bias signal generating circuit, coupled to the at least one third mirror branch circuit, for according to the at least one A third mirror current generates a third bias signal; wherein the fifth voltage is a voltage on the third reference branch circuit, and the sixth voltage is a voltage on the at least one third mirror branch circuit or the adjusted voltage on the at least one third mirror branch circuit; a third amplifier coupled between the input terminal of the signal amplifying device and the first amplifier for receiving the third bias signal and amplifying the radio frequency signal; a first low-dropout regulator for generating the first reference voltage according to a supply voltage; and A second low-drop voltage regulator is used to generate the second reference voltage according to the supply voltage.

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