TWI783869B - Memory and reading method thereof - Google Patents

Abstract

A memory includes a selected memory cell block and a first sense amplifying device. Both of the selected memory cell block and a first sense amplifying device are coupled to a global bit line. The first sense amplifying device is configured to: in a leakage current detection mode, detect a leakage current on a first global bit line of the first selected memory cell block to generate leakage current information; and in a data reading mode, provide a reference signal, and compare a readout signal on the first global bit line with the reference signal to generate a readout data, where the leakage current detection mode is happened before the data reading mode.

Description

Memory and how to read it

The present invention relates to a memory and a method for reading the memory, and in particular relates to a memory and a method for reading the memory that can be compensated for leakage current.

In the flash memory, the erasing action of memory cells may be suspended due to various reasons, and then the erasing action may not be complete. Such a phenomenon may cause leakage current in unselected memory cells when the memory is being read. As shown in FIG. 1 , a schematic diagram of a conventional memory reading operation is shown. Wherein, the memory cell MC2 is a memory cell that has not completed the erasing operation. When the memory 100 performs a read operation on the common bit line GBL, when the memory cell MC1 is the selected memory cell and the memory cell MC2 is the unselected memory cell, the memory cells MC1 and MC2 will provide the read current IC and the leakage current respectively. IL. In this way, the sensing operation of reading data based on the total current value on the common bit line GBL may cause errors due to the interference of the leakage current IL, resulting in incorrect reading data.

The memory of the present invention includes a selected memory cell block and a first sense amplification device. Both the selected memory cell block and the first sense amplifier are coupled to the first common bit line. The first sense amplifier is used for: in the leakage current detection mode, detecting the leakage current of the selected memory cell block on the first common bit line to generate leakage current information; in the data reading mode, according to the leakage current The information is used to provide a reference signal, and the read data is generated by comparing the read signal on the first common bit line with the reference signal, wherein the leakage current detection mode occurs before the read data mode.

The memory reading method of the present invention includes: providing a first sense amplifier to couple to the first common bit line; in the leakage current detection mode, enabling the first sense amplifier to detect the selected memory cell area block leakage current on the first common bit line to generate leakage current information; in the read data mode, make the first sense amplifier provide a reference signal according to the leakage current information, by comparing the read data on the first common bit line The fetch signal and the reference signal are used to generate read data, wherein the leakage current detection mode occurs before the read data mode.

Based on the above, before the memory of the present invention performs the read operation, the leakage current detection operation can be performed on the shared bit line to obtain a leakage current information. Moreover, in the data reading operation, compensation is performed according to the leakage current information, so as to obtain accurate read data.

200, 300, 601, 602, 701, 702: memory

210, 310, 711: select the memory cell block

220, 320, 721: sensing amplifier

311~31n: Division

321: proportional controller

322, SA~SA': sense amplifier

611, 612: memory cell array

621, 622: proportional controller

CR: compare results

DOUT: read data

GBL: common bit line

IE~IE': input terminal

IL: leakage current

ILD: leakage current information

IR: current reference signal

ISET: set signal

ITH: critical signal

MC1, MC2, MC1~MCn+i-1: memory cells

RS: read signal

S410~S450, S511~S532, S810~S830: steps

SMC: memory cell

VR: voltage reference signal

WL[0]~WL[n+i-1]: character line

FIG. 1 is a schematic diagram of a conventional memory reading operation.

FIG. 2 is a schematic diagram of a memory according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of an implementation of a memory according to another embodiment of the present invention.

FIG. 4 is a flow chart showing the operation of the memory device to obtain leakage current information according to the embodiment of the present invention.

FIG. 5 is a timing diagram of the reading operation of the memory according to the embodiment of the present invention.

6A and 6B are schematic diagrams of multiple implementations of the leakage current detection mode of the memory according to the embodiment of the present invention.

7A and 7B are schematic diagrams of multiple implementations of data reading modes of the memory according to the embodiment of the present invention.

FIG. 8 is a flow chart of the reading operation of the memory according to the embodiment of the present invention.

Please refer to FIG. 2 , which is a schematic diagram of a memory according to an embodiment of the present invention. The memory 200 includes a selected memory cell block 210 and a sense amplifier 220 . There are a plurality of memory cells in the selected memory cell block 210, which are commonly coupled to the common bit line GBL. The sense amplifier device 220 is coupled to the selected memory cell block 210 through the common bit line GBL. In this embodiment, when one or more memory cells in the memory cell block 210 are selected to perform a read operation, the sense amplifier 220 can detect the selected memory cells in the leakage current detection mode. Block 210 drains current on the common bit line GBL to generate a drain current information. Next, the sense amplifier 220 can provide a reference signal according to the leakage current information in the read data mode, and generate a read data DOUT by comparing the read signal RS on the common bit line GBL with the reference signal.

In this embodiment, the leakage current detection mode may occur before the data reading mode. Moreover, in the leakage current detection mode, the multiple word line signals received by the multiple memory cells corresponding to the common bit line GBL are all disabled. That is to say, in the leakage current detection mode, all the memory cells in the selected memory cell block 210 are in a non-access state. At this time, the sense amplifier device 220 can receive the leakage current IL generated on the common bit line GBL, and thereby generate leakage current information.

Further, the sense amplifier device 220 can receive a set signal ISET, and adjust the set signal ISET according to a set ratio to generate a leakage current replica signal. The sense amplifier 220 compares the leakage current replica signal with the leakage current IL on the common bit line GBL to generate a comparison result. If the initial value of the comparison result is a first logic level, the sense amplifying device 220 can adjust the setting ratio when the comparison result remains at the first logic level, and perform the next leakage current replication signal Comparison operation with leakage current IL. Once the comparison result changes from the first logic level to the second logic level, the sense amplifier device 220 can record the current leakage current replica signal to generate leakage current information.

Incidentally, in other embodiments, the sense amplifier 220 can also record the current setting ratio to generate leakage current information.

In this embodiment, the setting signal ISET can be preset as a signal with a relatively high value. Under this condition, the sense amplifier 220 can gradually lower the setting ratio to perform the comparison action between the leakage current replica signal and the leakage current IL. . In the initial stage, the leakage current replica signal may be greater than the leakage current IL, and make the comparison result be the first logic level. And as the setting ratio is lowered, the leakage current replica signal can be adjusted to be less than Or equal to the leakage current IL, the sense amplifier device 220 can generate a comparison result of the second logic level. The leakage current replica signal at this time is in a state closest to the leakage current IL.

Alternatively, the setting signal ISET can also be preset as a signal with a relatively low value. Under this condition, the sense amplifier 220 can gradually increase the setting ratio to perform a comparison action between the leakage current replica signal and the leakage current IL. In the initial stage, the leakage current replica signal may be smaller than the leakage current IL, and make the comparison result be the first logic level. As the setting ratio is increased, the leakage current replica signal can be adjusted to be greater than or equal to the leakage current IL, and the sense amplifier 220 can generate a comparison result of the second logic level. The leakage current replica signal at this time can also be in a state closest to the leakage current IL.

In addition, the above-mentioned first logic level can be a logic 1 or a logic 0, and the above-mentioned second logic level can be a logic 0 or 1 complementary to the first logic level, and there is no fixed limitation.

After the leakage current detection mode is completed, the memory 100 can enter the data reading mode. In the data reading mode, a selected word line in the selected memory cell block 210 can be enabled, while at least one unselected word line is disabled. At this time, the selected memory cell in the selected memory cell block 210 can provide a read signal RS on the common bit line GBL.

On the other hand, in the data reading mode, the sense amplifier device 220 can generate a reference signal according to the leakage current information. Moreover, the sense amplifier device 220 can compare the read signal RS with the reference signal, and generate the read data DOUT. It can be known from the above description that the reference signal generated by the sense amplifier 220 in the embodiment of the present invention is generated after compensation according to leakage current information. Therefore, sensing The readout data DOUT generated by the amplifying device 220 can avoid the interference of the leakage current generated by the memory cells in the selected memory cell block 210 . Effectively improve the accuracy of reading data DOUT.

Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of an implementation of a memory according to another embodiment of the present invention. The memory 300 includes a selected memory cell block 310 and a sense amplifier 320 . The selected memory cell block 310 can be divided into a plurality of sectors 311˜31n. The plurality of subsections 311 - 31 n of the selected memory cell block 310 share the same common bit line GBL. The selected memory cell block 310 has a plurality of memory cells MC1˜MCn+i−1. The memory cells MC1˜MCn+i−1 are respectively coupled to the word lines WL[0]˜WL[n+i−1]. The source terminals of the memory cells MC1˜MCn+i−1 are commonly coupled to the ground voltage GND.

The sense amplifier device 320 includes a proportional controller 321 and a sense amplifier 322 . The sense amplifier 322 has a first input terminal coupled to the common bit line GBL, and the sense amplifier 322 has a second input terminal coupled to the proportional controller 321 . The ratio controller 321 is used for receiving the setting signal ISET, and adjusting the setting signal ISET according to the setting ratio to generate a leakage current replica signal. The ratio controller 321 can also adjust the above-mentioned setting ratio according to the comparison result CR generated by the sense amplifier 322 .

In the leakage current detection mode, the word lines WL[0]˜WL[n+i-1] are all disabled. The sense amplifier device 320 compares the leakage current replica signal provided by the proportional controller 321 with the leakage current IL on the common word line GBL. The proportional controller 321 gradually adjusts the value of the set ratio according to the comparison result CR generated by the sense amplifier 322 to obtain leakage current information.

The implementation details of the way of obtaining leakage current information have been described in detail in the aforementioned embodiment of FIG. 1 , and will not be repeated here.

On the other hand, in the read data mode, one of the selected word lines in word lines WL[0]~WL[n+i-1] is enabled (other unselected word lines are disabled ). The selected memory cell can provide the read signal RS to the common word line GBL according to the stored data and the leakage current IL. At the same time, the sense amplifier device 320 can generate a reference signal according to the leakage current information obtained in the leakage current detection mode, and make the sense amplifier 322 compare the read signal RS with the reference signal to generate read data. DOUT.

Please note here that the reference signal is generated according to the leakage current information. Therefore, when the sense amplifier 322 compares the read signal RS with the reference signal, the part of the leakage current IL in the read signal RS can be eliminated. . In this way, the sense amplifier 322 can generate correct readout data DOUT.

Please refer to FIG. 4 below. FIG. 4 shows a flow chart of the operation of the memory device to obtain leakage current information according to the embodiment of the present invention. Wherein, in the leakage current detection mode, in step S410 , the value of the set signal can be set through the trim mechanism of the test process during the wafer test. Wherein, the setting signal can be set as a signal with a relatively large value. In an embodiment of the present invention, the setting signal may be a current signal. The trimming mechanism of the test process can be performed by blowing (or not blowing) the electronic fuse, or using the trimming technology of the test process well known to those skilled in the art, and there is no special limitation.

In step S420, an adjustment operation of the setting ratio is performed. In this implementation For example, based on the setting signal can be set as a signal having a relatively large value, the setting ratio can be a value equal to 1. Through setting the signal and the setting value, the sense amplifier device of this embodiment can generate a leakage current replica signal and compare it with the leakage current on the common bit line, and generate a comparison result in step S430.

In step S440, it is judged whether the comparison result is equal to the initial value (for example, logic 0)? If the judging result is yes, re-execute step S420 to further lower the set ratio. If the judgment result is negative, the set ratio can be recorded to obtain leakage current information (step S450).

Incidentally, step S410 in this embodiment can also adjust a relatively small setting signal through the adjustment mechanism of the test process. In this way, the setting ratio can be adjusted to a value less than 1 in step S420. And after the determination result of step S440 is yes, step S420 may further increase the setting ratio.

Please refer to FIG. 5 below. FIG. 5 shows a timing diagram of the reading operation of the memory according to the embodiment of the present invention. Firstly, corresponding to the common bit line GBL of the first selected memory cell block, the steps of reading data sensing S511 and data buffering S512 are executed in sequence. The corresponding word line signal WL can be enabled (pulled up to a high voltage), and the corresponding common bit line GBL generates a voltage corresponding to the readout data. Then, corresponding to the common bit line GBL' of the second selected memory cell block, steps such as leakage current detection S521, data read sensing S522, and data buffering S523 are executed in sequence. During the leakage current detection step S521, the corresponding word line signal WL is disabled, and during the read data sensing step S522, the voltage on the word line signal WL is pulled high and enabled. Correspondingly, the common bit line GBL has no action but a low voltage, and the common bit line GBL’ corresponds to the drain The step of current detection S521 and the step of reading data and sensing S522 generate voltage changes.

It is worth mentioning that while the steps of leakage current detection S521, data readout sensing S522, and data buffering S523 are sequentially executed, the data read from the first selected memory cell block can be output through data sequence S513 step and be sent out. The step of data sequence output S513 and the steps of leakage current detection S521 , reading data sensing S522 and data buffering S523 can be executed synchronously. Wherein, the total time required for the step of data sequence output S513 is just enough to execute all the actions of steps such as leakage current detection S521 , data readout sensing S522 and data buffering S523 . That is to say, the leakage current detection step S521 does not require extra time to be executed, effectively maintaining the data read rate of the memory.

Then, corresponding to the common bit line GBL" of the third selected memory cell block, steps such as leakage current detection S531 and data read sensing S532 are executed sequentially. Moreover, data sequence output S524 is executed synchronously to send out The reading data obtained from the second selected memory cell block. The reading operation of the third selected memory cell block is similar to the reading operation of the third selected memory cell block, and will not be repeated here.

In this embodiment, it can be seen that in the embodiment of the present invention, through the operation of the leakage current detection mode, the leakage current phenomenon can be effectively compensated without increasing the reading time of the memory, so as to ensure that the read the correctness of the data.

Please refer to FIG. 6A and FIG. 6B . FIG. 6A and FIG. 6B are schematic diagrams of multiple implementations of the leakage current detection mode of the memory according to the embodiment of the present invention. In FIG. 6A , the memory 601 includes a memory cell array 611 . There are a plurality of memory cell blocks in the memory cell array 611, and a plurality of sense amplifiers are set corresponding to the plurality of memory cell blocks SA˜SA’, the sense amplifiers SA˜SA’ are respectively coupled to the common bit lines GBL˜GBL’. In this embodiment, the leakage current replica signal generated by multiplying the set ratio by the set signal ISET through the proportional controller 621 is used. The leakage current replica signal is a current signal, and through the mirroring action of the current mirror 622, a plurality of mirrored leakage current replica signals are respectively generated to be transmitted to a plurality of sense amplifiers SA˜SA’. In this way, through the comparison results of the plurality of sense amplifiers SA~SA' and the stepwise adjustment of the setting ratio with the proportional controller 621, the multiple memory cell areas corresponding to the common bit lines GBL~GBL' can be calculated one by one. Block leakage current information, quickly complete the leakage current detection action.

In FIG. 6B , memory 602 includes memory cell array 612 . There are a plurality of memory cell blocks in the memory cell array 612, and a plurality of sense amplifiers SA~SA' are set corresponding to the plurality of memory cell blocks, and the sense amplifiers SA~SA' are respectively coupled to common bit lines GBL~GBL' . In this embodiment, the leakage current replica signal generated by multiplying the set ratio by the set signal ISET through the proportional controller 622 is used. The leakage current replica signal can be a voltage signal, which is transmitted to a plurality of sense amplifiers SA˜SA’ through transmission wires. In this way, through the comparison results of the plurality of sense amplifiers SA~SA' and the stepwise adjustment of the setting ratio with the proportional controller 621, the multiple memory cell areas corresponding to the common bit lines GBL~GBL' can be calculated one by one. Block leakage current information, quickly complete the leakage current detection action.

Please refer to FIG. 7A and FIG. 7B . FIG. 7A and FIG. 7B are schematic diagrams of multiple implementations of data reading modes of the memory according to the embodiment of the present invention. In FIG. 7A , the memory 701 includes a selected memory cell block 711 and a sense amplifier 721 . In the data reading mode, the memory cell SMC is the selected memory cell, and the common bit line A read signal RS is transmitted on the GBL. One end of the sense amplifier SA receives the readout signal RS, and the other end receives a reference signal combined with the threshold signal ITH and the leakage current information ILD. In this embodiment, the readout signal RS, the threshold signal ITH and the leakage current information ILD are all current signals. Wherein, the leakage current information ILD can be used to offset the error of the readout signal RS caused by the leakage current. Effectively improve the accuracy of reading data DOUT.

In FIG. 7B, the memory 702 includes a memory cell array 712 and a plurality of sense amplifiers SA~SA'. The memory cell array 712 has a plurality of memory cell blocks, which are respectively coupled to a plurality of common bit lines GBL˜GBL’. In the data reading mode, the sense amplifiers SA~SA' receive a reference signal in addition to the read signals generated by the common bit lines GBL~GBL' respectively. In this embodiment, the reference signal may be a current reference signal IR or a voltage reference signal VR.

When the reference signal is the current reference signal IR, a current mirror circuit can be provided on the input terminals IE˜IE′ of the sense amplifiers SA˜SA’. The current mirror circuits of the input ends IE˜IE’ can have different mirror ratios respectively, and the multiple mirror ratios are respectively equivalent to multiple weight values, and respectively correspond to multiple leakage current information on the common bit lines GBL˜GBL’. Leakage current information can be generated in leakage current detection mode.

When the reference signal is the voltage reference signal VR, the input terminals IE~IE' of the sense amplifiers SA~SA' can be provided with devices that can adjust the input impedance, such as setting an adjustable load or adjusting the sense amplifiers SA~SA' The size of the transistor on the input terminal IE~IE'. In order to provide a plurality of weight values respectively corresponding to a plurality of leakage current information on the common bit lines GBL~GBL'. Leakage current information can also be generated in leakage current detection mode.

Please refer to FIG. 8 below. FIG. 8 shows a flow chart of the reading operation of the memory according to the embodiment of the present invention. Wherein, in step S810, a first sense amplifier device is provided to be coupled to the first common bit line. In step S820 , in the leakage current detection mode, the first sense amplifier is enabled to detect the leakage current of the selected memory cell block on the first common bit line to generate leakage current information. Next, in the read data mode in step S830, make the first sense amplifier device provide a reference signal according to the leakage current information, and generate read data by comparing the read signal on the first common bit line with the reference signal .

The implementation details of the above steps have been described in detail in the aforementioned multiple embodiments, and will not be repeated here.

To sum up, in the read operation, the memory of the present invention detects the leakage current information on the common bit line through the leakage current detection mode, and in the read data mode, according to the leakage current information to target The leakage current is compensated to effectively ensure the accuracy of the read data.

200: Memory

210: Select memory cell block

220: Sense amplification device

DOUT: read data

GBL: common bit line

IL: leakage current

ISET: set signal

RS: read signal

Claims (16)

A memory, comprising: a selected memory cell block, coupled to a first common bit line; and a first sense amplifier, coupled to the first common bit line, for: in a drain In the current detection mode, detect the leakage current of the selected memory cell block on the first common bit line to generate a leakage current information; in a data reading mode, provide a reference according to the leakage current information signal, by comparing the read signal on the first common bit line with the reference signal to generate a read data, wherein the leakage current detection mode occurs before the read data mode, wherein in the leakage current detection mode , all word lines corresponding to the selected memory cell block are disabled. The memory according to claim 1, wherein in the data reading mode, a selected word line of the word lines is enabled, and at least one unselected word line of the word lines is disabled can. The memory according to claim 1, wherein the first sense amplifier device comprises: a sense amplifier having a first input terminal coupled to the first common bit line; and a proportional controller coupled to the a second input terminal of the sense amplifier, the proportional controller receives a setting signal, adjusts the setting signal according to a setting ratio to generate a leakage current replica signal, Wherein in the leakage current detection mode, the sense amplifier compares the leakage current on the first common bit line with the leakage current replica signal to generate a comparison result, and the proportional controller adjusts the setting according to the comparison result When the comparison result changes from a first logic level to a second logic level, the leakage current information is generated according to the leakage current replica signal. The memory according to claim 3, wherein the setting signal, the leakage current replica signal and the reference signal are all current signals. The memory as claimed in claim 4, further comprising: a second sense amplifier coupled to a second common bit line; and a current mirror coupled between the first sense amplifier and the second sense amplifier Between the sense amplifiers, in the leakage current detection mode, the leakage current replica signal is mirrored to generate a mirrored leakage current replica signal that is transmitted to the second sense amplifier. The memory as described in claim 3, further comprising: a current mirror, disposed on the input terminal of the first sense amplifier, in the data reading mode, mirroring the setting signal according to the leakage current information to generate The reference signal, wherein the leakage current information is a current signal. The memory according to claim 3, wherein the reference signal is a voltage signal, and in the read data mode, the sense amplifier adjusts the impedance on the input terminal to generate the reference signal according to the leakage current information. The memory according to claim 3, wherein in the data reading mode, the sense amplifier combines the leakage current information and a preset threshold signal to generate the reference signal. A method for reading a memory, comprising: providing a first sense amplifier to couple to a first common bit line; in a leakage current detection mode, enabling the first sense amplifier to detect a selected The middle memory cell block leaks current on the first common bit line to generate a leakage current information; and in a read data mode, the first sense amplifier device provides a reference signal according to the leakage current information, generating a read data by comparing the read signal on the first common bit line with the reference signal, wherein the leakage current detection mode occurs before the read data mode, wherein in the leakage current detection mode, All the word lines corresponding to the selected memory cell block are disabled. The memory reading method as described in claim item 9 further includes: in the data reading mode, enabling a selected word line of the word lines, at least one of the word lines Unchecked character lines are disabled. The memory reading method as described in claim 9, wherein the step of generating the leakage current information includes: coupling a first input terminal of a sense amplifier to the first common bit line; providing a proportional controller to be coupled to a second input terminal of the sense amplifier; to make the proportional controller receive a setting signal, and adjust the setting signal according to a setting ratio to generate a leakage current replica signal; In the leakage current detection mode, the sense amplifier is made to compare the leakage current on the first common bit line with the leakage current replica signal to generate a comparison result, and the proportional controller adjusts the setting according to the comparison result ratio; and when the comparison result changes from a first logic level to a second logic level, generating the leakage current information according to the leakage current replica signal. The method for reading memory according to claim 11, wherein the setting signal, the leakage current replica signal and the reference signal are all current signals. The memory reading method as described in claim 12, further comprising: coupling a current mirror between the first sense amplifier and a second sense amplifier; and making the current mirror according to a mirror ratio and The leakage current information is used to generate a mirror reference signal sent to the second sense amplifier. The memory reading method according to claim 11, wherein the sense amplifier converts the leakage current on the first common bit line into a first voltage signal, and the reference signal is a second voltage signal. The memory reading method according to claim 14 further includes: in the data reading mode, adjusting the impedance of the input terminal of the sense amplifier to generate the reference signal according to the leakage current information. The memory reading method as described in claim 11 further includes: in the data reading mode, combining the leakage current information and a preset critical signal to generate the reference signal.

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