TWI783711B - Gate driving apparatus and driving method thereof - Google Patents

Abstract

A gate driving apparatus and driving method thereof are provided. A gate driving apparatus includes a plurality of shift register circuits. The shift register circuits are coupled in series, and a Nth stage shift register circuit includes a gate driving signal generator and voltage compensator. The gate driving signal generator generates an Nth gate driving signal at an output end according to a first control signal and a prior stage first control signal, and based on a first clock signal. The voltage compensator adjusts a signal strength of the Nth gate driving signal according to the first control signal and the prior stage first control signal, and based on a second clock signal.

Description

Gate driving device and driving method thereof

The present invention relates to a gate driving device, and in particular to a gate driving device for driving a display panel.

In recent years, many products integrate the gate driver in the display driver circuit on the glass, that is, the Gate-Driver-on-Array (GOA) circuit. The GOA circuit has many advantages. It can reduce the width of the frame of the display panel to achieve the effect of a narrow frame, thereby effectively reducing the design area of the internal circuit of the display.

With the rise of the e-sports market, users have higher requirements for the frame rate (Frame Rate) of electronic products (such as notebook computers, tablet computers, smart phones, etc.). Therefore, designers usually use high-frequency capabilities architecture to design GOA circuits. However, in the case that electronic products generally have low power consumption requirements and the GOA circuit is a physical circuit on the panel, when the electronic device needs to lower the frame update rate to reduce power consumption according to the user's usage situation, the GOA circuit initially It is a high-frequency capability architecture. Therefore, under the same low-frequency operation conditions, the power consumption of the GOA circuit of the electronic product of the e-sports type will be higher than that of the GOA of the general type of electronic product.

In other words, how to enable the electronic device to optimize the power consumption of the GOA circuit according to the user's usage situation, so as to improve the performance of the electronic device, will be an important issue for those skilled in the art.

The invention provides a gate driving device and its driving method, which can optimize the power consumption of the gate driving signal generator according to the user's use situation, so as to improve the efficiency of the gate driving device.

The gate driving device of the present invention includes a plurality of shift register circuits. A plurality of shift register circuits are coupled in series and generate a plurality of gate drive signals respectively, wherein the shift register circuit of the Nth stage includes a gate drive signal generator and a voltage compensator. The gate drive signal generator has a first control terminal and a second control terminal for respectively receiving the first control signal and the previous first control signal. The gate driving signal generator generates an Nth-level gate driving signal at the output terminal according to the first control signal and the first control signal of the previous stage, and based on the first clock signal. The voltage compensator is coupled to the first control terminal, the second control terminal and the output terminal, and is used to adjust the gate driving signal of the Nth stage according to the first control signal and the first control signal of the previous stage, and based on the second clock signal signal strength.

The driving method of the gate driving device of the present invention includes: providing a plurality of shift register circuits coupled in series to generate a plurality of gate driving signals respectively; providing a gate driving signal generator to receive the first control signal and the first control signal of the previous stage, and make the gate driving signal generator generate the gate driving signal of the Nth stage at the output end according to the first control signal and the first control signal of the previous stage, and based on the first clock signal; and A voltage compensator is provided to adjust the signal strength of the Nth stage gate driving signal according to the first control signal and the previous first control signal, and based on the second clock signal.

Based on the above, the gate driving device of the present invention can reduce the response time of the gate driving signal through the voltage compensator when the display panel has a high frame refresh rate. In this way, under the premise that the circuit structure of the gate drive signal generator cannot be changed, the voltage compensator can be used to adjust the response time of the gate drive signal correspondingly according to the user's usage situation, so as to make the gate drive The power consumption of the signal generator achieves the best benefit, and the working efficiency of the gate driving device is improved.

The term "coupled (or connected)" used throughout the specification of this case (including the scope of claims) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or certain A connection means indirectly connected to the second device. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

Please refer to FIG. 1 . FIG. 1 is a circuit diagram of an Nth stage shift register circuit according to an embodiment of the present invention. Wherein, the gate driving device is composed of a plurality of shift register circuits coupled in series, and generates a plurality of gate driving signals respectively. Taking the shift register circuit 1000 of the Nth stage as an example, the shift register circuit 1000 includes a gate drive signal generator 100 and a voltage compensator 110 , wherein the aforementioned N is a positive integer.

In this embodiment, the gate driving signal generator 100 has a control terminal CT1 and a control terminal CT2. The control terminal CT1 and the control terminal CT2 can respectively receive the first control signal P(n) and the previous first control signal P(n-x). The gate driving signal generator 100 can generate the Nth-level gate driving signal G( n).

On the other hand, the voltage compensator 110 is coupled to the control terminal CT1, the control terminal CT2 and the output terminal OUT of the gate driving signal generator 100, and can respectively receive the first control signal P through the control terminal CT1 and the control terminal CT2. (n) and the previous first control signal P(n-x). In addition, the voltage compensator 110 can adjust the signal strength of the gate driving signal G(n) of the Nth stage according to the first control signal P(n) and the first control signal P(n-x) of the previous stage, and based on the clock signal DCK .

Specifically, in this embodiment, the clock signal CK and the clock signal DCK may be independent signals, wherein the clock signal CK may be set to transition periodically. In addition, the gate driving device can generate the mode selection signal SEL according to the usage situation of the user, and the gate driving device can set the state of the clock signal DCK according to the mode selection signal SEL.

For example, when the voltage compensator 110 receives the mode selection signal SEL indicating the first operation mode, it indicates that the display panel (not shown) operates in a low frame rate mode (for example, the display panel operates in a word processing mode or a display The frame update rate of the panel is less than or equal to 60 hertz (Hz), at this time, the clock signal DCK can be set to maintain the gate low voltage state. And when the voltage compensator 110 receives the mode selection signal SEL indicating the second operation mode different from the first operation mode, it indicates that the display panel is operating in a high frame refresh rate mode (for example, the display panel is operating in an e-sports operation mode or The frame update rate of the display panel is greater than 60 Hz), at this time, the clock signal DCK can be set to transition periodically and be synchronized with the clock signal CK.

Further, in this embodiment, when the voltage compensator 110 is operated in the first operation mode according to the mode selection signal SEL, the gate driving signal generator 100 can be based on the first control signal P(n) and the previous stage A control signal P(n-x), based on the clock signal CK to generate an Nth gate driving signal G(n) at the output terminal OUT. At this time, the voltage compensator 110 may stop adjusting the gate driving signal G(n) of the Nth stage according to the clock signal DCK in the gate low voltage state.

On the other hand, when the voltage compensator 110 operates in the second operation mode according to the mode selection signal SEL, the gate drive signal generator 100 also operates according to the first control signal P(n) and the previous first control signal P (n-x), and based on the clock signal CK to generate an Nth gate driving signal G(n) at the output terminal OUT. Next, the voltage compensator 110 can generate the Nth-level gate driving signal G according to the first control signal P(n) and the first control signal P(n-x) of the previous stage, and based on the clock signal DCK which is periodically in transition. (n).

It is worth mentioning that since the output terminal OUT of the gate drive signal generator 100 and the output terminal OUT of the voltage compensator 110 are short-circuited, the Nth stage gate drive generated by the gate drive signal generator 100 The signal after the superposition of the signal G(n) and the Nth-level gate drive signal G(n) generated by the voltage compensator 110 is The Nth stage gate drive signal G(n) finally generated by the shift register circuit 1000 . In this way, the voltage compensator 110 can reduce the rising time and falling time of the Nth-level gate driving signal G(n) generated by the shift register circuit 1000 according to the periodically transitioning clock signal DCK, so as to enhance overall output capability.

In other words, the gate driving device of this embodiment can enable the gate driving signal generator 100 to normally generate the Nth-level gate driving signal G(n) when the display panel has a low frame refresh rate. When it is determined that the display panel has a high frame refresh rate, the voltage compensator 110 can be used to reduce the response time of the Nth-level gate driving signal G(n). In this way, under the premise that the circuit structure of the gate driving signal generator 100 cannot be changed, the voltage compensator 110 can be used in this embodiment to adjust the Nth-level gate driving signal G accordingly according to the user's usage situation. The response time of (n) is used to optimize the power consumption of the gate driving signal generator 100 and improve the working efficiency of the gate driving device.

FIG. 2 is a circuit diagram of a gate driving signal generator and a voltage compensator according to an embodiment of the invention. Referring to FIG. 2 , in this embodiment, the shift register circuit 2000 includes a gate driving signal generator 300 and a voltage compensator 400 . The gate driving signal generator 300 includes an output stage circuit 310 , a voltage regulator 320 and a voltage regulator 330 .

The output stage circuit 310 includes a transistor T12 and a transistor T13. The first terminal of the transistor T12 (for example, the source terminal) receives the start signal F(n), the second terminal of the transistor T12 (for example, the drain terminal) receives the clock signal CK, and the control terminal of the transistor T12 (for example, the gate Extreme) is coupled to the control terminal CT3 to receive the second control signal Q(n). The first terminal of the transistor T13 is coupled to the output terminal OUT, the second terminal of the transistor T13 receives the clock signal CK, and the control terminal of the transistor T13 is coupled to the control terminal CT3 to receive the second control signal Q(n) .

The voltage regulator 320 includes a diode D1 and a pull-down circuit 340 . Wherein, the diode D1 includes a transistor T11. The first terminal of the transistor T11 is coupled to the control terminal CT3 , and the second terminal of the transistor T11 and the control terminal are commonly coupled to receive the pre-stage enable signal F(n−2). The transistor T11 of this embodiment can form a diode D1 according to the connection mode of the diode connection. Wherein, the cathode terminal of the diode D1 (that is, the first terminal of the transistor T11) is coupled to the control terminal CT3, and the anode terminal of the diode D1 (that is, the second terminal of the transistor T11) receives the pre-stage start signal F(n-2).

The pull-down circuit 340 includes transistors T2-T7. The first terminal of the transistor T2 is coupled to the system low voltage VSS1, the second terminal of the transistor T2 is coupled to the control terminal CT3 to receive the second control signal Q(n), and the control terminal of the transistor T2 is coupled to the control terminal CT3. terminal CT1 to receive the first control signal P(n). The first terminal of the transistor T3 is coupled to the system low voltage VSS1, the second terminal of the transistor T3 is coupled to the output terminal OUT, and the control terminal of the transistor T3 is coupled to the control terminal CT1 to receive the first control signal P( n).

The first terminal of the transistor T4 is coupled to the system low voltage VSS1, the second terminal of the transistor T4 is coupled to the control terminal CT3 to receive the second control signal Q(n), and the control terminal of the transistor T4 is coupled to the control terminal CT3. Terminal CT2 to receive the previous first control signal P(n-x). The first terminal of the transistor T5 is coupled to the system low voltage VSS1, the second terminal of the transistor T5 is coupled to the output terminal OUT, and the control terminal of the transistor T5 is coupled to the control terminal CT2 to receive the first control signal of the previous stage P(n-x).

The first terminal of the transistor T6 is coupled to the system low voltage VSS1, the second terminal of the transistor T6 is coupled to the control terminal CT3 to receive the second control signal Q(n), and the control terminal of the transistor T6 receives the second control signal Q(n) of the subsequent stage. Two gate driving signals G(n+4). The first terminal of the transistor T7 is coupled to the system low voltage VSS1, the second terminal of the transistor T7 is coupled to the output terminal OUT, and the control terminal of the transistor T7 receives the first gate drive signal G(n+2) of the subsequent stage .

The voltage regulator 330 includes a diode D2 , a transistor T15 and a pull-down circuit 350 . Wherein, the diode D2 includes a transistor T8. The first terminal of the transistor T8 is coupled to the control terminal of the transistor T15 , and the second terminal of the transistor T8 and the control terminal are commonly coupled to receive the third control signal LC. The transistor T8 of this embodiment can form a diode D2 according to the connection method of the diode configuration. Wherein, the cathode end of the diode D2 (that is, the first end of the transistor T8) is coupled to the control end of the transistor T15, and the anode end of the diode D2 (that is, the second end of the transistor T8) receives the first Three control signals LC. A first terminal of the transistor T15 is coupled to the control terminal CT1, a second terminal of the transistor T15 is coupled to the anode terminal of the diode D2, and a control terminal of the transistor T15 is coupled to the cathode terminal of the diode D2.

The pull-down circuit 350 includes transistors T9-T14. The first terminal of the transistor T9 is coupled to the system low voltage VSS1, the second terminal of the transistor T9 is coupled to the first terminal of the transistor T8, and the control terminal of the transistor T9 receives the second control signal Q(n- 2). The first terminal of the transistor T10 is coupled to the system low voltage VSS1, the second terminal of the transistor T10 is coupled to the control terminal CT1 to receive the first control signal P(n), and the control terminal of the transistor T10 receives the first stage Two control signals Q(n-2).

The first end of the transistor T11 is coupled to the system low voltage VSS1 , the second end of the transistor T11 is coupled to the first end of the transistor T8 , and the control end of the transistor T11 receives the second control signal Q(n). The first terminal of the transistor T12 is coupled to the system low voltage VSS1, the second terminal of the transistor T12 is coupled to the control terminal CT1 to receive the first control signal P(n), and the control terminal of the transistor T12 receives the second control Signal Q(n). The first terminal of the transistor T13 is coupled to the system low voltage VSS1, the second terminal of the transistor T13 is coupled to the first terminal of the transistor T8, and the control terminal of the transistor T13 receives the second control signal Q(n+ 2). The first terminal of the transistor T14 is coupled to the system low voltage VSS1, the second terminal of the transistor T14 is coupled to the control terminal CT1 to receive the first control signal P(n), and the control terminal of the transistor T14 receives the second Two control signals Q(n+2).

The voltage compensator 400 includes transistors T21 - T23 and a pull-down circuit 360 . The first terminal of the transistor T21 is coupled to the driving terminal A1, and the second terminal and the control terminal of the transistor T21 are commonly coupled to receive the previous-stage enabling signal DF(n−2). A first terminal of the transistor T22 receives the enable signal DF(n), a second terminal of the transistor T22 receives the clock signal DCK, and a control terminal of the transistor T22 is coupled to the driving terminal A1. The first terminal of the transistor T23 is coupled to the output terminal OUT, the second terminal of the transistor T23 receives the clock signal DCK, and the control terminal of the transistor T23 is coupled to the driving terminal A1.

The pull-down circuit 360 includes a transistor T16 and a transistor T17. A first terminal of the transistor T16 is coupled to the system low voltage VSS2 , a second terminal of the transistor T16 is coupled to the driving terminal A1 , and a control terminal of the transistor T16 receives the first control signal P(n). The first end of the transistor T17 is coupled to the system low voltage VSS2 , the second end of the transistor T17 is coupled to the driving end A1 , and the control end of the transistor T17 receives the previous first control signal P(n-x).

In particular, in this embodiment, the low system voltage VSS1 and the low system voltage VSS2 may be independent gate low voltages, which are not particularly limited here. In addition, in this embodiment, the widths of the transistors T11 - T13 in the gate driving signal generator 300 are respectively proportional to the widths of the transistors T21 - T23 in the voltage compensator 400 .

For example, on the premise that the shift register circuit 2000 only includes the gate drive signal generator 300, assuming that the width and dimension requirements of the transistors T11-T13 of the gate drive signal generator 300 are all 7000 μm, then when the shift When the bit temporary storage circuit 2000 includes the gate drive signal generator 300 and the voltage compensator 400, the width dimensions of the transistors T11-T13 can be designed to be 4000 μm, while the width dimensions of the transistors T21-T23 in the voltage compensator 400 are Can be designed to 3000µm.

That is to say, in this embodiment, when the shift register circuit 2000 includes the gate drive signal generator 300 and the voltage compensator 400, the width dimensions of the transistors T11-T13 and the transistors T21-T23 can be determined by Effectively reduce, thereby reducing the overall power consumption.

3A and 3B are schematic waveform diagrams of the Nth-stage shift register circuit in different modes according to an embodiment of the present invention. For the implementation details of the shift register circuit 2000 in the first operation mode, please refer to FIG. 2 and FIG. 3A at the same time.

In detail, in the first operation mode, the clock signal DCK of this embodiment can be set to maintain the state of the gate low voltage VGL. At this time, the voltage compensator 400 may stop generating or stop adjusting the Nth-level gate driving signal G(n).

Further, when the shift register circuit 2000 operates in the time interval PH11 of the first operation mode, the pull-down circuit 340 of the voltage regulator 320 can be based on the first control signal P(n), the previous first control signal P( n-x), the subsequent first gate drive signal G(n+2) and the subsequent second gate drive signal G(n+4) to pull down the second control signal Q(n) on the control terminal CT3 and the output terminal Nth stage gate drive signal G(n) on OUT.

In this case, the transistors T12 and T13 of the output stage circuit 310 are turned off, which makes the gate driving signal generator 300 generate the Nth gate driving signal G(n) at a low voltage level.

On the other hand, when the shift register circuit 2000 is operating in the time interval PH12 of the first operation mode, the pull-down circuit 350 of the voltage regulator 330 can operate according to the second control signal Q(n), the previous second control signal Q (n-2) and the subsequent second control signal Q(n+2) to pull down the first control signal P(n). In this case, the pull-down circuit 340 of the voltage regulator 320 can be disconnected according to the first control signal P(n) which is a low voltage level, so that the output stage circuit 310 can be turned off according to the second control signal P(n) which is a high voltage level. The control signal Q(n) and the enabling signal F(n) are used to generate an Nth-level gate driving signal G(n) at a high voltage level based on the clock signal CK.

In particular, in the time interval PH12 of the first operation mode, the rise time Tr and fall time Tf of the Nth-level gate drive signal G(n) generated by the gate drive signal generator 2000 are 4.54µ seconds and 3.95µ seconds.

On the other hand, for the implementation details when the shift register circuit 2000 operates in the time interval PH13 of the first operation mode, reference may be made to the description of the shift register circuit 2000 operating in the time interval PH11 of the first operation mode. I won't go into details on this.

Next, for the implementation details of the shift register circuit 2000 in the second operation mode, please refer to FIG. 2 and FIG. 3B at the same time. In detail, in the second mode, the clock signal DCK of this embodiment can be set to transition periodically and be synchronized with the clock signal CK.

Further, when the shift register circuit 2000 operates in the time interval PH21 of the second operation mode, the pull-down circuit 340 of the voltage regulator 320 can be based on the first control signal P(n), the previous first control signal P( n-x), the subsequent first gate drive signal G(n+2) and the subsequent second gate drive signal G(n+4) to pull down the second control signal Q(n) on the control terminal CT3 and the output terminal Nth stage gate drive signal G(n) on OUT.

In this case, the transistors T12 and T13 of the output stage circuit 310 are turned off, which makes the gate driving signal generator 300 generate the Nth gate driving signal G(n) at a low voltage level.

On the other hand, the pull-down circuit 360 of the voltage compensator 400 can pull down the voltage DQ( n), so that the transistor T22 and the transistor T23 are turned off.

Next, when the shift register circuit 2000 is operating in the time interval PH22 of the second operation mode, the pull-down circuit 350 of the voltage regulator 330 can be based on the second control signal Q(n), the previous second control signal Q(n- 2) and the subsequent second control signal Q(n+2) to pull down the first control signal P(n). In this case, the pull-down circuit 340 of the voltage regulator 320 can be disconnected according to the first control signal P(n) which is a low voltage level, so that the output stage circuit 310 can be turned off according to the second control signal P(n) which is a high voltage level. The control signal Q(n) and the enabling signal F(n) are used to generate an Nth-level gate driving signal G(n) at a high voltage level based on the clock signal CK.

At the same time, the transistor T16 and the transistor T17 of the pull-down circuit 360 can be turned off respectively according to the first control signal P(n) of the low voltage level and the first control signal P(n-x) of the previous stage, so that the drive The voltage DQ(n) on the terminal A1 is pulled up to a high voltage level.

In this case, the voltage compensator 400 can adjust the N-th stage gate driving signal G(n) according to the pulled-up voltage DQ(n) and based on the clock signal DCK, so that the shift register circuit 2000 generates The rising time Tr and falling time Tf of the Nth-level gate driving signal G(n) are reduced to 2.72µs and 2.4µs respectively, so as to reduce the response time of the Nth-level gate driving signal G(n).

On the other hand, for the implementation details when the shift register circuit 2000 operates in the time interval PH23 of the second operation mode, reference may be made to the description of the shift register circuit 2000 operating in the time interval PH23 of the second operation mode. I won't go into details on this.

FIG. 4 is a schematic waveform diagram of a third control signal according to an embodiment of the invention. Please refer to FIG. 2 and FIG. 4 at the same time. In the gate driving device of this embodiment, the diodes D2 (or transistors T8 ) of the shift register circuits of each stage can be controlled by the third control signal LC.

As shown in FIG. 4, in this embodiment, the third control signal (such as the third control signal LC1) of the shift register circuit of the current stage is connected with the third control signal (such as the third control signal LC1) of the shift register circuit of the next stage (such as are the third control signal LC2 ) are periodically transitioned and are complementary to each other. Therefore, the transistor T8 of each stage can be turned on periodically according to the third control signal LC.

FIG. 5 is a layout diagram of a plurality of shift register circuits according to an embodiment of the present invention. In the gate driving device of this embodiment, a plurality of shift register circuits (for example, the previous stage shift register circuit S(n-1), the shift register circuit S(n) and the subsequent stage shift register circuit The storage circuit S(n+1)) may be configured between the active area (AA) and the frame area of the display panel.

On the layout of the gate drive device, from left to right, it can be the signal routing of the gate drive signal generator (for example, the clock signal CK, the third control signal LC, the system low voltage VSS1 and the start signal F (n), etc.), gate drive signal generator, voltage compensator, and signal routing of the voltage compensator (for example, clock signal DCK and start signal DF(n) etc.).

FIG. 6 is a flowchart of a driving method of a gate driving device according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 6 at the same time. In step S610 , the gate driving device may provide a plurality of shift register circuits coupled in series to generate a plurality of gate driving signals respectively. In step S620, the gate driving device may provide a gate driving signal generator to receive the first control signal and the first control signal of the preceding stage, and make the gate driving signal generator control the signal, and based on the first clock signal to generate an Nth-level gate drive signal at the output terminal. In step S630 , the gate driving device may provide a voltage compensator to adjust the signal strength of the Nth stage gate driving signal according to the first control signal and the previous first control signal, and based on the second clock signal.

The implementation details of each step have been described in detail in the aforementioned embodiments and implementation modes, and will not be repeated here.

To sum up, the gate driving device of the present invention can reduce the response time of the gate driving signal through the voltage compensator when the display panel has a high frame refresh rate. In this way, under the premise that the circuit structure of the gate drive signal generator cannot be changed, the voltage compensator can be used to adjust the response time of the gate drive signal correspondingly according to the user's usage situation, so as to make the gate drive The power consumption of the signal generator achieves the best benefit, and the working efficiency of the gate driving device is improved.

1000, 2000, S(n), S(n-1), S(n+1): shift register circuit 100, 300: gate drive signal generator 110, 400: voltage compensator 310: output stage circuit 320, 330: voltage regulator 340, 350, 360: pull-down circuit A1: Drive end CK, DCK: clock signal CT1, CT2, CT3: control terminal D1, D2: Diodes DQ(n): Voltage DF(n), F(n): start signal DF(n-2), F(n-2): Pre-stage start signal G(n): Level N gate drive signal G(n+2): the first gate drive signal of the latter stage G(n+4): the second gate drive signal of the latter stage LC, LC1, LC2: the third control signal OUT: output terminal PH11～PH13, PH21～P23: time interval P(n): the first control signal P(n-x): the first control signal of the front stage Q(n): the second control signal Q(n-2): the second control signal of the front stage Q(n+2): the second control signal of the rear stage SEL: mode selection signal T11～T13, T21～T23, T2～T17: Transistor VSS1, VSS2: System low voltage

FIG. 1 is a circuit diagram of an Nth stage shift register circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a gate driving signal generator and a voltage compensator according to an embodiment of the invention. 3A and 3B are schematic waveform diagrams of the Nth-stage shift register circuit in different modes according to an embodiment of the present invention. FIG. 4 is a schematic waveform diagram of a third control signal according to an embodiment of the invention. FIG. 5 is a layout diagram of a plurality of shift register circuits according to an embodiment of the present invention. FIG. 6 is a flowchart of a driving method of a gate driving device according to an embodiment of the invention.

1000: shift temporary storage circuit

100: Gate drive signal generator

110: voltage compensator

CK, DCK: clock signal

CT1, CT2: control terminal

G(n): Level N gate drive signal

OUT: output terminal

P(n): the first control signal

P(n-x): the first control signal of the front stage

SEL: mode selection signal

Claims (18)

A gate driving device, comprising: a plurality of shift temporary storage circuits, the shift temporary storage circuits are coupled in series and generate a plurality of gate driving signals respectively, wherein the shift temporary storage circuit of the Nth stage includes: A gate drive signal generator has a first control terminal and a second control terminal to respectively receive a first control signal and a previous first control signal, the gate drive signal generator according to the first control signal and the first control signal of the previous stage, and based on a first clock signal to generate an Nth-level gate drive signal at an output terminal; and a voltage compensator, coupled to the first control terminal, the second The control terminal and the output terminal are used to adjust the signal strength of the Nth stage gate driving signal according to the first control signal and the previous first control signal, and based on a second clock signal. The gate driving device as claimed in item 1, wherein when the second clock signal is set to be in a periodic transition state, the voltage compensator reduces the Nth-level gate driving signal according to the second clock signal rise time and fall time. The gate driving device as described in Claim 1, wherein the voltage compensator includes: a first transistor, the first terminal of which is coupled to the output terminal, the second terminal of which receives the second clock signal, and controls The end is coupled to a drive end; a second transistor, the first end of which receives a start signal, the second end of which receives the second clock signal, and the control end of which is coupled to the drive end; A third transistor, the first terminal of which is coupled to the drive terminal, the second terminal of which is coupled to the control terminal and receives a previous start signal; and a pull-down circuit, coupled to the drive terminal and a system low voltage, and used to pull down the voltage on the driving end according to the first control signal and the previous first control signal. The gate driving device as described in claim 3, wherein the pull-down circuit includes: a fourth transistor, the first terminal of which is coupled to the system low voltage, the second terminal of which is coupled to the driving terminal, and the control terminal receiving the first control signal; and a fifth transistor, the first terminal of which is coupled to the system low voltage, the second terminal of which is coupled to the drive terminal, and the control terminal of which receives the preceding first control signal. The gate driving device as described in Claim 1, wherein the gate driving signal generator includes: an output stage circuit having a third control terminal for receiving a second control signal, the output stage circuit according to the second control signal and a start signal, and based on the first clock signal to generate the Nth-level gate drive signal at the output terminal; a first voltage regulator, coupled to the output stage circuit, the first voltage regulator Adjusting the second control signal and the first gate drive signal according to the first control signal, the first control signal of the previous stage, the first gate driving signal of the latter stage, the second gate driving signal of the latter stage and the enabling signal of the former stage N-level gate drive signal; and a second voltage regulator, coupled to the first voltage regulator, the second voltage regulator according to the second control signal, a previous second control signal, a rear second control signal and a third control signal to adjust the first control signal. The gate driving device as described in claim 5, wherein the output stage circuit includes: a first transistor, the first terminal of which receives the start signal, the second terminal of which receives the first clock signal, and the control terminal of which receives the the second control signal; and a second transistor, the first end of which is coupled to the output end, the second end of which receives the first clock signal, and the control end of which receives the second control signal. The gate driving device as described in claim 5, wherein the first voltage regulator includes: a diode, the anode terminal of which receives the previous stage startup signal, and the cathode terminal of which is coupled to the third control terminal; and a pull-down circuit, coupled to the first control terminal, the third control terminal and the output terminal, the pull-down circuit is based on the first control signal, the first control signal of the previous stage, the first gate drive signal of the latter stage and The second gate driving signal of the subsequent stage is used to pull down the second control signal and the gate driving signal of the Nth stage. The gate driving device as claimed in item 7, wherein the diode includes: a first transistor, the first terminal of which is coupled to the third control terminal, and the second terminal and the control terminal are jointly coupled and receive The pre-stage enable signal, and wherein the pull-down circuit includes: A second transistor, whose first end is coupled to a system low voltage, whose second end receives the second control signal, whose control end receives the first control signal; a third transistor, whose first end is coupled Connected to the system low voltage, its second terminal is coupled to the output terminal, its control terminal receives the first control signal; a fourth transistor, its first terminal is coupled to the system low voltage, its second terminal Receive the second control signal, and its control terminal receives the first control signal of the previous stage; a fifth transistor, its first terminal is coupled to the system low voltage, its second terminal is coupled to the output terminal, and its control The terminal receives the first control signal of the previous stage; a sixth transistor, the first terminal of which is coupled to the system low voltage, the second terminal of which receives the second control signal, and the control terminal of which receives the second gate of the subsequent stage a driving signal; and a seventh transistor, the first terminal of which is coupled to the system low voltage, the second terminal of which is coupled to the output terminal, and the control terminal of which receives the subsequent first gate driving signal. The gate driving device as described in Claim 5, wherein the second voltage regulator includes: a diode, the anode terminal of which receives the third control signal; a first transistor, the first terminal of which is coupled to the a first control terminal, the second terminal of which is coupled to the anode terminal of the diode, and the control terminal is coupled to the cathode terminal of the diode; and a pull-down circuit, coupled to the cathode terminal of the diode and The first control terminal pulls down the first control signal according to the second control signal, the previous second control signal and the subsequent second control signal. The gate driving device as claimed in item 9, wherein the diode includes: a second transistor, the second terminal of which and the control terminal are commonly coupled to receive the third control signal, and wherein the pull-down circuit includes : a third transistor, the first end of which is coupled to a system low voltage, the second end of which is coupled to the first end of the second transistor, and the control end of which receives the second control signal of the previous stage; a first Four transistors, the first terminal of which is coupled to the system low voltage, the second terminal of which receives the first control signal, and the control terminal of which receives the previous second control signal; a fifth transistor, the first terminal of which is coupled Connected to the system low voltage, its second terminal is coupled to the first terminal of the second transistor, and its control terminal receives the second control signal; a sixth transistor, its first terminal is coupled to the system low voltage, the second end of which receives the first control signal, and its control end receives the second control signal; a seventh transistor, whose first end is coupled to the system low voltage, and whose second end is coupled to the first The first end of the second transistor, the control end of which receives the second control signal of the subsequent stage; and an eighth transistor, the first end of which is coupled to the system low voltage, and the second end of which receives the first control signal, Its control terminal receives the subsequent second control signal. The gate driving device as claimed in claim 1, wherein when the voltage compensator is operated in a first operation mode according to a mode selection signal, the second clock signal is maintained at a gate low voltage, and when the When the voltage compensator operates in a second operation mode according to the mode selection signal, the first clock signal is synchronized with the first clock signal Two clock signals, wherein the first clock signal and the second clock signal are independent signals. A driving method for a gate driving device, comprising: providing a plurality of shift register circuits coupled in series to generate a plurality of gate driving signals respectively; providing a gate driving signal generator to receive a first control signal and a first control signal of the previous stage, and make the gate drive signal generator generate an Nth at an output terminal according to the first control signal and the first control signal of the previous stage, and based on a first clock signal level gate driving signal; and providing a voltage compensator to adjust the signal strength of the Nth level gate driving signal according to the first control signal and the previous first control signal, and based on a second clock signal. The driving method according to claim 12, wherein when the second clock signal is set to be in a periodic transition, the voltage compensator reduces the level of the Nth-level gate drive signal according to the second clock signal rise time and fall time. The driving method as claimed in claim 12, wherein the voltage compensator is provided to adjust the Nth stage gate driving signal based on the second clock signal according to the first control signal and the previous stage first control signal The step of the signal strength includes: providing a first transistor to receive the second clock signal; providing a second transistor to receive a start signal and the second clock signal; providing a third transistor to receive a pre-stage enable signal; and A pull-down circuit is provided to pull down the voltage on the driving end of the first transistor according to the first control signal and the previous first control signal. The driving method as claimed in claim 12, wherein the gate drive signal generator is provided to receive the first control signal and the first control signal of the preceding stage, and the gate drive signal generator is made to follow the first control signal and the first control signal of the previous stage, and the step of generating the Nth-level gate drive signal at the output terminal based on the first clock signal includes: providing an output-level circuit to receive a second control signal, and making The output stage circuit is based on the second control signal, a start signal, and based on the first clock signal to generate the Nth-level gate drive signal at the output terminal; a first voltage regulator is provided to rely on the first control signal, the first control signal of the previous stage, a first gate driving signal of the subsequent stage, a second gate driving signal of the subsequent stage, and a start signal of the previous stage to adjust the second control signal and the gate of the Nth stage driving signal; and providing a second voltage regulator to adjust the first control signal according to the second control signal, a previous second control signal, a rear second control signal and a third control signal. The driving method according to claim 15, wherein the first voltage regulator is provided to operate according to the first control signal, the first control signal of the previous stage, the first gate drive signal of the subsequent stage, and the second gate of the subsequent stage. The step of adjusting the second control signal and the Nth stage gate driving signal by using the pole driving signal and the previous stage start signal includes: providing a diode to receive the previous stage start signal; and A pull-down circuit is provided to pull down the second control signal and the Nth level gate drive signal. The driving method according to claim 15, wherein the second voltage regulator is provided to adjust the The step of the first control signal includes: providing a diode to receive the third control signal; providing a first transistor to receive the third control signal; and providing a pull-down circuit to rely on the second control signal, the previous The stage second control signal and the subsequent stage second control signal are used to pull down the first control signal. The driving method as claimed in claim 12, wherein when the voltage compensator is operated in a first operation mode according to a mode selection signal, the second clock signal is maintained at a gate low voltage, and when the voltage compensator is made to operate in a first operation mode When the voltage compensator operates in a second operation mode according to the mode selection signal, the first clock signal is synchronized with the second clock signal, wherein the first clock signal and the second clock signal are independent of each other signal of.

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