TWI783534B - Dynamic random access memory and method of manufacturing the same - Google Patents

Abstract

Provided is a dynamic random access memory including: a substrate having a trench; a gate dielectric layer located on sidewalls and a bottom surface of the trench; the metal filling layer filled in the trench; an adhesion layer located between the gate dielectric layer and the metal filling layer; a plurality of work function layers located in the trench, wherein each work function layer is located between a sidewall of the gate dielectric layer and a sidewall of the adhesion layer; a plurality of doped regions located in the substrate on both sides of the trench, wherein the plurality of work function layer part and portions of the gate dielectric layer are laterally sandwiched between the plurality of doped regions.

Description

Dynamic random access memory and manufacturing method thereof

The present invention relates to an integrated circuit and its manufacturing method, and in particular to a dynamic random access memory and its manufacturing method.

The performance of DRAM directly affects its yield and its related specifications, such as write recovery time (write recovery time, tWR) and refresh performance (refresh performance). However, as the size of DRAM designs continues to shrink and semiconductor devices continue to develop toward high integration, the performance of DRAMs also decreases. Therefore, how to maintain or improve the performance of DRAM has become an urgent problem to be solved in this field.

Embodiments of the present invention provide a dynamic random access memory and a manufacturing method thereof, which can reduce GIDL leakage current and improve writing recovery time.

An embodiment of the present invention provides a dynamic random access memory, including: a substrate having a trench; a gate dielectric layer located on the sidewall and bottom of the trench; a metal filling layer, in the trench; an adhesion layer between the gate dielectric layer and the metal fill layer; a plurality of work function layers in the trench, wherein each work function layer is between a sidewall of the gate dielectric layer and a sidewall of the adhesion layer and a plurality of doped regions located in the substrates on both sides of the trench, wherein part of the plurality of work function layers and part of the gate dielectric layer are laterally sandwiched between part of the plurality of doped regions and part of the adhesive layer between.

An embodiment of the present invention provides a method for manufacturing a dynamic random access memory, including: providing a substrate; forming a trench in the substrate; forming a gate dielectric layer on the sidewall and bottom of the trench; a function layer; an adhesive layer is formed on the sidewalls of the plurality of work function layers and the gate dielectric layer on the bottom surface of the trench; a metal filling layer is filled in the trench; and a plurality of doped regions are formed in the substrates on both sides of the trench, Part of the multiple work function layers and part of the gate dielectric layer are sandwiched between the part of the multiple doped regions and the part of the adhesive layer in the lateral direction.

Based on the above, the DRAM and the manufacturing method thereof according to the embodiments of the present invention can reduce GIDL leakage current and improve writing recovery time.

10: Base

11: Ditch

12: gate dielectric material layer

14: Work function material layer

14a: Work function layer

16: Adhesive material layer

16a: Adhesive layer

18: metal filling material layer

18a: Metal fill layer

20: Top cover material layer

20a: top cover layer

24. S, D: doped area

P1, P2: part

WL: Embedded word line structure

1A to 1H are schematic cross-sectional views of a manufacturing method of a DRAM according to an embodiment of the present invention.

Referring to FIG. 1A, a substrate 10, such as a silicon substrate, is provided. Next, Yuki A trench 11 is formed in the bottom 10. Trenches 11 may form a layer of hard mask material on substrate 10 . Then, the hard mask material layer is patterned by lithography and etching processes to form a hard mask layer. Using the hard mask layer as a mask, an etching process is performed to partially remove the substrate 10 to form the trench 11 , and then the hard mask layer is removed. The trench 11 is, for example, a buried word line trench.

Referring to FIG. 1A , a gate dielectric material layer 12 is formed in the trench 11 . The gate dielectric material layer 12 is conformally formed on the inner surface of the trench 11 . The gate dielectric material layer 12 may be an oxide layer, such as silicon oxide. In some embodiments, a thermal oxidation process is further performed to allow oxygen to pass through the chemically deposited silicon oxide layer and react with the substrate 10 on the surface of the trench 11 to form another layer of silicon oxide.

Referring to FIG. 1B , a work function material layer 14 is formed on the gate dielectric material layer 12 . The work function material layer 14 has a different work function from the subsequently formed adhesive material layer 16 (as shown in FIG. 1D ). The work function of the work function material layer 14 is smaller than the work function of the adhesive material layer 16 . The work function material layer 14 includes a semiconductor, such as doped polysilicon, undoped polysilicon or a combination thereof.

Referring to FIG. 1C, an anisotropic etching process is performed to remove the work function material layer 14 covering the gate dielectric material layer 12 on the bottom surface of the trench 11, leaving two separate parts in the trench 11. Work function layer 14a. The work function layer 14 a respectively covers the sidewalls of the gate dielectric material layer 12 on the sidewalls of the trench 11 , exposing the gate dielectric material layer 12 on the bottom surface of the trench 11 .

Referring to FIG. 1D , an adhesive material layer 16 is formed on the sidewalls of the work function layer 14 a and the gate dielectric material layer 12 on the bottom surface of the trench 11 . The work function of the adhesive material layer 16 Greater than the work function of the work function layer. The adhesive material layer 16 can also be referred to as a barrier material layer or a buffer material layer. The adhesive material layer 16 includes metal, metal nitride or a combination thereof. The adhesive material layer 16 is, for example, titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof.

Referring to FIG. 1D , a metal filling material layer 18 is formed on the substrate 10 and filled in the remaining space of the trench 11 . The metal filling material layer 18 is metal or metal alloy, such as tungsten.

Referring to FIG. 1E, one or more etching processes are performed to remove part of the metal filling material layer 18, the adhesive material layer 16 and the work function material layer 14, leaving the metal filling layer 18a and the adhesive layer at the lower part of the trench 11. 16a and work function layer 14a.

Referring to FIG. 1G , a cap material layer 20 is formed on the substrate 10 and filled in the remaining space of the trench 11 . The cap material layer 20 is a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.

Referring to FIG. 1H, an etch-back process or a chemical mechanical polishing process is performed to remove the cap material layer 20 and the gate dielectric material layer 12 outside the trench 11, leaving the cap layer 20a and gate dielectric in the trench 11. Electrical layer 12a. The capping layer 20a covers and contacts the top surfaces of the metal filling layer 18a, the adhesive layer 16a, the work function layer 14a and the gate dielectric layer 12a. The capping layer 20a, the metal filling layer 18a, the adhesive layer 16a, the work function layer 14a and the gate dielectric layer 12a form the buried word line structure WL. The buried word line structure WL includes dual work function layers, wherein the work function layer 14a may be called a first work function layer; the adhesive layer 16a may be called a second work function layer.

Next, a plurality of doped regions 24 are formed in the substrate 10 on both sides of the trench 11 . The doped region 24 is, for example, a lightly doped source and drain region (LDD).

In this embodiment, the work function layer 14 a includes a first portion P1 and a second portion P2 separated from each other. In some embodiments, the first portion P1 and the second portion P2 are work function layers perpendicular to the surface of the substrate 10 . The doped region 24 includes a first doped region S and a second doped region D separated by the buried word line structure WL. The first part P1 of the work function layer 14 a , part of the gate dielectric layer 12 a , and part of the adhesive layer 16 a overlap with the first doped region S laterally. The first part P1 of the work function layer 14a and part of the gate dielectric layer 12a are laterally sandwiched between the first doped region S and part of the adhesive layer 16a. The second portion P2 of the work function layer 14 a , part of the gate dielectric layer 12 a , and part of the adhesive layer 16 a overlap with the second doped region D laterally. The second part P2 of the work function layer 14a and another part of the gate dielectric layer 12a are laterally sandwiched between the second doped region D and another part of the adhesive layer 16a.

The first portion P1 of the work function layer 14a is closer to the gate dielectric layer 12a than the adhesive layer 16a; the second portion P2 of the work function layer 14a is also closer to the gate dielectric layer 12a than the adhesive layer 16a. The first portion P1 and the second portion P2 of the work function layer 14 a are in contact with sidewalls of the gate dielectric layer 12 a respectively. The sidewall of the adhesive layer 16a is separated from the sidewall of the gate dielectric layer 12a by the first portion P1 and the second portion P2 of the work function layer 14a, and the bottom surface of the adhesive layer 16a is in contact with the gate dielectric layer 12a.

Since the work function layer 14a is closer to the gate dielectric layer 12a than the adhesive layer 16a, and the work function of the work function layer 14a is smaller than the work function of the adhesive layer 16a, the induced electric field can be reduced, and the gate-induced drain leakage current ( Gate Induced Drain Leakage, GIDL), improve write recovery time (tWR).

Furthermore, since the work function of the work function layer 14a is small, the work function layer 14a, the gate dielectric layer 12a and the doped region 24 can have a larger overlapping area in the lateral direction, and will not cause too high a GIDL. Therefore, on-current can be increased.

On the other hand, since the work function layer 14a is formed on the sidewall of the gate dielectric layer 12a, its end point is in contact with the cap layer 20a, and is away from the bottom corner of the doped region 24, so the corner electric field can be reduced.

In addition, the height of the sidewall work function layer 14a formed on the gate dielectric layer 12a can be easily controlled by etching back, thus reducing the difficulty of the manufacturing process.

10: Base

11: Ditch

14a: Work function layer

16a: Adhesive layer

18a: Metal fill layer

20a: top cover layer

24. S, D: doped area

P1, P2: part

WL: Embedded word line structure

Claims (9)

A dynamic random access memory, comprising: a substrate with a trench; a gate dielectric layer located on the sidewall and bottom of the trench; a metal filling layer located in the trench; an adhesive layer located on the gate dielectric layer between the metal filling layer; a plurality of work function layers located in the trench, wherein each work function layer is located between the sidewall of the gate dielectric layer and the sidewall of the adhesive layer; and a plurality of doped impurity regions located in the substrate on both sides of the trench, wherein part of the plurality of work function layers and part of the gate dielectric layer are laterally sandwiched between part of the plurality of doped regions and Part of the adhesive layer, wherein the work function of the plurality of work function layers is smaller than the work function of the adhesive layer. The DRAM according to claim 1, wherein the plurality of work function layers comprises a plurality of semiconductor layers. The DRAM according to claim 2, wherein the plurality of work function layers comprise polysilicon, doped polysilicon or a combination thereof. The DRAM according to claim 1, wherein the plurality of work function layers are closer to the plurality of doped regions than the adhesive layer. The DRAM according to claim 1 further includes a cap layer in contact with top surfaces of the metal filling layer, the adhesive layer, and the plurality of work function layers. A method of manufacturing a dynamic random access memory, comprising: A substrate is provided; a trench is formed in the substrate; a gate dielectric layer is formed on the sidewall and bottom surface of the trench; a plurality of work function layers are formed on the sidewalls of the gate dielectric layer; forming an adhesive layer on the gate dielectric layer on the sidewall and the bottom surface of the trench; filling the trench with a metal filling layer; and forming a plurality of doped layers in the substrate on both sides of the trench. region, wherein part of the plurality of work function layers and part of the gate dielectric layer are laterally sandwiched between part of the plurality of doped regions and part of the adhesive layer, wherein the plurality of The work function of the work function layer is smaller than the work function of the adhesive layer. The method for manufacturing a dynamic random access memory according to claim 6, wherein the method for forming the work function layer includes: forming a work function material layer covering the gate dielectric layer; and removing the layer covering the trench the work function material layer on the gate dielectric layer on the bottom surface of the to form the plurality of work function material layers. The method for manufacturing a DRAM according to claim 6, wherein the plurality of work function layers are formed before the adhesive layer is formed. The method for manufacturing a dynamic random access memory according to claim 6, further comprising: forming a cap layer in the trench to cover the metal filling layer, the adhesive layer, and the plurality of work function layers .

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