TWI782100B - Through-electrode substrate and semiconductor device using through-electrode substrate - Google Patents
Through-electrode substrate and semiconductor device using through-electrode substrate Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 186
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910010272 inorganic material Inorganic materials 0.000 claims abstract description 5
- 239000011147 inorganic material Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 89
- 230000000149 penetrating effect Effects 0.000 claims description 40
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- 239000000463 material Substances 0.000 claims description 25
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- 239000011521 glass Substances 0.000 abstract description 83
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 21
- 229910052802 copper Inorganic materials 0.000 description 21
- 239000010949 copper Substances 0.000 description 21
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Photovoltaic Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一種貫通電極基板,具有:由無機材料構成之基板;設置於前述基板上之第1配線;於與前述第1配線分離之位置,設置於該基板之貫通孔;設置於該貫通孔之內壁的貫通電極;及連接該第1配線及該貫通電極之第2配線。若根據本發明,則可提供一種貫通電極基板及其製造方法,該貫通電極基板為使用玻璃基板之高長寬比(aspect ratio)的貫通電極基板,可確保貫通電極與基板上之配線的導通,電可靠性獲得提升。A through-electrode substrate, comprising: a substrate made of an inorganic material; a first wiring provided on the substrate; a through hole provided in the substrate at a position separated from the first wiring; and a through hole provided on the inner wall of the through hole a through-electrode; and a second wiring connecting the first wiring and the through-electrode. According to the present invention, it is possible to provide a through-electrode substrate and a method of manufacturing the same. The through-electrode substrate is a through-electrode substrate with a high aspect ratio of a glass substrate, which can ensure conduction between the through-electrode and wiring on the substrate, and the electrical connection between the through-electrode substrate and the substrate. Reliability is improved.
Description
本發明係關於一種貫通電極基板。尤其是關於一種具有將貫通電極與基板上之配線交聯之交聯配線的貫通電極基板。The invention relates to a through-electrode substrate. In particular, it relates to a through-electrode substrate having cross-linked wiring for cross-linking the through-electrode and the wiring on the substrate.
近年來,隨著智慧型手機或筆記型電腦等電子機器之小型化或高速化,關於構成電子機器之半導體零件或裝載半導體零件之配線基板,亦不斷高密度化、高速化。In recent years, with the downsizing and speeding up of electronic equipment such as smartphones and notebook computers, the density and speed of semiconductor components constituting electronic equipment or wiring boards on which semiconductor components are mounted are also increasing.
於積層複數個配線基板之多層配線基板中,為了連接上下之配線,而使用形成有貫通配線基板之貫通電極的貫通電極基板。作為形成此種貫通電極之方法,當基材為有機物之有機基板的情形時,為了於貫通孔內形成配線得到導通,藉由進行無電鍍銅,而可得到形成於基板上之配線與形成於貫通孔內之貫通電極的導通。In a multilayer wiring board in which a plurality of wiring boards are laminated, a through-electrode board on which a through-electrode penetrating the wiring board is formed is used in order to connect upper and lower wirings. As a method of forming such a through-hole electrode, when the base material is an organic substrate, in order to form the wiring in the through-hole to achieve conduction, by performing electroless copper plating, the wiring formed on the substrate and the wiring formed on the substrate can be obtained. Conduction of the through-electrode in the through-hole.
於專利文獻1,揭示一種印刷配線基板,該印刷配線基板具有通孔(via hole),該通孔係於基板形成有底部之孔,然後於有底部之孔內形成導電層而成,其中該基材為玻璃環氧樹脂(glass epoxy)。
[先前技術文獻]
[專利文獻]In
專利文獻1:日本特開2008-205070號公報Patent Document 1: Japanese Patent Laid-Open No. 2008-205070
[發明所欲解決之課題][Problem to be Solved by the Invention]
然而,當基材為由玻璃、矽或陶瓷等無機材料構成之基板的情形時,難以將貫通孔之內壁作同樣地粗糙化,而為了形成無電鍍銅,必須預先形成密接層。又,當形成密接層後進行無電鍍銅之情形時,鍍銅僅會形成於形成有密接層之部分。於此情形時,若以無電鍍銅來連接基板上之配線與貫通孔內之貫通電極,則由於配線與貫通電極會透過絕緣性密接層連接,故電可靠性會有問題。However, when the base material is a substrate made of inorganic materials such as glass, silicon, or ceramics, it is difficult to roughen the inner walls of the through holes in the same way, and an adhesive layer must be formed in advance to form electroless copper plating. Moreover, when performing electroless copper plating after forming an adhesive layer, copper plating will be formed only in the part in which the adhesive layer was formed. In this case, if electroless copper plating is used to connect the wiring on the substrate and the through-electrode in the through-hole, the wiring and the through-electrode will be connected through the insulating adhesive layer, so there will be problems in electrical reliability.
鑑於上述問題,本發明的目的之一為提供一種貫通電極基板及其製造方法,該貫通電極基板為使用由玻璃等無機材料構成之基板的高長寬比(aspect ratio)之貫通電極基板,可確保貫通電極與基板上之配線的導通,電可靠性獲得提升。 [用以解決課題之手段]In view of the above-mentioned problems, one object of the present invention is to provide a through-electrode substrate and a method of manufacturing the same. The conduction between the electrodes and the wiring on the substrate improves the electrical reliability. [Means to solve the problem]
本發明之一實施形態的貫通電極基板具有: 由無機材料構成之基板; 設置於前述基板上之第1配線; 於與前述第1配線分離之位置,設置於前述基板之貫通孔; 設置於前述貫通孔之內壁的貫通電極;及 連接前述第1配線及前述貫通電極之第2配線。A through-electrode substrate according to an embodiment of the present invention has: Substrates made of inorganic materials; The first wiring provided on the aforementioned substrate; A through hole provided in the aforementioned substrate at a position separated from the aforementioned first wiring; a through-electrode provided on the inner wall of the aforementioned through-hole; and The first wiring and the second wiring of the penetrating electrode are connected.
本發明之一實施形態的貫通電極基板,亦可進一步具有設置於前述基板與前述貫通電極之間的密接層。The through-electrode substrate according to an embodiment of the present invention may further include an adhesive layer provided between the substrate and the through-electrodes.
於本發明之一實施形態的貫通電極基板中,前述第2配線亦可進一步與前述密接層接觸。In the through-electrode substrate according to one embodiment of the present invention, the second wiring may further be in contact with the adhesive layer.
於本發明之一實施形態的貫通電極基板中,前述密接層亦可含有有機樹脂材料。In the through-electrode substrate according to one embodiment of the present invention, the adhesion layer may contain an organic resin material.
本發明之一實施形態的貫通電極基板,亦可進一步具有: 設置於前述第1配線、前述第2配線及前述貫通電極上之絕緣層; 設置於前述絕緣層上之第3配線;及 與前述絕緣層、前述第3配線及前述貫通電極接觸之第4配線。The through-electrode substrate according to an embodiment of the present invention may further include: an insulating layer provided on the first wiring, the second wiring, and the through-electrode; a third wiring provided on the aforementioned insulating layer; and A fourth wiring in contact with the insulating layer, the third wiring, and the through-electrode.
於本發明之一實施形態的貫通電極基板中,前述絕緣層亦可由有機樹脂材料構成,前述貫通電極可設置於前述貫通孔之內壁及設於前述絕緣層之開口部的內側。In the through-electrode substrate according to an embodiment of the present invention, the insulating layer may be made of an organic resin material, and the through-electrode may be provided on the inner wall of the through-hole and inside the opening of the insulating layer.
於本發明之一實施形態的貫通電極基板中,前述貫通電極亦可含有: 設置於前述貫通孔之內壁的第1貫通電極;及 設置於設在前述絕緣層之前述開口部之內側的第2貫通電極。In the through-electrode substrate according to an embodiment of the present invention, the above-mentioned through-electrode may also contain: a first through electrode provided on the inner wall of the through hole; and The second penetrating electrode provided inside the opening provided in the insulating layer.
本發明之一實施形態的貫通電極基板其前述貫通孔之長寬比亦可為3以上。 [發明之效果]In the through-electrode substrate according to an embodiment of the present invention, the aspect ratio of the through-holes may be 3 or more. [Effect of Invention]
若根據本發明,則可提供一種貫通電極基板及其製造方法,該貫通電極基板為使用玻璃基板之高長寬比的貫通電極基板,可確保貫通電極與基板上之配線的導通,電可靠性獲得提升。According to the present invention, it is possible to provide a through-electrode substrate and a manufacturing method thereof. The through-electrode substrate is a through-electrode substrate with a high aspect ratio using a glass substrate, which ensures conduction between the through-electrodes and wiring on the substrate, and improves electrical reliability. .
以下,一邊參照圖式等,一邊說明本發明之各實施形態。惟,本發明於不脫離其要旨之範圍內,可用各種各樣之態樣加以實施,並不限定於以下例示之實施形態的記載內容作解釋。Hereinafter, various embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in various forms within a range not departing from the gist thereof, and should not be construed as limited to the descriptions of the following exemplary embodiments.
圖式有時會為了使說明更加明確,而相較於實際之態樣,示意地表示各部分之寬度、厚度、形狀等,但其僅為一例示,並不限定本發明之解釋。於本說明書及各圖式中,對於具備與已揭示之圖所說明者相同功能的元件,有時會賦予相同符號,並省略重複之說明。In order to clarify the description, the drawings sometimes schematically show the width, thickness, shape, etc. of each part compared with the actual form, but these are just examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described in the already disclosed figures may be assigned the same symbols and redundant descriptions will be omitted.
於本說明書及申請專利範圍中,當表現將另外之構造體配置於某構造體上的態樣時,在僅記述為「於...上」之情形時,只要沒有特別說明,係包含「以與某構造體接觸之方式將另外之構造體配置於正上方的情形」與「進一步透過不同之構造體將另外之構造體配置於某構造體上方的情形」此兩種情形。又,於本說明書及申請專利範圍中,「U」及其箭頭在剖面中表示上或上方,而「D」及其箭頭則在剖面中表示下或下方。In this specification and the scope of the patent application, when expressing the aspect of disposing another structure on a certain structure, when it is only described as "on", unless otherwise specified, it includes " There are two cases of placing another structure directly above a certain structure in such a way as to be in contact with a certain structure" and "the case of further placing another structure above a certain structure through a different structure". Also, in this specification and the scope of the patent application, "U" and its arrow indicate up or above in section, while "D" and its arrow indicate down or below in section.
於本說明書及申請專利範圍中,某構造體與另外之構造體「重疊」此一表現,意指於俯視此等之構造體時,至少一部分重疊。換言之,意指當此等構造體中之任一者位於另一者之上或者之下,且從上面或者下面觀看此等構造體的情形時,彼此至少一部分重疊。In this specification and the scope of the patent application, the expression that a certain structure "overlaps" another structure means that at least a part of them overlaps when these structures are viewed from above. In other words, it means that when any one of these structures is positioned above or below the other, and these structures are viewed from above or below, at least a part of them overlaps with each other.
關於本發明第1實施形態之貫通電極基板100的構成及貫通電極基板100的製造方法,參照圖1至圖6加以說明。The configuration of the through-
[半導體裝置之構造]
將表示半導體裝置1000之一例的俯視圖揭示於圖1,該半導體裝置1000具有為本發明實施形態之一的貫通電極基板100。半導體裝置1000具有印刷基板200、貫通電極基板100、積體電路300、凸塊122及配線層120。[Structure of semiconductor device]
FIG. 1 shows a plan view showing an example of a
積體電路300亦可設置複數個於配線層120上,複數個積體電路300亦可透過配線層120彼此電連接。又,各積體電路300透過配線層120及凸塊122等導電體與貫通電極基板100電連接。貫通電極基板100透過後述之貫通電極108與印刷基板200電連接。Multiple integrated
於圖1,雖然揭示1個與配線層120電連接之積體電路300構裝於貫通電極基板100之例,但並不限定於此處所示之例。積體電路300之端子數可為4個,亦可為5個以上,又,亦可未達4個。又,構裝於貫通電極基板100之積體電路300的個數,可為複數個,亦可為1個。並且,構裝於貫通電極基板100之積體電路300,亦可構裝複數個端子數不同之積體電路。可根據半導體裝置1000之用途,適當加以選擇。另,於圖1,雖然揭示貫通電極基板100構裝於印刷基板200上之例示,但並不限定於此例示。構裝貫通電極基板100者,例如可在玻璃基板上,亦可在如FPC之類的撓性素材上。可根據半導體裝置之用途,適當加以選擇。In FIG. 1 , although an example in which one
[配線基板之構造1] 將本發明一實施形態之貫通電極基板的一例表示於圖2。圖2(A)為本發明一實施形態之貫通電極基板的俯視圖。圖2(B)則為圖2(A)所示之剖線的剖面圖。[Structure of wiring board 1] An example of a through-electrode substrate according to an embodiment of the present invention is shown in FIG. 2 . FIG. 2(A) is a plan view of a through-electrode substrate according to an embodiment of the present invention. Fig. 2(B) is a sectional view of the section line shown in Fig. 2(A).
將圖1所示之貫通電極基板100之部分俯視圖與部分剖面圖表示於圖2。貫通電極基板100具有玻璃基板102及設置於貫通孔10之內壁的貫通電極108,該玻璃基板102具有第1面102a、第2面102b、貫通第1面102a與第2面102b之貫通孔10。又,於圖2中,雖然省略一部分,但是於第1面102a上,亦可設置如圖1所示之配線層120之類的多層配線層。圖2所示之第1配線104為構成圖1所示之配線層120的一部分者。FIG. 2 shows a partial plan view and a partial cross-sectional view of the through-
配線層120及凸塊122與貫通電極108電連接。貫通電極108則與凸塊122電連接。積體電路300透過凸塊122與配線層120電連接。貫通電極基板100透過凸塊122與印刷基板200電連接。另,第1面102a與第2面102b相對於貫通電極基板100,為上與下,或表面與背面之關係。The
如圖2所示,貫通電極基板100具有「玻璃基板102」、「從玻璃基板102之第1面102a貫通第2面102b的貫通孔10」、「形成於玻璃基板102之第1面102a上的第1配線104」與「設置於貫通孔10之內壁的密接層106及形成於密接層106上之貫通電極108」,於玻璃基板102之第1面102a上,具有電連接貫通電極108與第1配線104之第2配線110。As shown in FIG. 2 , the through-
於本實施例,雖然揭示使用以玻璃材料構成之玻璃基板102作為基板的例子,但是本發明並不限定於此,亦可使用以含有矽之材料構成的矽基板、以含有氧化鋁之材料構成的陶瓷基板。In this embodiment, although an example of using a
玻璃基板102具有第1面102a及第2面102b作為2個主面,於至少第1面102a上形成有第1配線104。第1配線104例如可為構成TFT(thin film transistor,薄膜電晶體)者。The
於本實施例中,第1配線104雖然僅形成於第1面102a上,但是本發明並不限定於此,亦可於玻璃基板102之第1面102a及第2面102b的兩面形成有配線。第1配線104之材料例如可為銅等。In this embodiment, although the
玻璃基板102之板厚,例如可為200μm~900μm左右。The thickness of the
於玻璃基板102之貫通孔10內的側壁,形成有「密接層106」及「形成於密接層106上之貫通電極108」。密接層106係作為用以藉由無電電鍍將貫通電極108之材料形成於玻璃基板102上的基底發揮功能。密接層106可用含有有機樹脂之材料形成。構成密接層106之含有有機樹脂的材料,例如可為環氧樹脂、丙烯酸樹脂、聚醯亞胺樹脂、胺酯樹脂(urethane resin)等。藉由形成密接層106,相較於玻璃表面,可更加導入觸媒吸附性優異之官能基,可成膜密接性良好之銅或鎳等無電電鍍。On the sidewall of the through-
貫通電極108形成於玻璃基板102之表面中形成有密接層106之部分。貫通電極108由於係為了得到玻璃基板102上下之導通而形成,故形成為覆蓋玻璃基板102之貫通孔10內的側壁全部,沿著貫通孔10之內壁形成為中空之圓柱狀。有時將貫通電極108之中空部分稱為穿孔(through hole)130。又,貫通電極108為了與上下之配線電連接,亦可於玻璃基板102之第1面102a或第2面102b上之穿孔130的周緣部具有連接盤(land)108-1(較穿孔直徑大之「承受(連接盤)部分)。貫通電極108之材料例如可為銅或鎳。The penetrating
如圖2所示,貫通孔10及穿孔130可為具有相同中心軸之同心圓。貫通孔10之孔徑例如可為40μm~140μm左右,穿孔130之孔徑例如可為30μm~135μm左右。於圖2所示之配線基板,貫通孔10之孔徑大於穿孔130之孔徑。As shown in FIG. 2 , the through
雖然於圖2揭示中空之穿孔130,但是穿孔130之內部亦可經用與貫通電極108相同之鍍覆填充,又,亦可經用有機樹脂或與貫通電極108不同之金屬填充。Although the hollow through-
於玻璃基板102之第1面102a上,形成有和玻璃基板102與第1配線104與貫通電極108接觸之第2配線110。第2配線110具有作為交聯配線之功能,該交聯配線係將第1配線104與貫通電極108於第1面102a上之連接盤108-1電連接。第2配線110之材料若為銅或鎳、錫等具有導電性之材料,則可為任何材料。On the
第2配線110如圖2所示,可為單層,但是本發明並不限定於此。例如,當第2配線110之材料為銅的情形時,亦可為下述之多層構造:為了提升銅與玻璃基板102之密接性,而於銅與玻璃基板102之間含有1層以上由Ti等低電阻之金屬膜構成的密接層。The
圖10為本發明一實施形態之貫通電極基板的剖面圖。圖10所示之第2配線110'具有2層構造,該2層構造係形成於玻璃基板102上由Ti等低電阻之金屬模構成的密接層110-1與形成於密接層110-1上由銅等具有導電性之材料構成的第2配線部分110-2積層而成。若根據圖10所示之構成,則可提升第2配線110'之第2配線部分110-2與玻璃基板102的密接性。又,雖然未圖示,但圖10所示之第2配線110'之密接層110-1亦可為2層以上由低電阻金屬膜構成之多層構造。10 is a cross-sectional view of a through-electrode substrate according to an embodiment of the present invention. The second wiring 110' shown in FIG. 10 has a two-layer structure. The two-layer structure is an adhesive layer 110-1 formed of a low-resistance metal mold such as Ti formed on the
又,第2配線110若為可將分開形成於玻璃基板102之一主面上的第1配線104與貫通電極108交聯加以電連接的配線,則何者皆可。例如,第2配線110可為將第1配線104與貫通電極108電連接之打線(wire bonding),又,亦可為將第1配線104與貫通電極108電連接之焊料。第2配線110之材料,例如可為鎳、金、錫、銅、鋁、鈦、鉻、ITO等金屬氧化物等。In addition, the
如圖2所示,對一個貫通電極108,可以拉出於不同方向之方式連接複數條第2配線110。然而,本發明並不限定於此。圖11為本發明之一實施形態的貫通電極基板俯視圖。如圖11所示,亦可僅對一個貫通電極108連接一條第2配線110而電連接於第1配線104。As shown in FIG. 2 , a plurality of
第1配線104、第2配線110及貫通電極108係以具有導電性之材料形成。例如,可使用金、銀、銅、鉑、鎳、銠、釕或銥等。第1配線104、第2配線110及葉通電極108亦可使用相同材料,亦可組合不同材料來使用。藉由以相同材料來形成第1配線104、第2配線110及貫通電極108,可提升特性阻抗匹配。The
於本實施形態中,由於貫通電極108與第1配線104係藉由第2配線110電連接,故可確保貫通電極108與玻璃基板102上之第1配線104的導通,提升電可靠性。In this embodiment, since the through-
[配線基板之構造1的變形例]
於圖2所示之例中,第2配線110雖然直接連接於貫通電極108之第1面102a上的連接盤108-1,但本發明並不限定於此。圖9為表示圖2所示之本發明一實施形態之貫通電極基板的變形例之圖。圖9(A)為本發明一實施形態之貫通電極基板的俯視圖。圖9(B)為圖9(A)所示之剖線的剖面圖。[Modification of
如圖9所示,貫通電極108亦可具有從形成於第1面102a上之連接盤108-1延長的配線部分108-2。於此情形時,第2配線110亦可直接連接於從形成於貫通電極108之第1面102a上之連接盤108-1延長的配線部分108-2。As shown in FIG. 9 , the
[配線基板之製造方法1]
關於圖2所示之本發明第1實施形態之貫通電極基板100的製造方法,參照圖2至圖6加以說明。另,於圖3至圖6中,對於與圖1至圖2相同之構成,賦予相同符號來說明。[Manufacturing method of wiring board 1]
A method of manufacturing through
首先,於玻璃基板102上,形成第1配線104(參照圖3)。第1配線104可為構成TFT等元件者。於圖3中,雖然於玻璃基板102之第1面102a上形成有第1配線104,但是並不限定於此,不僅第1面102a,亦可於第2面102b形成第1配線104。First, the
接著,於單面或兩面形成有第1配線104之玻璃基板102,形成貫通第1面102a與第2面102b之貫通孔10(參照圖4)。貫通孔10形成於玻璃基板102之位置,為未形成有第1配線104之部分。貫通孔10形成於與第1配線104分離之位置。貫通孔10之形狀可為上下之孔徑大致一定的圓筒狀。Next, the through
於玻璃基板102形成貫通孔10之方法,可為任意之方法。The method of forming the through
接著,在形成於玻璃基板102之貫通孔10的內壁及第1面102a、第2面102b上之貫通孔的周緣部,形成密接層106(參照圖5)。密接層106例如可藉由旋塗、浸塗、噴霧塗布(spray coating)等方法形成。密接層106係於之後作為用以使貫通電極材料成膜的密接層發揮功能。密接層106可用含有有機樹脂之材料形成。Next, an
接著,於玻璃基板102之表面中形成有密接層106之部分,形成貫通電極108(參照圖6)。貫通電極108形成於形成在玻璃基板102表面之密接層106上。貫通電極108係使用無電電鍍法使銅或鎳等形成為被膜而成。Next, on the surface of the
此處,當製造圖9所示之配線基板之構造1的變形例之情形時,從貫通電極108形成於第1面102a上之連接盤108-1延長的配線部分108-2,亦可與貫通電極108同時在上述步驟形成。具體而言,係於玻璃基板102之表面中形成有密接層106的部分,形成包含連接盤108-1及從連接盤108-1延長之配線部分108-2的貫通電極108(參照圖9)。貫通電極108係形成於形成在玻璃基板102表面之密接層106上。貫通電極108係使用無電電鍍法使銅或鎳等形成為被膜而成。Here, when manufacturing the modified example of the
於本發明中,藉由將密接層106使用作為密接層或還原劑,而可用無電電鍍法等將貫通電極材料成膜於形成在玻璃基板102上之貫通孔10內。In the present invention, by using the
亦有與本發明不同之方法,亦即,不形成密接層106,藉由濺鍍法將銅等貫通電極材料成膜在形成於玻璃基板102上之貫通孔10內。There is also a method different from the present invention, that is, without forming the
若為玻璃基板之貫通孔之長寬比低的情形時(例如,板厚薄的情形或孔徑大的情形),則即使是使用藉由濺鍍法將銅等電極材料成膜於貫通孔內之方法的情形,亦能夠形成貫通電極。In the case where the aspect ratio of the through hole of the glass substrate is low (for example, when the thickness of the plate is thin or the hole diameter is large), even if an electrode material such as copper is formed into a film in the through hole by sputtering In the case of the method, it is also possible to form a through-hole electrode.
所謂長寬比,係指板厚/孔徑之值,「玻璃基板102之板厚」與「玻璃基板102之貫通孔之孔徑」的關係,係以玻璃基板之貫通孔的長寬比來表現。例如當板厚厚之情形時或孔徑小之情形時,長寬比會變高,而當板厚薄之情形時或孔徑大之情形時,長寬比則會變小。The so-called aspect ratio refers to the value of plate thickness/aperture diameter, and the relationship between "thickness of
然而,當玻璃基板之貫通孔之長寬比高的情形時(例如,板厚厚之情形或孔徑小之情形),由於以濺鍍法無法充分將電極材料成膜至遠離玻璃基板主面之貫通孔的內部,故會變得容易發生貫通孔內部未形成有電極材料之空白部分(空孔(void)或空心洞),而在電可靠性具有問題。例如,當玻璃基板之貫通孔之長寬比為3以上的情形時,使用濺鍍法的話,則容易於貫通孔內發生空孔或空心洞,而在電可靠性上產生問題。However, when the aspect ratio of the through hole of the glass substrate is high (for example, the case of a thick plate or the case of a small hole diameter), the electrode material cannot be sufficiently formed into a film far from the main surface of the glass substrate by the sputtering method. Therefore, a blank portion (void or hollow) in which no electrode material is formed inside the through hole is likely to occur inside the through hole, which poses a problem in electrical reliability. For example, when the aspect ratio of the through-hole of the glass substrate is 3 or more, if the sputtering method is used, voids or hollow holes are likely to occur in the through-hole, which causes problems in electrical reliability.
於本發明中,藉由將密接層106使用作為密接層或還原劑,即使是形成於玻璃基板102之貫通孔10之長寬比高的情形時,亦可藉由無電電鍍法等充分地將貫通電極材料成膜於貫通孔10內。因此,本發明尤其是對於形成在玻璃基板102之貫通孔10之長寬比為3以上的高密度配置之配線基板,可更加提升電可靠性,於此點上是有用的。In the present invention, by using the
接著,為了將形成於玻璃基板102上之第1配線104與形成於和第1配線104分離之位置的貫通電極108電連接,而形成與第1配線104與玻璃基板102與貫通電極108接觸之第2配線110(參照圖2)。於圖2中,第2配線110雖是藉由濺鍍法等形成為與玻璃基板之第1面102a接觸的配線,但本發明並不限定於此。Next, in order to electrically connect the
如上述,為了對玻璃基板102進行無電鍍銅形成貫通電極108,而必須將密接層106作為密接層形成於玻璃基板102。又,若僅是透過密接層106形成貫通電極108,則會無法得到預先形成於玻璃基板102上之第1配線104等配線層與貫通電極108的導通。因此,本發明為了得到預先形成於玻璃基板102上之第1配線104等配線層與透過密接層106形成之貫通電極108的導通,而具備第2配線110作為交聯配線。As described above, in order to perform electroless copper plating on the
於本發明中,由於第2配線110以交聯配線之形態電連接分離形成於玻璃基板102之一主面上的第1配線104與貫通電極108,故可確保貫通電極108與第1配線104之導通,能夠提供一種電可靠性經提升之貫通電極基板。In the present invention, since the
又,如圖2所示,第2配線110亦可為藉由濺鍍法等形成為與玻璃基板之第1面102a接觸的配線。於此情形時,第2配線110配置成直接接觸於玻璃基板102之一主面(未絕緣分離),將直接接觸於同一面之第1配線104與貫通電極108(惟,於貫通電極108與玻璃基板102之間隔著密接層106。)交聯。具體而言,於圖2中,直接接觸於玻璃基板之第1面102a的第1配線104與貫通電極108於第1面102a上之連接盤108-1,係藉由直接接觸於玻璃基板之第1面102a的第2配線110電連接。Moreover, as shown in FIG. 2, the
若根據圖2所示之第2配線110的構造,則由於直接接觸於玻璃基板之第1面102a的第1配線104與貫通電極108之連接盤108-1藉由直接接觸於玻璃基板之第1面102a的第2配線110電連接,故可提高與形成有第1配線104或貫通電極108之連接盤108-1等的玻璃基板第1面102a直接接觸之層內的配線密度。以此方式若與玻璃基板第1面102a直接接觸之層內的配線密度提高,則相應地對其他層形成配線會變得容易,配線之設計自由度會變高。According to the structure of the
又,第1配線104與貫通電極108之連接盤108-1由於在與玻璃基板第1面102a直接接觸之相同層內連接,故可縮短第2配線110之配線長度,因此,電阻低,可穩定地通電。又,第2配線110由於直接接觸於與第1配線104或貫通電極108之連接盤108-1相同之面,故可使配線層低背化。並且,當透過絕緣層將其他之配線積層於該配線層上的情形時,可確保下層配線層之平坦性。In addition, since the
又,第1配線104、貫通電極108之連接盤108-1及第2配線110皆是以相同之玻璃基板的第1面102a作為基底而形成,故由玻璃基板第1面102a之熱膨脹所產生之應力由於會均勻地作用在第1配線104、貫通電極108及第2配線110各者,因此,不易發生配線之扭曲、斷線,連接可靠性變高。In addition, since the
[配線基板之構造2] 作為配線基板之構成2,參照圖7及圖8,說明本發明另一實施形態之貫通電極基板。另,對於與圖1及圖2相同之構成,賦予相同符號加以說明。[Structure of Wiring Board 2] As the configuration 2 of the wiring board, a through-electrode board according to another embodiment of the present invention will be described with reference to FIGS. 7 and 8 . In addition, the same code|symbol is attached|subjected to the same structure as FIG. 1 and FIG. 2, and it demonstrates.
圖7所示之貫通電極基板100',含有構成圖2所示之貫通電極基板100的玻璃基板102、第1貫通電極108a、第1配線104及第2配線110。圖7所示之貫通電極基板100'進一步具有絕緣層112,於絕緣層112上,具有構成第1配線104上層之配線層的第3配線114。絕緣層112於第1貫通電極108a上具有開口部20,於開口部20之內壁形成第2貫通電極108b。第2貫通電極108b與第3配線114具有藉由絕緣層112上之第4配線116交聯的構成。Penetrating electrode substrate 100' shown in FIG. 7 includes
絕緣層112設置成被覆玻璃基板102之第1面102a上的第1配線104、第2配線110、第1貫通電極108之上。絕緣層112為由有機樹脂材料構成之絕緣層,係作為用以將由第3配線層114構成之另外的配線層積層於由第1配線104構成之配線層上的層間絕緣膜發揮功能。The insulating
絕緣層112於與形成有第1貫通電極108a之貫通孔10重畳的位置具有開口部20,於絕緣層112之開口部20的內壁,形成有第2貫通電極108b。The insulating
第2貫通電極108b由於形成在以有機樹脂材料構成之絕緣層112的開口部20,故與第1貫通電極108a不同,而無需使密接層居於其間。因此,第2貫通電極108b可藉由無電鍍銅等方法直接形成於絕緣層112之表面。Since the second
第2貫通電極108b將形成於上層之第3配線114與第1貫通電極108a電連接,係用以在形成於玻璃基板102第1面102a上之第3配線114與形成在第2面102b上之其他配線等之間得到上下之導通。The second through
第2貫通電極108b與第3配線形成於絕緣層112上之分離的位置,第4配線116於絕緣層112上將第2貫通電極108b與第3配線交聯而於該層電連接。The second
於圖7所示之貫通電極基板100',具有下述構成:於玻璃基板102之第1面102a上,積層有含有第1配線104之配線層與含有第3配線之配線層,於含有第1配線104之配線層中,與玻璃基板102第1面102a直接接觸之第1貫通電極108a與第1配線104藉由與玻璃基板102第1面102a直接接觸之第2配線110在該層交聯。並且,於含有第3配線114之配線層中具有下述構成:與絕緣層112之上面直接接觸的第2貫通電極108b與第3配線114藉由與絕緣層112之上面直接接觸的第4配線116在該層交聯。其他之構成則與圖1及圖2所示之貫通電極基板100相同。Penetrating electrode substrate 100' shown in FIG. 7 has a structure in which a wiring layer including
於圖7,雖然在玻璃基板102之第1面102a上,積層有含有第1配線104之配線層與含有第3配線之配線層此2層,但是本發明並不限定於此,亦可積層3層以上之配線層。In FIG. 7, although two layers of a wiring layer including the
又,如圖7所示,貫通電極基板100'亦可進一步具備將第3配線114與形成於玻璃基板102第2面102b上之其他配線等上下導通的第3貫通電極108c。如圖7所示,於第3貫通電極108c與玻璃基板102之間,亦可形成有絕緣層112。作為絕緣層112之製造方法,例如可藉由使用輥塗機(roller coater)將絕緣性液狀阻劑膜(resist film)塗布於玻璃基板102表面之方法來形成絕緣層112。另外,亦可使用浸漬塗布機(dip coater)或噴霧塗佈機(spray coater)來形成絕緣層112。Furthermore, as shown in FIG. 7 , the through
圖8為圖7所示之貫通電極基板的俯視圖。於圖8中,係用實線表示最上面之配線或貫通電極,位於下層之配線或貫通電極則以透視圖之形態用虛線表示。如圖7及圖8所示,複數個第1貫通電極108a係於含有第1配線104之配線層彼此連接,第2貫通電極108b則於第1配線104之上層亦即含有第3配線114之配線層與為其他貫通電極之第3貫通電極108c連接。FIG. 8 is a top view of the through-electrode substrate shown in FIG. 7 . In FIG. 8 , the uppermost wiring or through-electrode is shown by a solid line, and the wiring or through-electrode located on the lower layer is shown by a dotted line in a perspective view. As shown in FIG. 7 and FIG. 8, a plurality of first through-
於本發明中,由於第4配線116將分離形成於絕緣層112上之第3配線114與第2貫通電極108b在該層交聯連接,故可確保第2貫通電極108b與第3配線114之導通,可提供電可靠性經提升之貫通電極基板100'。In the present invention, since the
如圖7及圖8所示,第2貫通電線108b於中空部分之穿孔130b的周緣部形成有連接盤108b-1,此連接盤係作為將其他配線與貫通電極電連接之連接部分發揮功能。又,第1貫通電極108a及第3貫通電極108c亦可與第2貫通電極108b同樣地於穿孔之周緣部具有連接盤。As shown in FIGS. 7 and 8 , a
若根據圖7及圖8所示之具有複數層配線層的貫通電極基板100',則可確保電可靠性,且同時藉由積層配線層,而可更加提升配線密度。According to the through-
上述作為本發明之實施形態的各實施形態,只要沒有互相矛盾,則可適當加以組合來實施。又,基於各實施形態,該行業者進行適當構成元件之追加、刪除或者設計變更而成者,只要具備有本發明之要旨,則包含於本發明之範圍內。The above-mentioned respective embodiments which are embodiments of the present invention can be implemented in combination as appropriate unless they contradict each other. Moreover, based on each embodiment, the addition, deletion, or design change of the appropriate constituent elements by the industry is included in the scope of the present invention as long as it has the gist of the present invention.
又,即使為與藉由上述各實施形態所達成之作用效果不同的其他作用效果,但只要是從本說明書之記載可清楚得知者或該行業者可輕易預期者,當然亦理解為是藉由本發明所達成者。Also, even if it is other effects different from the effects achieved by the above-mentioned embodiments, as long as they are clearly known from the description in this specification or can be easily expected by those in the industry, it is of course understood that they are achieved by means of Achieved by the present invention.
10‧‧‧貫通孔
20‧‧‧開口部
100、100'‧‧‧貫通電極基板
102‧‧‧玻璃基板
102a‧‧‧第1面
102b‧‧‧第2面
104‧‧‧第1配線
106、110-1‧‧‧密接層
108、108a、108b‧‧‧貫通電極
108c‧‧‧第3貫通電極
108-1、108b-1‧‧‧連接盤
108-2‧‧‧配線部分
110‧‧‧第2配線
110-2‧‧‧第2配線部分
112‧‧‧絕緣層
114‧‧‧第3配線
116‧‧‧第4配線
120‧‧‧配線層
122‧‧‧凸塊
130、130b‧‧‧穿孔
200‧‧‧印刷基板
300‧‧‧積體電路
1000‧‧‧半導體裝置
10‧‧‧through
圖1為使用本發明之一實施形態的貫通電極基板的半導體裝置之剖面圖。 圖2:圖2(A)為本發明之一實施形態的貫通電極基板的俯視圖。圖2(B)為圖2(A)所示之剖線的剖面圖。 圖3為說明本發明之一實施形態的貫通電極基板製造方法的剖面圖。 圖4為說明本發明之一實施形態的貫通電極基板製造方法的剖面圖。 圖5為說明本發明之一實施形態的貫通電極基板製造方法的剖面圖。 圖6為說明本發明之一實施形態的貫通電極基板製造方法的剖面圖。 圖7為本發明另一實施形態的貫通電極基板之剖面圖。 圖8為圖7所示之貫通電極基板的俯視圖。 圖9:圖9(A)為本發明之一實施形態的貫通電極基板的俯視圖。圖9(B)為圖9(A)所示之剖線的剖面圖。 圖10為本發明之一實施形態的貫通電極基板的剖面圖。 圖11為本發明之一實施形態的貫通電極基板的俯視圖。FIG. 1 is a cross-sectional view of a semiconductor device using a through-electrode substrate according to an embodiment of the present invention. FIG. 2: FIG. 2(A) is a top view of a through-electrode substrate according to an embodiment of the present invention. Fig. 2(B) is a sectional view along the line shown in Fig. 2(A). 3 is a cross-sectional view illustrating a method of manufacturing a through-electrode substrate according to an embodiment of the present invention. 4 is a cross-sectional view illustrating a method of manufacturing a through-electrode substrate according to an embodiment of the present invention. 5 is a cross-sectional view illustrating a method of manufacturing a through-electrode substrate according to an embodiment of the present invention. 6 is a cross-sectional view illustrating a method of manufacturing a through-electrode substrate according to an embodiment of the present invention. 7 is a cross-sectional view of a through-electrode substrate according to another embodiment of the present invention. FIG. 8 is a top view of the through-electrode substrate shown in FIG. 7 . FIG. 9 : FIG. 9(A) is a plan view of a through-electrode substrate according to an embodiment of the present invention. Fig. 9(B) is a sectional view along the line shown in Fig. 9(A). 10 is a cross-sectional view of a through-electrode substrate according to an embodiment of the present invention. 11 is a plan view of a through-electrode substrate according to an embodiment of the present invention.
10‧‧‧貫通孔 10‧‧‧through hole
100‧‧‧貫通電極基板 100‧‧‧through electrode substrate
102‧‧‧玻璃基板 102‧‧‧Glass substrate
102a‧‧‧第1面
102a‧‧‧
102b‧‧‧第2面 102b‧‧‧Side 2
104‧‧‧第1配線 104‧‧‧1st wiring
106‧‧‧密接層 106‧‧‧adhesive layer
108‧‧‧貫通電極 108‧‧‧through electrode
108-1‧‧‧連接盤 108-1‧‧‧connection plate
110‧‧‧第2配線 110‧‧‧Second wiring
130‧‧‧穿孔 130‧‧‧perforation
Claims (6)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017190129 | 2017-09-29 | ||
| JPJP2017-190129 | 2017-09-29 |
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| TW201924505A TW201924505A (en) | 2019-06-16 |
| TWI782100B true TWI782100B (en) | 2022-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107133985A TWI782100B (en) | 2017-09-29 | 2018-09-27 | Through-electrode substrate and semiconductor device using through-electrode substrate |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP7180605B2 (en) |
| TW (1) | TWI782100B (en) |
| WO (1) | WO2019065656A1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080298023A1 (en) * | 2007-05-28 | 2008-12-04 | Matsushita Electric Industrial Co., Ltd. | Electronic component-containing module and manufacturing method thereof |
| US20090283311A1 (en) * | 2008-05-14 | 2009-11-19 | Sharp Kabushiki Kaisha | Electronic element wafer module and method for manufacturing electronic element wafer module, electronic element module, and electronic information device |
| TW201637143A (en) * | 2015-01-15 | 2016-10-16 | 凸版印刷股份有限公司 | Interposer, semiconductor device, and the like |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6017991A (en) * | 1983-07-12 | 1985-01-29 | 株式会社東芝 | Method of producing through hole substrate |
| JP5547566B2 (en) * | 2010-06-29 | 2014-07-16 | 株式会社アドバンテスト | Method for manufacturing through wiring board |
| US9466578B2 (en) * | 2013-12-20 | 2016-10-11 | Qualcomm Incorporated | Substrate comprising improved via pad placement in bump area |
| JP2015177382A (en) * | 2014-03-15 | 2015-10-05 | キヤノン株式会社 | Device with element electrode connected with through-wiring, and manufacturing method thereof |
-
2018
- 2018-09-25 JP JP2019545145A patent/JP7180605B2/en active Active
- 2018-09-25 WO PCT/JP2018/035524 patent/WO2019065656A1/en not_active Ceased
- 2018-09-27 TW TW107133985A patent/TWI782100B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080298023A1 (en) * | 2007-05-28 | 2008-12-04 | Matsushita Electric Industrial Co., Ltd. | Electronic component-containing module and manufacturing method thereof |
| US20090283311A1 (en) * | 2008-05-14 | 2009-11-19 | Sharp Kabushiki Kaisha | Electronic element wafer module and method for manufacturing electronic element wafer module, electronic element module, and electronic information device |
| TW201637143A (en) * | 2015-01-15 | 2016-10-16 | 凸版印刷股份有限公司 | Interposer, semiconductor device, and the like |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7180605B2 (en) | 2022-11-30 |
| WO2019065656A1 (en) | 2019-04-04 |
| TW201924505A (en) | 2019-06-16 |
| JPWO2019065656A1 (en) | 2020-11-19 |
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