TWI779425B - Gate structure of gallium nitride hemt - Google Patents

Abstract

A gate structure of gallium nitride HEMT including a doped gallium nitride layer, a gate metal layer and an undoped gallium nitride layer is provided. The gate metal layer is located on the doped gallium nitride layer. The doped gallium nitride layer has protrusions extending from sidewalls of the gate metal layer. The undoped gallium nitride layer is located between the gate metal layer and the doped gallium nitride layer.

Description

Gate Structure of Gallium Nitride High Electron Mobility Transistor

The present invention relates to a gallium nitride high electron mobility transistor, and in particular to a gate structure of a gallium nitride high electron mobility transistor.

Gallium nitride high electron mobility transistor (high electron mobility transistor, HEMT) is a heterogeneous structure using aluminum gallium nitride (AlGaN) and gallium nitride (GaN), which will produce high plane charge density and high Electron mobility two-dimensional electron gas (two dimensional electron gas, 2DEG), so suitable for high power, high frequency and high temperature operation. However, the gallium nitride high electron mobility transistor often has a gate leakage problem, which causes the switching performance of the transistor to decrease or fail under abnormal operation, thereby reducing the reliability.

The invention provides a gate structure of GaN high electron mobility transistor, which can effectively improve the problem of gate leakage and has better reliability.

A gate structure of a gallium nitride high electron mobility transistor according to the present invention comprises a doped gallium nitride layer, a gate metal layer and an undoped gallium nitride layer. A gate metal layer is on the doped gallium nitride layer. The doped gallium nitride layer has protrusions extending from sidewalls of the gate metal layer. The undoped GaN layer is located between the gate metal layer and the doped GaN layer.

In an embodiment of the present invention, the aforementioned gate metal layer penetrates the undoped GaN layer.

In an embodiment of the present invention, the bottom surface of the gate metal layer is coplanar with the bottom surface of the undoped GaN layer.

In an embodiment of the present invention, the above-mentioned gate metal layer and the undoped GaN layer are in direct contact with the doped GaN layer.

In an embodiment of the present invention, the above-mentioned gate structure further includes an insulating layer. The insulating layer is located between the gate metal layer and the undoped gallium nitride layer.

In an embodiment of the present invention, the sidewalls of the above-mentioned gate metal layer are aligned with the sidewalls of the insulating layer.

In an embodiment of the present invention, the above-mentioned gate structure further includes a spacer. The spacer is located on the protruding portion and at least covers the sidewall of the gate metal layer.

In an embodiment of the present invention, the width of the bottom surface of the spacer is equal to or smaller than the width of the top surface of the protrusion.

In an embodiment of the present invention, the above-mentioned undoped GaN layer includes a portion retracted in the gate metal layer.

In an embodiment of the present invention, the above-mentioned undoped GaN layer includes another portion extending onto the protruding portion.

Based on the above, with the protection of the undoped GaN layer and the increase of the path length of the leakage current through the protrusion, the gate structure of the GaN high electron mobility transistor of the present invention can effectively improve the gate structure. Extreme leakage problem, with better reliability.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

The following disclosure of this specification provides different embodiments or examples for implementing different features of various embodiments of the present invention. However, the following disclosures in this specification describe specific examples of each component and its arrangement in order to simplify the description. Of course, these specific examples are not intended to limit the present invention. In addition, different examples may use repeated reference symbols and/or words in the description of the present invention. These repeated symbols or words are used for the purpose of simplification and clarity, and are not used to limit the relationship between various embodiments and/or the appearance structure. Furthermore, if the following disclosure in this specification describes that the first feature is formed on or above the second feature, it means that it includes the embodiment in which the above-mentioned first feature and the above-mentioned second feature are formed in direct contact, Embodiments in which additional features can be formed between the above-mentioned first feature and the above-mentioned second feature, so that the above-mentioned first feature and the above-mentioned second feature may not be in direct contact are also included.

Please refer to FIG. 1, the gallium nitride high electron mobility transistor 100 of this embodiment may include a substrate 102, a channel layer 108, a barrier layer 110, and a gate structure G1, wherein the channel layer 108 may be located on the substrate 102, and the barrier Layer 110 may be on channel layer 108 , and gate structure G1 may be on barrier layer 110 . Here, the substrate 102 may include materials such as sapphire (Sapphire), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium oxide (Ga ₂ O ₃ ); the material of the channel layer 108 may include gallium nitride (GaN); and the material of the barrier layer 110 may include aluminum gallium nitride (Al _x Ga _1-x N, x=0.2˜1), but the present invention is not limited thereto.

In some embodiments, when there is a lattice mismatch problem between the substrate 102 and the channel layer 108, the first buffer layer 104 and the second buffer layer 106 can be selectively disposed between the substrate 102 and the channel layer 108, wherein The second buffer layer 106 is more lattice-matched to the channel layer 108 than the first buffer layer 104 . Here, the first buffer layer 104 is, for example, an aluminum nitride layer, and the second buffer layer 106 is, for example, multiple overlapping layers of aluminum gallium nitride (Al _x Ga _1-x N, x=0.2˜1) and gallium nitride. However, the present invention is not limited thereto. In an unillustrated embodiment, only the first buffer layer 104 or the second buffer layer 106 may be selectively disposed between the substrate 102 and the channel layer 108 .

In addition, the gate structure G1 of this embodiment may include a doped GaN layer 112 , an undoped GaN layer 114 and a gate metal layer 116 , wherein the doped GaN layer 112 may be located on the barrier layer 110 , the gate metal layer 116 may be located on the doped GaN layer 112 , and the undoped GaN layer 114 may be located between the gate metal layer 116 and the doped GaN layer 112 . Here, the doped GaN layer 112 can be N-type doped or P-type doped according to actual design requirements. Furthermore, the undoped GaN layer 114 can be used to protect the doped GaN layer 112 serving as the gate structure G1 to ensure that it is not affected by the gate metal layer 116 or subsequent source and drain processes, Furthermore, the reliability of the GaN high electron mobility transistor 100 can be improved.

In addition, the doped GaN layer 112 may also have a protruding portion 112p extending from the sidewall 116s of the gate metal layer 116. The design of the protruding portion 112p can increase the path length of the leakage current to more effectively improve the leakage current. The leakage problem of the gate structure G1, therefore, the GaN high electron mobility transistor 100 of this embodiment can more effectively improve the leakage problem of the gate structure G1, and has better reliability.

In some embodiments, the leakage current flows through the sidewall 116s of the gate metal layer 116, the sidewall 114s of the undoped GaN layer 114, and then flows through the protrusion 112p of the doped GaN layer 112, as shown by the arrow in FIG. 1 As shown in the path, the design of the protruding portion 112p can increase the path length of the leakage current, so as to improve the leakage problem of the gate structure G1 more effectively.

In some embodiments, the material of the gate metal layer 116 includes nickel, platinum, tantalum nitride, titanium nitride, tungsten, or an alloy of the aforementioned metals, but the present invention is not limited thereto, and the gate metal layer 116 can also be any suitable conductive material.

In some embodiments, the protrusion 112p of the doped GaN layer 112 is a ledge, and the gate metal layer 116 and the undoped GaN layer 114 protrude from the ledge, but the present invention Not limited to this.

In some embodiments, the gate metal layer 116 penetrates through the undoped GaN layer 114 to separate the undoped GaN layer 114 so that the undoped GaN layer 114 is only located on the gate metal Near the sidewall 116s of the layer 116, but the invention is not limited thereto.

In this embodiment, the undoped GaN layer 114 shrinks within the gate metal layer 116, and the sidewall 114s of the undoped GaN layer 114 is substantially aligned with the sidewall 116s of the gate metal layer 116. In other words, the undoped GaN layer 114 may be defined within the sidewall 116s of the gate metal layer 116, but the present invention is not limited thereto. In other embodiments, the undoped GaN layer may not be defined within Inside the sidewall 116s of the gate metal layer 116 .

In some embodiments, the bottom surface 116b of the gate metal layer 116 is coplanar with the bottom surface 114b of the undoped GaN layer 114, in other words, the bottom surface 116b of the gate metal layer 116 is coplanar with the undoped GaN layer 114 The bottom surface 114b of the can form an extended plane. In addition, the bottom surface 116b of the gate metal layer 116, the bottom surface 114b of the undoped GaN layer 114, and the top surface of the protrusion 112p are coplanar, in other words, the bottom surface 116b of the gate metal layer 116, the undoped GaN layer The bottom surface 114b of the gallium layer 114 and the top surface of the protruding portion 112p may form an extended plane, but the invention is not limited thereto.

In some embodiments, the gate metal layer 116 and the undoped GaN layer 114 directly contact the doped GaN layer 112 , but the invention is not limited thereto.

In some embodiments, the undoped GaN layer 114 is in direct contact with the gate metal layer 116, that is, there may be no other film layers between the undoped GaN layer 114 and the gate metal layer 116, But the present invention is not limited thereto. In other embodiments, other film layers may be selectively formed between the undoped GaN layer 114 and the gate metal layer 116 .

In this embodiment, the protruding portion 112p of the doped GaN layer 112 may be exposed, but the present invention is not limited thereto. In other embodiments, the protruding portion 112p of the doped GaN layer 112 may also be exposed by other component covered.

In this embodiment, the doped GaN layer 112 is trapezoidal in cross-section, so the sidewall 112s of the doped GaN layer 112 and the top surface 110a of the barrier layer 110 may have an obtuse angle, but this The invention is not limited thereto. In other embodiments, the doped GaN layer 112 may have other shapes in cross-sectional view, and the sidewall 112s of the doped GaN layer 112 and the top surface 110a of the barrier layer 110 The included angle can have other different angles.

The GaN high electron mobility transistor 100 of this embodiment includes a substrate 102 , a channel layer 108 , a barrier layer 110 and a gate structure G1 . The channel layer 108 is located on the substrate 102 . The barrier layer 110 is on the channel layer 108 . The gate structure G1 is located on the barrier layer 110 . The gate structure G1 includes a doped GaN layer 112 , a gate metal layer 116 and an undoped GaN layer 114 . The doped GaN layer 112 is on the barrier layer 110 . The gate metal layer 116 is on the doped GaN layer 112 . The doped GaN layer 112 has a protrusion 112p extending from a sidewall 116s of the gate metal layer 116 . The undoped GaN layer 114 is located between the gate metal layer 116 and the doped GaN layer 112 . Therefore, through the protection of the undoped GaN layer 114 and the increase of the path length of the leakage current through the protrusion 112p, the GaN high electron mobility transistor 100 of this embodiment can effectively improve the gate electrode. The structure G1 leakage problem has better reliability.

It must be noted here that the following embodiments continue to use the component numbers and part of the content of the above-mentioned embodiments, wherein the same or similar numbers are used to indicate the same or similar components, and the description of the same technical content is omitted, and the description of the omitted part Reference can be made to the aforementioned embodiments, and the following embodiments will not be repeated.

Please refer to FIG. 2 , the gallium nitride high electron mobility transistor 200 is similar to the gallium nitride high electron mobility transistor 100 in FIG. 1 , the difference lies in: the gate of the gallium nitride high electron mobility transistor 200 The structure G2 further includes an insulating layer 218, wherein the insulating layer 218 is located between the gate metal layer 116 and the undoped GaN layer 114 to block the leakage current at the side of the gate structure G2 and further reduce the leakage current of the gate structure G2. problems, but the present invention is not limited thereto.

In this embodiment, the sidewalls 116 s of the gate metal layer 116 and the sidewalls 218 s of the insulating layer 218 may be substantially aligned. In other words, the insulating layer 218 may be defined within the sidewalls 116 s of the gate metal layer 116 . In addition, the sidewall 116s of the gate metal layer 116 and the sidewall 218s of the insulating layer 218 can also be substantially aligned with the sidewall 114s of the undoped GaN layer 114, but the present invention is not limited thereto. In other embodiments, it can Only the sidewall 116s of the gate metal layer 116 is substantially aligned with the sidewall 218s of the insulating layer 218, while the sidewall 114s of the undoped GaN layer 114 is not aligned with the sidewall 116s of the gate metal layer 116 and the sidewall 218s of the insulating layer 218. Qie Qi.

In some embodiments, the insulating layer 218 is made of silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), boron nitride (BN) or aluminum nitride (AlN ), but the present invention is not limited thereto, and the insulating layer 218 may be any suitable insulating material.

Please refer to FIG. 3 , the gallium nitride high electron mobility transistor 300 is similar to the gallium nitride high electron mobility transistor 100 in FIG. 1 , the difference lies in: the gate of the gallium nitride high electron mobility transistor 300 The structure G3 further includes a spacer 320, wherein the spacer 320 is located on the protruding portion 112p and covers at least the sidewall 116s of the gate metal layer 116, so that the spacer 320 can protect the sidewall 116s of the gate metal layer 116 during the manufacturing process and reduce impurities The possibility of attaching to the sidewall 116s of the gate metal layer 116 further reduces the leakage problem of the gate structure G3, but the invention is not limited thereto.

In this embodiment, the width of the bottom surface of the spacer 320 is equal to the width of the top surface of the protrusion 112p, that is, the spacer 320 can completely cover the originally exposed space on the protrusion 112p, but the invention is not limited thereto. In addition, the gate structure G3 of the GaN high electron mobility transistor 300 may further include a cap layer 322 , wherein the cap layer 322 is located on the gate metal layer 116 and connected to the spacer 320 .

In some embodiments, the material of the spacer 320 is, for example, silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), and the material of the cap layer 322 is, for example, silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ), but the present invention is not limited thereto, and the material of the spacer 320 and the top cover layer 322 can be any suitable insulating material.

Please refer to FIG. 4 , the gallium nitride high electron mobility transistor 400 is similar to the gallium nitride high electron mobility transistor 300 in FIG. 3 , the difference lies in: the gate of the gallium nitride high electron mobility transistor 400 The top of the gate metal layer 416 of the structure G4 further includes a recess 416 a. Here, the recess portion 416a may be formed along with the formation of the gate metal layer 416, but the invention is not limited thereto.

In some embodiments, the spacer 420 and the top cap layer 422 of the gate structure G4 of the electron mobility transistor 400 may be disposed at different positions corresponding to the recessed portion 416 a. As shown in FIG. 4, a part of the spacer 420 can cover the sidewall 416s of the gate metal layer 416 and the sidewall 422s of the top layer 422, and another part of the spacer 420 can be embedded in the top layer 422, wherein the top layer 422 can be is conformally formed on the concave portion 416a, but the invention is not limited thereto.

On the other hand, the gate structure G4 of the GaN high electron mobility transistor 400 may also include the insulating layer 218 , wherein the insulating layer 218 may be covered by the spacer 420 , but the invention is not limited thereto.

Please refer to FIG. 5 , the gallium nitride high electron mobility transistor 500 is similar to the gallium nitride high electron mobility transistor 100 in FIG. 1 , the difference lies in: the gate of the gallium nitride high electron mobility transistor 500 The undoped GaN layer 514 of the structure G5 includes another portion extending onto the protrusion 112p. In other words, the undoped GaN layer 514 can cover the exposed space on the protrusion 112p in FIG. 5, But the present invention is not limited thereto.

In some embodiments, the sidewalls of the undoped GaN layer 514 and the sidewalls of the protruding portion 112p may be continuous sidewalls, but the invention is not limited thereto.

Please refer to FIG. 6, the GaN high electron mobility transistor 600 is similar to the GaN high electron mobility transistor 400 in FIG. The width of the bottom surface of the wall 620 is smaller than the width of the top surface of the protruding portion 112p, and the undoped GaN layer 514 includes another portion extending onto the protruding portion 112p. Furthermore, since the undoped GaN layer 514 and the protruding portion 112p present a trapezoidal profile, when part of the undoped GaN layer 514 is sandwiched between the protruding portion 112p and the spacer 620, the spacer will be further reduced. 620 of formation space.

Please refer to FIG. 7, the GaN high electron mobility transistor 700 is similar to the GaN high electron mobility transistor 100 in FIG. The doped gallium nitride layer 712 of the gate structure G7 of the crystal 700 is rectangular, so the sidewall 712s of the doped gallium nitride layer 712 and the top surface 110a of the barrier layer 110 may have a right angle, but the present invention is not limited to this.

It should be noted that the present invention is not limited to the aspects of the above-mentioned embodiments, and the characteristics of the insulating layer, the spacer, the top cover layer, the recess and the cross-sectional shape of the doped gallium nitride layer in the above-mentioned embodiments can be viewed as Combination or selective configuration according to actual design requirements, as long as the gate structure of the GaN high electron mobility transistor includes an undoped GaN layer between the gate metal layer and the doped GaN layer, Moreover, the doped GaN layer of the gate structure has a protruding portion extending from the sidewall of the gate metal layer, all of which belong to the protection scope of the present invention.

In summary, the undoped GaN layer can be used to protect the doped GaN layer as the gate structure to ensure that it is not affected by the gate metal layer or subsequent source and drain processes, and by The protruding portion can increase the path length of the leakage current, so the gate structure of the GaN high electron mobility transistor of the present invention can effectively improve the gate leakage problem and has better reliability.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100, 200, 300, 400, 500, 600, 700: Gallium Nitride High Electron Mobility Transistor 102: Substrate 104: The first buffer layer 106: Second buffer layer 108: Channel layer 110: barrier layer 110a: top surface 112, 712: doped gallium nitride layer 112p: protrusion 114, 514: undoped gallium nitride layer 116, 416: gate metal layer 114b, 116b: bottom surface 112s, 114s, 116s, 218s, 416s, 422s, 712s: side wall 218: insulation layer 320, 420, 620: gap wall 322, 422: roof layer 416a: depression G1, G2, G3, G4, G5, G6, G7: gate structure

1 to 7 are schematic cross-sectional views of GaN high electron mobility transistors according to some embodiments of the present invention.

100: Gallium Nitride High Electron Mobility Transistor

102: Substrate

104: The first buffer layer

106: Second buffer layer

108: Channel layer

110: barrier layer

110a: top surface

112: doped gallium nitride layer

112s, 114s, 116s: side walls

112p: protrusion

114: Undoped gallium nitride layer

116: gate metal layer

114b, 116b: bottom surface

G1: gate structure

Claims (8)

A gate structure of a gallium nitride high electron mobility transistor, comprising: a doped gallium nitride layer; a gate metal layer located on the doped gallium nitride layer, wherein the doped gallium nitride layer has a protrusion extending from a sidewall of the gate metal layer; and an undoped gallium nitride layer between the gate metal layer and the doped gallium nitride layer, wherein the undoped nitrogen The GaN layer includes a portion extending over the protrusion. The gate structure of GaN high electron mobility transistor according to claim 1, wherein the gate metal layer penetrates through the undoped GaN layer. The gate structure of GaN high electron mobility transistor according to claim 1, wherein the bottom surface of the gate metal layer is coplanar with the bottom surface of the undoped GaN layer. The gate structure of a gallium nitride high electron mobility transistor according to claim 1, wherein the gate metal layer and the undoped gallium nitride layer are in direct contact with the doped gallium nitride layer. The gate structure of GaN high electron mobility transistor according to claim 1, wherein the gate structure further includes an insulating layer, and the insulating layer is located between the gate metal layer and the undoped nitrogen between gallium oxide layers. The gate structure of GaN high electron mobility transistor according to claim 5, wherein the sidewall of the gate metal layer is aligned with the sidewall of the insulating layer. The gate structure of GaN high electron mobility transistor according to claim 1, wherein the gate structure further includes a spacer, the spacer is located on the protrusion and at least covers the gate metal The sidewall of the layer. The gate structure of GaN high electron mobility transistor according to claim 7, wherein the width of the bottom surface of the spacer is equal to or smaller than the width of the top surface of the protrusion.

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