TWI779277B - Level shifter - Google Patents

Abstract

The invention relates to a level shifter, which includes a conversion circuit and a plurality of switching circuits. The conversion circuit converts a voltage level of an input signal. The switching circuits are coupled between a plurality of reference voltages and the conversion circuit. The switching circuits switch the reference voltages and provide them to the conversion circuit.

Description

level converter

The invention relates to a level converter, in particular to a level converter which reduces the number of high-voltage-resistant electronic components.

Level shifters (LEVEL SHIFTER) are widely used in circuits in different fields, such as display panel drive circuits, which are mainly used to convert the voltage level of the signal, and can provide a signal with a suitable voltage level so that the circuit can working normally. However, during the voltage level conversion process of the level converter, the internal electronic components of the level converter need to withstand high voltage differences, such as transistors, so the internal electronic components of the level converter are almost high-voltage resistant electronic components, and also It is to use large-sized high-voltage drop-resistant electronic components for voltage level conversion, which leads to more transient current consumption, and because of the large size of high-voltage drop-resistant electronic components, it is necessary to use a large circuit area to separate high-voltage and Low voltage related circuits. In addition, high-voltage-resistant electronic components can only be manufactured using high-voltage processes, which leads to high manufacturing costs

In view of the above problems, the present invention provides a level converter, which can be applied to various circuits that need to convert the voltage level of the input signal, and can reduce the number of electronic components with high voltage drop resistance and reduce the circuit size to achieve circuit area and cost. reduction, so that the above problems can be solved.

The purpose of the present invention is to provide a level converter, which uses multiple reference voltages with different voltage levels to convert the voltage level of the input signal, thereby reducing the number of electronic components with high voltage drop resistance, and reducing the circuit area and cost. .

The invention relates to a level converter, which includes a conversion circuit and complex switching circuits. The conversion circuit converts the voltage level of an input signal. The switch circuits are coupled between the complex reference voltages and the conversion circuit, and the switch circuits switch the reference voltages and provide them to the conversion circuit.

10: level converter

20: Input circuit

21: Enabling circuit

22: Conversion circuit

30: The first switching circuit

31: Second switching circuit

32: The first switching circuit

33: The second switching circuit

40: Display panel

41: Source drive circuit

42: Gate drive circuit

43: Controller

A1~A8: Source line

B1~B6: gate line

CLK: clock signal

DATA: data

EN:enable signal

G1~G6: Gate signal

M11~M18: Transistor

M21~M28: Transistor

M31~M32: Transistor

O: output terminal

OL: Inverting output terminal

S: input signal

S1~S8: Source signal

Sub-Pixel: sub-pixel

VDDK: the first reference level

VDDL: the first reference level

VDDM: the third reference level

VDDN: the third reference level

VSSK: Second reference level

VSSL: second reference level

VSSM: fourth reference level

VSSN: the fourth reference level

XEN: enable signal

XO: inverting output

XOL: inverting output

XS: input signal

The first figure: it is the circuit diagram of the first embodiment of the level converter of the present invention; the second figure: it is the circuit diagram of the second embodiment of the level converter of the present invention; the third figure: it is the circuit diagram of the present invention The circuit diagram of the embodiment of the level converter controlling a buffer circuit; and the fourth figure: it is the circuit diagram of the embodiment of the level converter of the present invention applied to the display device.

Some terms are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the technical field of the present invention should understand that manufacturers may use different terms to refer to the same component. Moreover, this specification and The claim item does not use the difference in name as the way to distinguish the components, but the difference in the overall technology of the components as the criterion for distinguishing. "Includes" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to". Furthermore, the term "coupled" herein includes any direct and indirect means of connection. Therefore, if the text describes a first If the device is coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other connection means.

Please refer to the first figure, which is the circuit diagram of the first embodiment of the level converter of the present invention. As shown in the figure, the level converter 10 includes complex switching circuits 30 , 31 , and the switching circuits 30 , 31 are coupled to complex reference voltages. The reference voltages include a first reference voltage and a second reference voltage. The level converter 10 includes a conversion circuit 22, and the conversion circuit 22 converts the voltage level of an input signal S/XS. The switch circuits 30 , 31 are coupled between the reference voltages and the conversion circuit 22 , so the switch circuits 30 , 31 can switch the reference voltages and provide one of the reference voltages to the conversion circuit 22 . Furthermore, the level converter 10 includes an input circuit 20 . The input circuit 20 receives the input signal S/XS, and the input signal XS and the input signal S are mutually inverse signals. The level converter 10 can convert the voltage level of the input signal S/XS received by the input circuit 20 to a different voltage level, wherein, because the level converter 10 can be applied to various voltage levels that need to convert the input signal S/XS A bit circuit, such as a source driver circuit or a gate driver circuit for driving a display panel, so the input signal S/XS described in the embodiment can be a voltage signal or a data.

Following the above, the conversion circuit 22 is coupled to the input circuit 20, and coupled to the first reference voltage or the second reference voltage through the switching circuits 30, 31. The first reference voltage in the embodiment includes a first reference level VDDL and A second reference level VSSL, the second reference voltage includes a third reference level VDDM and a fourth reference level VSSM. Moreover, the level difference between the first reference level VDDL and the second reference level VSSL may be equal to or close to the level difference between the third reference level VDDM and the fourth reference level VSSM. For example, the level of the first reference level VDDL is 6V and the level of the second reference level VSSL is 0V, and the level difference between them is 6V, that is, the first reference voltage may be 6V. The level of the third reference level VDDM is 15V and the level of the fourth reference level VSSM is 9V, and the level difference between the two is 6V, that is, the second reference voltage can be It is 6V, but the level of the second reference voltage is different from that of the first reference voltage. In one embodiment of the present invention, the level of the second reference voltage is greater than that of the first reference voltage. In addition, the levels of the first reference level VDDL, the second reference level VSSL, the third reference level VDDM, the fourth reference level VSSM, the first reference voltage and the second reference voltage are for illustration only, and the The first reference voltage and the second reference voltage can be supplied by the same or different power circuits, for example, two independent power circuits, or one power circuit provides different reference levels, so the above examples do not limit the embodiments of the present invention.

Referring back to the first figure, the first switching circuit 30 is coupled to the first reference level VDDL and the third reference level VDDM, the second switching circuit 31 is coupled to the second reference level VSSL and the fourth reference level VSSM, and the These switching circuits 30, 31 switch the first reference level VDDL, the second reference level VSSL, the third reference level VDDM and the fourth reference level VSSM, and provide the first reference level VDDL and the second reference level VSSL to the conversion circuit 22 , or provide the third reference level VDDM and the fourth reference level VSSM to the conversion circuit 22 , that is, the switching circuits 30 and 31 provide the first reference voltage or the second reference voltage to the conversion circuit 22 . Therefore, during the period when the conversion circuit 22 is coupled to the first reference voltage, for example, during the period when it is coupled to 6V (the first reference level VDDL) and 0V (the second reference level VSSL), the conversion circuit 22 is based on the level of the first reference voltage Convert the voltage level of the input signal S/XS to a first voltage level, that is, the first reference level VDDL or the second reference level VSSL, such as 6V or 0V. During the period when the conversion circuit 22 is coupled to the second reference voltage, for example, 15V (the third reference level VDDM) and 9V (the fourth reference level VSSM), the conversion circuit 22 switches the input according to the level of the second reference voltage. The voltage level of the signal S/XS is from the first voltage level (6V/0V) to a second voltage level (15V/9V), that is, from the first reference level VDDL to the third reference level VDDM, or from The second reference level VSSL to the fourth reference level VSSM. In other words, the level converter 10 converts the voltage level of the input signal S/XS to the first voltage level according to the first reference voltage, and converts the voltage level of the input signal S/XS from the first voltage level according to the second reference voltage. bit to the second voltage level bit. In this way, the conversion circuit 22 of the level converter 10 can output the input signal S and the input signal XS having the second voltage level at an output terminal O and an inverting output terminal XO.

In the embodiment, when the level of the input signal S is a high level (1) and the level of the input signal XS is a low level (0), the output terminal O outputs the second voltage level as the third reference level The input signal S is VDDM, and the inverting output terminal XO outputs the input signal XS whose second voltage level is the fourth reference level VSSM. When the level of the input signal S is low level (0) and the level of the input signal XS is high level (1), the output terminal O outputs the input signal S whose second voltage level is the fourth reference level VSSM , and the inverting output terminal XO outputs the input signal XS whose second voltage level is the third reference level VDDM.

The first switching circuit 30 and the second switching circuit 31 are coupled to the conversion circuit 22 , the first reference voltage and the second reference voltage, and the conversion circuit 22 is coupled to the first reference voltage or the second reference voltage via the first switching circuit 30 and the second switching circuit 31 Two reference voltages. Therefore, the first switching circuit 30 and the second switching circuit 31 switch the first reference voltage to the switching circuit 22, the voltage level of the input signal S/XS can be switched to the first voltage level, and the first switching circuit 30 and the second switching circuit The circuit 31 switches the second reference voltage coupled to the conversion circuit 22, and the voltage level of the input signal S/XS can be converted from the first voltage level to the second voltage level. One of the implementations of the first switching circuit 30 and the second switching circuit 31 may respectively include a plurality of switching switches, and the on-switching circuit 22 is coupled to the path of the first reference voltage or the second reference voltage, and the off-switching circuit 22 is coupled to the path of the first reference voltage. A path for a reference voltage or a second reference voltage.

Furthermore, the level converter 10 may include an enable circuit 21, which receives an enable signal EN, so that the level converter 10 has the level-converted input signal S/ on the latch output terminal O and the inverting output terminal XO. The function of the voltage level of XS. The enable circuit 21 is coupled between the conversion circuit 22 and the input circuit 20 , and controls the conversion circuit 22 to latch the levels of the output terminal O and the inverting output terminal XO. That is to say, the enabling circuit 21 controls the conversion circuit 22 to latch the second voltage level after level conversion between the output terminal O and the inverting output terminal XO. It is to latch the third reference level VDDM (15V) or the fourth reference level VSSM (9V) located at the output terminal O and the inverting output terminal XO, wherein each reference level corresponds to Different circuit requirements may be other levels.

For example, when the first switching circuit 30 and the second switching circuit 31 switch the first reference level VDDL and the second reference level VSSL to be coupled to the conversion circuit 22, that is, when the conversion circuit 22 is coupled to the first reference voltage, if When the level of the enable signal EN is high level (1) and the level of the input signal S is high level and the level of the input signal XS is low level (0), a transistor M11 of the input circuit 20 A gate is controlled by the input signal S and the transistor M11 is in the on state, and a gate of a transistor M17 of the input circuit 20 is controlled by the input signal XS and the transistor M17 is in the off state, and one of the enabling circuits 21 Both the crystal M12 and a gate of a transistor M18 are controlled by the enable signal EN and the transistors M12 and M18 are in a conducting state. One source of the transistors M11 and M17 is coupled to the second reference level VSSL, and the second reference level VSSL may be a ground level, but is not limited to be only a ground level. A source of the transistors M12 and M18 is respectively coupled to a drain of the transistors M11 and M17, and the transistors M11, M12, M17, and M18 may be NMOS transistors. In this way, the level of the inverting output terminal XO coupled to the drain of the transistor M12 of the enabling circuit 21 is at the level of the second reference level VSSL. Furthermore, a gate of a transistor M16 and a gate of a transistor M15 of the conversion circuit 22 are coupled to the inverting output terminal XO, and the transistor M16 can be a PMOS transistor, and the transistor M15 can be an NMOS transistor. crystals.

Therefore, when the level of the inverting output terminal XO is the level of the second reference level VSSL, the transistor M16 is in the on state, and the transistor M15 is in the off state. In this way, the first switching circuit 30 coupled to one source of the transistor M16 provides the first reference level VDDL, and the first reference level VDDL is charged to the output terminal O of the conversion circuit 22 by the drain of the transistor M16, and the output terminal The voltage level of O rises. In other words, the voltage level of the input signal S is converted to the level of the first reference level VDDL through the conversion circuit 22 . output The terminal O can be the drain of the transistor M16, the drain of the transistor M15 and the drain of the transistor M18 are coupled to the drain of the transistor M16, and the source of the transistor M15 is coupled to the second switching circuit 31 , the source of the transistor M15 is coupled to the second reference level VSSL through the second switching circuit 31 . In addition, the drain of the transistor M18 is also coupled to the output terminal O. The first reference level VDDL is higher than the second reference level VSSL, the third reference level VDDM is higher than the fourth reference level VSSM, the third reference level VDDM is higher than the first reference level VDDL, and the fourth reference level VSSM is higher than the second reference level VSSL.

A gate of a transistor M14 and a gate of a transistor M13 of the conversion circuit 22 are coupled to the output terminal O, and a source and a drain of the transistor M14 are respectively coupled to the first switching circuit 30 and the reverse The phase output terminal XO, and the transistor 14 can be a PMOS transistor, and a source and a drain of the transistor M13 are respectively coupled to the second switching circuit 31 and the inverting output terminal XO, and the transistor M13 can be NMOS Transistor. Therefore, when the level of the output terminal O is the level of the first reference level VDDL, the transistor M14 is in an off state, and the transistor M13 is in an on state. In this way, the first reference level VDDL coupled to the source of the transistor M14 via the first switch circuit 30 does not charge the inverting output terminal XO of the conversion circuit 22, and the transistor M13 is in a conduction state so that the inverting output terminal XO is kept at the level of the second reference level VSSL via the second switching circuit 31 . The drain of the transistor M13 , the drain of the transistor M14 , and the drain of the transistor M12 are coupled to each other to form an inverting output terminal XO.

Therefore, when the first switching circuit 30 and the second switching circuit 31 switch the first reference level VDDL (6V) and the second reference level VSSL (0V) to couple to the conversion circuit 22 , the four transistors M13 of the conversion circuit 22 , M14, M15, M16 and the transistor M18 on the right side must bear the voltage difference between the first reference level VDDL and the second reference level VSSL, for example, 6V, or less than the first reference level VDDL and the second reference level VSSL. The level difference of the reference level VSSL. Furthermore, the input signal S with the first voltage level wants to be raised to a higher level, and before the level of the input signal S changes to a low level, the level of the enable signal EN changes to a low level bit (0), and the first switching circuit 30 and the second switching circuit 31 switch the third reference level VDDM (15V) and the fourth reference level VSSM (9V) to couple to the conversion circuit 22, that is, the conversion circuit 22 is coupled to the first Two reference voltages, so that the voltage level of the input signal S at the output terminal O can be raised from the first voltage level (6V) to the second voltage level (15V), and the input signal XS at the inverting output terminal XO The voltage level can be raised from the first voltage level (0V) to the second voltage level (9V). Moreover, the voltage difference that the four transistors M13, M14, M15, and M16 of the conversion circuit 22 need to withstand is the level difference between the third reference level VDDM and the fourth reference level VSSM, for example, 6V, or less than the third reference level. The level difference between the bit VDDM and the fourth reference level VSSM. However, the transistors M12 and M18 need to bear high voltage difference.

In other words, when the level converter 10 intends to increase the voltage level of the input signal S to the second voltage level, although the voltage level of the second reference voltage is higher than the voltage level of the first reference voltage, the conversion circuit 22 Regardless of coupling the first reference voltage or the second reference voltage, the cross-voltages of the transistors M13, M14, M15, and M16 of the conversion circuit 22 can be maintained at the same level, such as 6V, or maintained within a predetermined range, such as the middle , Low withstand voltage electronic components can withstand voltage range. In this way, the electronic components of the conversion circuit 22 do not need to be high-voltage-resistant electronic components, that is, it is not necessary to use electronic components manufactured by a high-voltage-resistant process, so that the size of the electronic components is small, and the number of high-voltage-resistant electronic components is reduced. Reduced area and cost. It can be seen from the embodiment in the first figure that the level converter 10 uses the complex reference voltage to convert the voltage level of the input signal S/XS so that the conversion circuit 22 does not need to use electronic components with high voltage difference resistance, so the level converter 10 of the present invention The number of electronic components used to withstand high voltage differences can be greatly reduced.

Referring to the first figure again, when the level of the input signal S is low level (0), the level of the input signal XS is high level (1), and the level of the enable signal EN is also high level ( 1), the transistor M11 of the input circuit 20 is in an off state, and the transistor M17 of the input circuit 20 is in an on state. The transistor M12 and the transistor M18 of the enable circuit 21 are in a conduction state, and the output terminal O of the conversion circuit 22 is bit is the level of the second reference level VSSL. Moreover, the transistor M14 is in the on state, and the transistor M13 is in the off state. In this way, the level of the inverting output terminal XO is the level of the first reference level VDDL. When the switching circuits 30 and 31 switch the third reference level VDDM and the fourth reference level VSSM, and when the level of the enabling signal EN changes to a low level (0), the third reference level VDDM charging conversion circuit 22 inverting output XO, the level of the inverting output XO The bit rises from the first reference level VDDL to the third reference level VDDM, and the level of the output terminal O of the conversion circuit 22 rises from the second reference level VSSL to the fourth reference level VSSM. In addition, in one embodiment of the present invention, the level of the input signal S received by the input circuit 20 changes from a high level (1) to a low level (0) and the level of the input signal XS changes from a low level (0 ) changes to a high level (1), because the level of the inverting output terminal XO has not risen to the ability to cut off the transistor M16, so the discharge capability of the transistor M17 to the output terminal O (the ability to pull down the level) needs to be high In the third reference level VDDM, the charging capability of the output terminal O through the transistor M16 (the ability to raise the level), so the third reference level VDDM can be limited by adjusting the third reference level VDDM. The charging capability of the output terminal O is beneficial to the transition of the high and low levels of the output terminal O. Similarly, when the level of the input signal S received by the input circuit 20 changes from a low level (0) to a high level (1), the level of the input signal XS changes from a high level (1) to a low level ( 0), limiting the charging capability of the third reference level VDDM via the transistor M14 to the inverting output terminal XO facilitates the transition of the high and low voltage levels of the inverting output terminal XO.

Please refer to the second figure, which is the circuit diagram of the second embodiment of the level converter of the present invention. As shown in the figure, the input circuit 20 and the enabling circuit 21 of the level converter 10 can be implemented by changing the NMOS transistors M11, M17, M12, and M18 in the first figure to PMOS transistors M21, M27, M22, and M28, and The connection relationship remains unchanged, and the transistors M13, M14, M15, M16 of the conversion circuit 22 in the first figure are of the same type as the transistors M24, M23, M26, M25 in the second figure, and the connection relationship remains unchanged. The enable circuit 21 in the second figure is coupled to the enable signal XEN, and the enable signal XEN and the enable signal EN are mutually inverse signals. No. Moreover, the embodiment in the first figure is used to convert the positive voltage level, the embodiment in the second figure is used to convert the negative voltage level, and the conversion circuit 22 in the second figure is coupled to the second switch circuit 33 via the first switch circuit 32 The first reference voltage and the second reference voltage. The first reference voltage and the second reference voltage of this embodiment can be a negative voltage, and respectively include a first reference level VDDK, a second reference level VSSK, a third reference level VDDN, a fourth reference level Level VSSN, such as 0V, -6V and -9V, -15V. Furthermore, the sources of the transistors M21 and M27 of the input circuit 20 in the embodiment of the second figure are coupled to the first reference level VDDK, and the output end of the level converter 10 is marked as OL, and the inverting output end is marked as XOL , and the level of the output terminal OL and the inverting output terminal XOL can be the second voltage level after the conversion circuit 22 converts the level, that is, the third reference level VDDN or the fourth reference level VSSN. The rest of the techniques are similar to the description of the first figure and will not be described again. In addition, the first reference level VDDK and the second reference level VSSK mentioned above can be replaced by the first reference level VDDL and the second reference level VSSL in the embodiment of the first figure, so it can be known that the first reference level VDDK , the second reference level VSSK, the third reference level VDDN, and the fourth reference level VSSN can be designed according to usage requirements.

Please refer to the third figure, which is a circuit diagram of an embodiment of the level converter controlling a buffer circuit of the present invention. As shown in the figure, the buffer circuit includes a transistor M32 and a transistor M31, a source of the transistor M32 is coupled to the first switching circuit 30, and a gate of the transistor M32 is coupled to the standard of the embodiment in the first figure. On the output terminal O of the bit converter 10, one source of the transistor M31 is coupled to the second switching circuit 33, and one gate of the transistor M31 is coupled to the output terminal OL of the level converter 10 of the embodiment of the second figure, In addition, a drain of the transistor M32 is coupled to a drain of the transistor M31 to be an output terminal. Moreover, the buffer circuit shown in the third figure can be used as a driver for the gate drive circuit of the display device, for outputting gate signals (such as G1, G2, G3, G4, G5, G6 in the fourth figure) to the display panel. The buffer circuit is coupled to the first reference level VDDL or the third reference level VDDM via the first switching circuit 30, and the buffer circuit is coupled to the second reference level via the second switching circuit 33. The reference level VSSK and the fourth reference level VSSN. Moreover, the first switch circuit 30 in the first figure and the third figure are switched synchronously, so the first switch circuit 30 in the first figure switches the first reference level VDDL or the third reference level VDDM coupled to the first figure. The level converter 10, let the level of the output terminal O of the level converter 10 in the first figure be the first voltage level (the first reference level VDDL) or the second voltage level (the third reference level VDDM ), the first switching circuit 30 in the third figure will also switch, so the source of the transistor M32 is also at the first voltage level (the first reference level VDDL) or the second voltage level (the third reference level VDDM), so that the transistor M32 does not need to withstand a higher voltage difference, that is, the transistor M32 does not need to be an electronic component that withstands a high voltage difference, and the size of the electronic component and the circuit area can be reduced.

Following the above, the second switch circuit 33 in the second figure and the third figure are switched synchronously, so the second switch circuit 33 in the second figure switches the second reference level VSSK or the fourth reference level VSSN coupled to the second figure level Bit converter 10, let the level of the output terminal OL of the level converter 10 in the second figure be the first voltage level (second reference level VSSK) or the second voltage level (fourth reference level VSSN) , the second switching circuit 33 in the third figure will also switch, so the source of the transistor M31 is also at the first voltage level (second reference level VSSK) or the second voltage level (fourth reference level VSSN ), so that the transistor M31 does not need to withstand a higher voltage difference, that is, the transistor M31 does not need to be an electronic component that withstands a high voltage difference, and the number of electronic components that withstand a high voltage difference can be reduced. In addition, the switching circuits in the first figure, the second figure and the third figure can be different independent switching circuits, that is, the switching circuit in the second figure is changed to a third switching circuit and a fourth switching circuit, and the switching circuit in the third figure The circuit is changed to the fifth switching circuit and the sixth switching circuit, but the switching method can also make the electronic components not need to bear high voltage difference, and maintain the electronic component only to bear low voltage difference.

Please refer to FIG. 4 , which is a circuit diagram of an embodiment of the level converter of the present invention applied to a display device. As shown in the figure, the display device includes a display panel 40 , a source driving circuit 41 , a gate driving circuit 42 and a controller 43 . The display panel 40 includes a plurality of sub-pixels Sub-Pixel, a plurality of source lines A1, A2, A3, A4, A5, A6, A7, A8 and complex gate lines B1, B2, B3, B4, B5, B6. The regions surrounded by the source lines A1 - A8 and the gate lines B1 - B6 include the sub-pixels Sub-Pixel. The complex source signals S1~S8 output by the source driving circuit 41 are transmitted to the sub-pixels Sub-Pixel through the source lines A1~A8, and the complex gate signals G1, G2, G3, G4, G5, and G6 are transmitted to the sub-pixels through the gate lines B1-B6. The sub-pixels Sub-Pixel display images according to the source signals S1-S8 under the control of the gate signals G1-G6. Furthermore, in the embodiment, the gate driving circuit 42 may include the level converter 10 in the first and second figures, however, during driving the display panel 40, the levels of the gate signals G1-G6 will be the scan level or disable level to scan these gate lines B1, B2, B3, B4, B5, B6, so when changing the voltage levels of these gate signals G1~G6, the gate drive circuit 42 can Cooperate with the level converter 10 to drive the buffers as shown in the third figure to output the gate signals G1~G6 with scan level or disable level. The scan level can be a positive voltage level, and the disable level The bit can be a negative voltage level. In other words, the level converter 10 of the present invention can be applied to various circuits that need to convert the voltage level of a signal.

Referring again to FIG. 4 , the controller 43 generates a clock signal CLK and a data DATA to the source driving circuit 41 , wherein the data DATA can be provided by the controller 43 or not provided by the controller 43 , which are optional designs. In addition, the controller 43 also outputs the clock signal CLK to the gate driving circuit 42 to control the working timing of the source driving circuit 41 and the gate driving circuit 42 . .

To sum up, the present invention relates to a level converter, which includes a conversion circuit and complex switching circuits. The conversion circuit converts the voltage level of an input signal. The switching circuits are coupled between the plurality of reference voltages and the conversion circuit. The switching circuits switch the reference voltages and provide them to the conversion circuit to convert the voltage level of the input signal.

10: level converter

20: Input circuit

21: Enabling circuit

22: Conversion circuit

30: The first switching circuit

31: Second switching circuit

EN:enable signal

M11~M18: Transistor

O: output terminal

S: input signal

VDDL: the first reference level

VDDM: the third reference level

VSSL: second reference level

VSSM: fourth reference level

XO: inverting output

XS: input signal

Claims (6)

A level converter, which includes: an input circuit, receiving an input signal; a conversion circuit, converting the voltage level of the input signal; an enabling circuit, coupled between the input circuit and the conversion circuit, to control the The conversion circuit latches the converted voltage level of the input signal; and the plurality of switching circuits are coupled between the plurality of reference voltages and the conversion circuit, and the switching circuits switch the reference voltages and provide them to the conversion circuit. The level converter as described in claim 1, wherein the reference voltages include a first reference voltage and a second reference voltage, and the first reference voltage includes a first reference level and a second reference level , the second reference voltage includes a third reference level and a fourth reference level, and the switching circuits are coupled to the first reference level, the second reference level, the third reference level and the first reference level Four reference levels, the switching circuits switch the first reference level, the second reference level, the third reference level and the fourth reference level, and provide the first reference level and the second reference level The reference level is provided to the conversion circuit, or the third reference level and the fourth reference level are provided to the conversion circuit. The level converter as described in claim 1, wherein the switching circuits include a first switching circuit and a second switching circuit, the reference voltages include a first reference voltage and a second reference voltage, and the first A switch circuit and the second switch circuit switch the first reference voltage coupled to the switch circuit, the voltage level of the input signal is converted to a first voltage level, the first switch circuit and the second switch circuit switch the The second reference voltage is coupled to the conversion circuit, and the voltage level of the input signal is converted from the first voltage level to a second voltage level. The level converter as described in claim 1, wherein the reference voltages include a first reference voltage and a second reference voltage, and the voltage level of the second reference voltage is higher than the voltage level of the first reference voltage bit, the conversion circuit is coupled to the first reference voltage or the second reference voltage through the switching circuits and maintains the cross voltage of the conversion circuit within a predetermined range. A level converter, which includes: a conversion circuit, which converts the voltage level of an input signal; and complex switching circuits, coupled between complex reference voltages and the conversion circuit, and the switching circuits switch the reference voltages, and provided to the conversion circuit; wherein, the reference voltages include a first reference voltage and a second reference voltage, and the switching circuits provide the first reference voltage or the second reference voltage to the conversion circuit, and the conversion circuit converting the voltage level of the input signal to a first voltage level according to the first reference voltage, and converting the voltage level of the input signal from the first voltage level to a second voltage level according to the second reference voltage bit. A level converter, which includes: a conversion circuit, which converts the voltage level of an input signal; and complex switching circuits, coupled between complex reference voltages and the conversion circuit, and the switching circuits switch the reference voltages, and provided to the conversion circuit; wherein, the reference voltages include a first reference voltage and a second reference voltage, the first reference voltage includes a first reference level and a second reference level, and the second reference The voltage includes a third reference level and a fourth reference level, the level difference between the first reference level and the second reference level is equal to the level of the third reference level and the fourth reference level Difference.

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