TWI775486B - Memory device and manufacturing method thereof - Google Patents

Abstract

A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and and electrically connected to the first conductive layer and the substrate.

Description

Memory device and method of manufacturing the same

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional memory device and a manufacturing method thereof.

Non-volatile memory devices (eg, flash memory) are widely used as memory devices in personal computers and other electronic devices because of the advantage that the stored data does not disappear after a power failure.

Currently, the flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of the NAND flash memory is to connect the memory cells in series, its accumulation and area utilization are better than those of the NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with 3D NAND flash memory.

According to an embodiment of the present invention, a memory element is provided, comprising: a first stack structure including a first insulating layer and a first conductor layer located on the first insulating layer; a second stack structure located on the first stack structure On the top, the second stack structure includes a plurality of second conductor layers and a plurality of second insulating layers alternated with each other; a channel column passes through the second stack structure and extends to the first stack structure; a storage layer , located between the channel column and the first stack structure and between the channel column and the second stack structure; and a conductor column located in the first conductor layer and connected to the first conductor The layer is electrically connected to the substrate.

According to an embodiment of the present invention, a memory element is proposed, comprising: a stacked structure located above a substrate, the stacked structure including a plurality of conductor layers and a plurality of insulating layers alternating with each other; a top insulating layer on the stacked structure; a channel a pillar located between the top insulating layer and the stacked structure; a storage layer located between the channel pillar and the plurality of conductor layers; a dielectric layer located on the top insulating layer; and a contact window, Passing through the dielectric layer and the top insulating layer, and electrically connecting the channel pillars, wherein the ratio of the thickness of the dielectric layer to the thickness of the top insulating layer is greater than 2.

According to an embodiment of the present invention, a method for manufacturing a memory element is provided, comprising: forming a first stack structure on a substrate, the first stack structure including a plurality of first conductor layers and a plurality of first insulating layers alternating with each other; forming a conductor post in the first stack structure to ground one of the plurality of first conductor layers; forming a first level of a second stack structure on the first stack structure, the second stack structure The first level of the second stack structure includes a plurality of sacrificial layers and a plurality of second insulating layers alternated with each other; a first opening is formed in the first level and the first stack structure of the second stack structure; A sacrificial column is formed in the first opening, the sacrificial column is electrically connected to the conductor column through the one of the first conductor layers, and then grounded; on the first level of the second stack structure forming a second level of the second stack structure; performing a patterning process to form a second opening in the second level of the second stack structure, wherein the second opening exposes the sacrificial pillars; removing the sacrificial pillars to expose the first openings; forming storage layers and channel pillars in the first openings and the second openings; and insulating a portion of the plurality of first openings Layers and part of the plurality of first conductor layers are replaced by a plurality of second conductor layers, so that the remaining plurality of first conductor layers and the plurality of second conductor layers form source lines.

The embodiments of the present invention can alleviate or solve the problems of misalignment and high etching rate of the unlanded area by the arrangement of the grounded conductor post and the selection of the etching gas in the over-etching process.

1A to 1N are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. 2A is a partial cross-sectional schematic diagram of a three-dimensional memory device according to an embodiment of the present invention. 2B is a schematic partial cross-sectional view of a three-dimensional memory device according to another embodiment of the present invention.

Referring to FIG. 1A , a substrate 100 is provided, and a stack structure SK1 is formed on the substrate 100 . In one embodiment, the substrate 100 has regions R1, R2 and R3, and the region R2 is located between the regions R1 and R3. The area R1 is also called the unit cell area 1, the area R2 is also called the transition area, and the area R3 is also called the step area. The substrate 100 has a grounded conductive region CR therein. The conductive region CR can be a semiconductor substrate, a doped region, or a grounded metal interconnect.

Referring to FIG. 2A , in one embodiment, the substrate 100 is a semiconductor substrate 10 , such as a silicon-containing substrate, and the conductive region CR may be a doped region 12 in the semiconductor substrate 10 . The memory array will be formed directly above the stacked structure SK1, and the peripheral circuit elements such as complementary metal oxide semiconductor elements (CMOS) will be formed in the peripheral circuit area (not shown) of the semiconductor substrate 10 beside the memory array. , without forming the stack structure below SK1.

Referring to FIG. 2B , in another embodiment, the substrate 100 includes a semiconductor substrate 10 , an element layer 20 and a metal interconnect structure 30 . The element layer 20 may include active elements or passive elements. The active elements are, for example, transistors, diodes, and the like. Passive elements are, for example, capacitors, inductors, and the like. The transistor may be an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a complementary metal-oxide-semiconductor (CMOS). The metal interconnect structure 30 includes a multilayer dielectric layer 32 and a metal interconnect 33 formed in the multilayer dielectric layer 32 . The metal interconnect 33 includes a plurality of plugs 34 and a plurality of wires 36 and the like. Dielectric layer 32 separates adjacent wires 36 . The wires 36 can be connected by the plugs 34 , and the wires 36 can be connected to the device layer 20 by the plugs 34 . Since the memory array will be formed just above the stacked structure SK1 in the region R1, and the device layer 20 is formed under the memory array, such as a complementary metal oxide semiconductor (CMOS), so this structure can also be called complementary The metal oxide semiconductor element is under the memory array (CMOS-Under-Array, CUA) structure.

Referring to FIG. 1A , the stacked structure SK1 includes a plurality of insulating layers 92 and a plurality of conductor layers 94 stacked alternately. In one embodiment, the material of the insulating layer 92 includes silicon oxide, and the material of the conductor layer 94 includes doped polysilicon.

Then, through lithography and etching processes, the stacked structure SK1 in the region R3 is patterned to form a plurality of grooves, and a dielectric layer 95 (eg, silicon oxide) is filled in the grooves. Next, an opening O1 is formed in the stacked structure SK1 in the region R2 through lithography and etching processes. The opening O1 is, for example, a hole or a trench. The opening O1 exposes the surface of the conductive region CR. The etching process is, for example, a dry etching process, a wet etching process, or a combination thereof. The shape of the opening O1 can be cylindrical, elliptical, or rectangular, and there is no particular limitation.

Referring to FIG. 1B, a conductor post DCC is formed in the opening O1. The conductor post DCC has a low resistance value, and its resistance value is lower than that of the conductor layer 94 . In one embodiment, the conductor layer 94 is doped polysilicon, and the conductor column DCC is tungsten, titanium nitride, tantalum, or a combination thereof. The method for forming the conductor column DCC is, for example, forming a conductor material on the stack structure SK1 and in the opening O1, and then removing excess conductor material on the stack structure SK1 through a planarization process, such as an etch-back process or a chemical mechanical polishing process.

The conductor post DCC is electrically connected to the conductive region CR, so the conductor post DCC can be grounded to serve as a discharge path. In one embodiment, the conductor column DCC is electrically connected to the doped region 12 in the semiconductor substrate 10 , as shown in FIG. 2A . In another embodiment, the conductor post DCC is electrically connected to the topmost wire 36 of the metal interconnection 33 , and the topmost wire 36 is electrically connected to the substrate 10 and then grounded, as shown in FIG. 2B .

In the embodiment of FIG. 1B , the conductor posts DCC extend from the top surface of the stack structure SK1 to the bottom surface of the stack structure SK1 . However, the embodiment of the present invention is not limited to this, and the conductor post DCC may extend from any insulating layer 92 or conductor layer 94 of the stack structure SK1 to pass through the bottommost insulating layer 92 and extend to the bottom surface of the stack structure SK1 to conduct electricity. The regions CR are electrically connected, as shown in FIGS. 3A to 3F .

Fig. 3G is a partial perspective schematic view of the line I-I' of Fig. 1M. For clarity, the dielectric layer DL1 is omitted.

Referring to FIG. 3G , the number of the conductor posts DCC can be determined according to actual needs. In some embodiments, each block B is used to form an array of channel pillars VC1. The arrays of channel posts VC1 of two adjacent blocks B are separated by a slit SLT. In this embodiment, four blocks B share a single conductor column DCC, as shown in FIG. 3G . However, the present invention is not limited to this, more or less blocks B may share a single conductor column DCC, or a single block may have a single or multiple conductor columns DCC (not shown).

Referring to FIG. 1C , a first level (tier, deck) P1 of the stacked structure SK2 is formed on the stacked structure SK1 . The first level P1 of the stacked structure SK2 includes a plurality of insulating layers 102 and a plurality of sacrificial layers 104 stacked alternately. The insulating layer 102 and the sacrificial layer 104 may also be referred to as the first insulating layer 102 and the second insulating layer 104, respectively. In one embodiment, the material of the insulating layer 102 includes silicon oxide, and the material of the sacrificial layer 104 includes silicon nitride.

The first level P1 of the stacked structure SK2 is patterned to form the stepped structure SC1 in the region R3. The stepped structure SC1 can be formed by any known patterning method, such as photolithography, etching, and trimming processes.

Referring to FIG. 1C , a dielectric layer DL1 is formed on the substrate 100 to cover the stepped structure SC1 . The material of the dielectric layer DL1 is, for example, silicon oxide. The method for forming the dielectric layer DL1 is, for example, to form a dielectric material layer, and then through a planarization process, such as an etch-back process or a chemical mechanical polishing process, to remove the excess dielectric material layer on the first level P1 of the stack structure SK2 .

Referring to FIG. 1D , a plurality of openings OP1 are formed in the first level P1 of the stacked structure SK2 and the stacked structure SK1 . The bottom of the opening OP1 exposes the bottommost conductor layer 94 of the stacked structure SK1.

Referring to FIG. 1E, a sacrificial pillar SP1 is formed in the opening OP1. The sacrificial column SP1 is electrically connected to the conductive region CR of the substrate 100 through the conductive layer 94 and the conductive column DCC. The material of the sacrificial pillar SP1 is different from that of the insulating layer 102 . The sacrificial pillar SP1 can be selected from a material with high conductivity, and its conductivity can be greater than that of the sacrificial layer 104 . The material of the sacrificial post SP1 may be the same as or different from that of the conductor post DCC. The material of the sacrificial pillar SP1 is, for example, tungsten, titanium nitride, tantalum, carbon, doped polysilicon, undoped polysilicon, or a combination thereof. The sacrificial pillar SP1 is formed by, for example, forming a conductor material on the first level P1 of the stack structure SK2 and in the opening OP1, and then through a planarization process, such as an etch back process or a chemical mechanical polishing process, to remove the stack structure SK2. Excess conductor material on the first level P1.

Referring to FIG. 1F , according to the method for forming the first level P1 of the stacked structure SK2 , the second level P2 of the stacked structure SK2 is formed. The second level P2 of the stacked structure SK2 includes a plurality of insulating layers 202 and a plurality of sacrificial layers 204 stacked alternately. In one embodiment, the material of the insulating layer 202 includes silicon oxide, and the material of the sacrificial layer 204 includes silicon nitride. After that, the second level P2 of the stacked structure SK2 of the region R3 is patterned to form the stepped structure SC2.

Referring to FIG. 1G , according to the method for forming the dielectric layer DL1 , a dielectric layer DL2 is formed on the substrate 100 to cover the stepped structure SC2 . The material of the dielectric layer DL2 is, for example, silicon oxide. The method of forming the dielectric layer DL2 is, for example, forming a dielectric material layer, and then removing the excess dielectric material layer on the second level P2 of the stack structure SK2 through a planarization process, such as an etch-back process or a chemical polishing process.

Referring to FIGS. 1G and 1H, lithography and etching processes are performed to form openings OP2 in the second level P2 of the stacked structure SK2. The etching process is, for example, dry etching, wet etching or a combination thereof. Dry etching is, for example, plasma etching. The etching process includes a main etching process ME1 and an over-etching process OE1. In some embodiments, the main etching process ME1 can be controlled by time mode to expose the bottommost insulating layer 202 of the second level P2 of the stacked structure SK2, as shown in FIG. 1G . The over-etching process OE1 may continue to etch the bottommost insulating layer 202 until the sacrificial pillar SP1 is exposed.

However, in some embodiments, misalignment occurs during the lithography process, so that the sidewall SW2' of the opening OP2' formed by the main etching process ME1 is offset from the corresponding sidewall SW1 of the sacrificial pillar SP1, as shown in FIG. 1G Show. In the subsequent over-etching process, a part of the formed opening OP2 will not land on the sacrificial pillar SP1, and this area is called an unlanded area UA1. If the etching rate of the unlanded area UA1 is too high, the multi-layer sacrificial layer 104 will be etched, thereby causing electrical problems. The present invention can alleviate or solve the problems of misalignment and too high etching rate of the unlanded area UA1 through the setting of the conductor column DCC and the selection of the etching gas in the over-etching process OE1.

In the embodiment of the present invention, the conductor post DCC is grounded and is electrically connected to the sacrificial post SP1 through the conductor layer 94. Therefore, during the plasma etching process, the conductor post DCC can be used as an antenna to collect charges and guide plasma ions toward the sacrificial post. Column SP1. Therefore, the amount of plasma ions staying in the unlanded area UA1 can be reduced, the degree of etching of the sacrificial layer 204 by the plasma ions can be slowed down, and the formed openings OP2 can be automatically aligned with the sacrificial pillars SP1.

Furthermore, the second etching gas used in the over-etching process OE1 according to the embodiment of the present invention is different from the first etching gas used in the main etching process ME1. The first etching gas has a first etching selectivity ratio for the insulating layer 202 to the sacrificial layer 204 or 104, and the second etching gas has a second etching selectivity ratio for the insulating layer 202 to the sacrificial layer 204 or 104, and the second etching selectivity ratio is greater than all. The first etching selectivity ratio is described. The first etching selection ratio is, for example, 0.3 to 3, and the second etching selection ratio is, for example, 4 to 20. In addition, the second etching gas has a third etching selectivity ratio for the insulating layer 202 to the sacrificial pillar SP1. The third etching selection ratio is, for example, greater than 6.5. In the embodiment where the sacrificial pillar SP1 is tungsten and the insulating layer 202 is silicon oxide, the third etch select ratio is greater than 40.

Both the first etching gas and the second etching gas are carbides containing fluorine. The first etching gas has a first ratio of fluorine to carbon (F/C), and the second etching gas has a second ratio of fluorine to carbon, and the second ratio is greater than the first ratio. The second etching gas used in the over-etching process OE1 has a high fluorocarbon (F/C) ratio, which can generate a by-product PM1 with a sufficient thickness (a large amount) during the etching process, such as a fluorocarbon polymer, covering the opening OP2. bottom to protect the topmost sacrificial layer 104 around the sacrificial pillar SP1. Thereby, the etching rate of the unlanded area UA1 is slowed down, and even the etching of the unlanded area UA1 is stopped, while the landed area LA1 continues to be etched. In this way, etching uniformity across the wafer can be ensured.

For example, the first etching gas used in the main etching process ME1 includes fluorinated hydrocarbons, such as CHF ₃ , CH ₂ F ₂ , CH ₃ F or a combination thereof; the second etching gas used in the over-etching process OE1 includes all Fluorocarbon _CxFy , where y/ _x is less than 3. _{A perfluorocarbon CxFy} such as _C4F6 , _C4F8 , _{C5F8 , C3F8 ,} or a _combination thereof. _In some embodiments, the main etch process ME1 uses a fluorinated hydrocarbon such as _CHF3 , _CH2F2 , _CH3F , or a combination thereof, while the overetch process _{OE1 uses a perfluorocarbon CxFy such} as C _4F6 , _C4F8 , _C5F8 , _C3F8 , or combinations thereof, without the use _{of fluorinated} hydrocarbons ₍ eg, _CHF3 , _CH2F2 , _{CH3F ,} or combinations thereof ₎ . In other embodiments, the main etch process ME1 uses fluorinated hydrocarbons such as CHF ₃ , CH ₂ F ₂ , CH ₃ F or a combination thereof, while the over-etch process OE1 uses perfluorocarbons C _x F _y such as C ₄ F ₆ , C ₄ F ₈ , C 5F ₈ , C ₃ F ₈ , or combinations thereof, and fluorinated hydrocarbons (eg, CHF ₃ , CH ₂ F ₂ , CH ₃ F , or combinations thereof) are used, but are overetched The content of the fluorinated hydrocarbon used in the process OE1 is lower than the content of the main etching process ME1 to improve the etching selectivity ratio of the insulating layer 202 to the sacrificial layer 204 .

Furthermore, when the over-etching process OE1 is performed, diluting the oxygen concentration or reducing the flow rate of oxygen with a large amount of carrier gas such as Ar can facilitate the deposition of the by-product (polymer) PM1. In addition, the over-etching process OE1 is performed at a higher pressure, eg, 20 mTorr to 200 mTorr, to facilitate the deposition of by-products (eg, polymers) PM1.

In some exemplary embodiments, the main etch process ME1 includes using 60 to 80 seem of CHF ₃ , 15 to 25 seem of C ₄ F ₈ , 120 to 180 seem of Ar, and 20 to 24 seem of O ₂ at a pressure of 20 mTorr; The overetch process OE1 includes using 15 to 20 seem of _C4F6 , ₈ to 12 seem of _C4F8 , 600 to ₈₀₀ seem of Ar, and 20 to 30 seem of _O2 at a pressure of 30 mTorr.

Referring to FIG. 1I , a cleaning process is performed, for example, an acid such as Carrollic acid (H ₂ SO ₅ ) is used first. After that, rinse with deionized water. So far, the bottom of the opening OP2 exposes the sacrificial pillar SP1 and the topmost sacrificial layer 104 around the sacrificial pillar SP1. In other words, the over-etching process OE1 can be stopped at the topmost sacrificial layer 104 . In the embodiment of the present invention, due to the setting of the conductor column DCC and the selection of the etching gas in the over-etching process OE1, the formed opening OP2 is aligned with the sacrificial column SP1, so that the outline of the upper sidewall SW2 _U of the formed opening OP2 is the same as The profile of the lower side wall SW2 _L is different. The contour of the upper side wall SW2 _U is, for example, a substantially straight line, and the contour of the lower side wall SW2 _L is, for example, a curve.

Referring to FIG. 1J, a sacrificial pillar SP2 is formed in the opening OP2. The sacrificial pillar SP2 is electrically connected to the conductive region CR of the substrate 100 through the sacrificial pillar SP1 , the conductor layer 94 and the conductor pillar DCC. The material and formation method of the sacrificial pillar SP2 may be the same as the material and formation method of the sacrificial pillar SP1, but not limited thereto.

Referring to FIG. 1K , according to the method for forming the first level P1 of the stacked structure SK2 , the third level P3 of the stacked structure SK2 is formed. The third level P3 of the stacked structure SK2 includes a plurality of insulating layers 302 and a plurality of sacrificial layers 304 stacked alternately. In one embodiment, the material of the insulating layer 302 includes silicon oxide, and the material of the sacrificial layer 304 includes silicon nitride. Then, according to the method for forming the stepped structure SC2, the third level P3 of the stacked structure SK2 is patterned to form the stepped structure SC3. After that, according to the method of forming the dielectric layer DL1 , the dielectric layer DL3 is formed on the substrate 100 .

Next, an insulating cap layer 115 is formed on the third level P3 of the stacked structure SK2 and the dielectric layer DL3. The insulating cap layer 115 is, for example, silicon oxide. Then, a plurality of openings OP3 are formed in the insulating cap layer 115 and the third level P3 of the stacked structure SK2. The opening OP3 may be formed in accordance with the method of forming the opening OP2. Likewise, the present invention can alleviate or solve the problems of misalignment and excessively high etching rate of the unlanded area UA2 through the setting of the conductor post DCC and the selection of the etching gas in the over-etching process. In some embodiments, the sacrificial pillar SP2 and the topmost sacrificial layer 204 around the sacrificial pillar SP2 are exposed at the bottom of the opening OP3 during the cleaning process after the over-etching. In other words, the over-etch process can be stopped at the topmost sacrificial layer 204 . In the embodiment of the present invention, the contour of the upper side wall SW3 _U of the formed opening OP3 is different from the contour of the lower side wall SW3 _L. The contour of the upper side wall SW3 _U is, for example, a substantially straight line, and the contour of the lower side wall SW3 _L is, for example, a curve.

In this embodiment, five insulating layers 102 , 202 , 302 and five sacrificial layers 104 , 204 , 304 are used for description, however, the present invention is not limited thereto. In addition, in this embodiment, a stack structure SK2 having three levels P1, P2 and P3 is used for description. However, the stacked structure SK2 may further include one or more levels between the first level P1 and the second level P2 or between the second level P2 and the third level P3 according to the present invention.

Referring to FIG. 1L, an etching process is performed to remove the sacrificial pillars SP1 and SP2, so that the openings OP3, OP2, and OP1 are communicated with each other to form a via hole OP4. Since the materials of the sacrificial pillars SP1 and SP2 are different from the materials of the layers of the stacked structures SK1 and SK2 , a high etching selectivity ratio can be obtained when the sacrificial pillars SP1 and SP2 are removed. The formed via hole OP4 passes through the insulating cap layer 115 and the stack structure SK2, and extends to the stack structure SK1, exposing the bottommost conductor layer 94 of the stack structure SK1.

Referring to FIG. 1M, a storage layer 108 and a channel column VC1 are formed in the channel hole OP4. The storage layer 108 surrounds the outer surface of the channel column VC1. The channel columns VC1 may be arranged in an array. The channel column VC1 may also be referred to as a vertical channel column, which may be formed by the method described below. A storage layer 108 is formed on the sidewall of the via hole OP4. In one embodiment, the storage layer 108 is an oxide/nitride/oxide (ONO) composite layer, so the storage layer 108 may also be referred to as a charge storage structure. In one embodiment, the storage layer 108 is formed on the sidewall of the channel hole OP4 in the form of a spacer, and the bottom surface of the channel hole OP4 is exposed. Next, a channel layer 110 is formed on the storage layer 108 . In one embodiment, the material of the channel layer 110 includes polysilicon. The channel layer 110 covers the storage layer 108 on the sidewall of the channel hole OP4, and also covers the channel layer 110 on the bottom surface of the channel hole OP4. Next, insulating pillars 112 are formed in the via holes OP4. In one embodiment, the material of the insulating pillars 112 includes silicon oxide. After that, conductor plugs 114 are formed on the insulating pillars 112 , and the conductor plugs 114 are in contact with the channel layer 110 . In one embodiment, the material of the conductor plug 114 includes polysilicon. The channel layer 110 and the conductor plugs 114 may be collectively referred to as a channel column (or referred to as a vertical channel column) VC1.

In some embodiments, the channel column VC1 is multi-segmented. For example, the channel column VC1 includes a first section S1, a second section S2 and a third section S3, and the centerlines CL1 and CL2 of the first section S1, the second section S2 and the third section S3 and between CL2 and CL3 They are not aligned, but have non-zero distances d1 and d2, respectively. In addition, the third section S3 extends downward until its bottom is surrounded by the gate layer 126 ₂ , but the bottom surface of the third section S3 is higher than the bottom surface of the gate layer 126 ₂ . The second section S2 extends downward until its bottom is surrounded by the gate layer 126 ₁ , but the bottom surface of the second section S2 is higher than the bottom surface of the gate layer 126 ₁ .

After that, referring to FIG. 1M , a replacement process is performed. The replacement process includes removing the sacrificial layers 104 , 204 , and 304 of the stacked structure SK2 to form horizontal openings (not shown), and filling the horizontal openings with conductor layers. The conductor layer includes, for example, a barrier layer 122 and a metal layer 124 . In one embodiment, the material of the barrier layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer 124 includes tungsten (W ). The conductor layer in the horizontal opening serves as the gate layer 126 .

1M , the conductor layer 94 in the middle of the stacked structure SK1 is removed, and then the insulating layers 92 above and below the conductor layer 94 are removed to form a horizontal opening (not shown) in the stacked structure SK1 . Then, the conductor layer 94' is filled in the horizontal opening. The conductor layer 94' in the horizontal opening together with the conductor layer 94 above and below it forms a source line 96. So far, the channel layer 110 is connected to the source line 96 .

Thereafter, referring to FIG. 1N , a dielectric layer 130 is formed on the substrate 100 . The dielectric layer 130 is, for example, silicon oxide. Next, a plurality of contact windows C1 and C2 are formed. The contact window C1 is electrically connected to the conductor plug 114 of the channel column VC1. The contact window C2 is electrically connected to the ends of the gate layers 126 of the plurality of stepped structures SC1 , SC2 and SC3 in the region R3 . The contact windows C1 and C2 may be formed simultaneously or separately. In one embodiment, each of the contacts C1, C2 may include a barrier layer and a conductor layer. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the conductor layer is, for example, tungsten (W).

The heights of the conductor post DCC, the contact windows C1 and C2 and the channel post VC1 in the embodiment of the present invention are different. The top surface of the conductor post DCC is lower than the top surfaces of the contact windows C1 and C2 and the via post VC1 . Also, the length of the conductor post DCC is smaller than the length of the channel post VC1. The material of the conductor post DCC is different from the material of the channel post VC1 and the source line 96 . The conductor post DCC is buried in the source line 96 and is electrically connected to the source line 96 . The conductor post DCC is electrically insulated from the upper gate layer 126 by the insulating layer 102 , but the conductor post DCC passes through the lower insulating layer 92 and is connected to the conductive region CR.

The etching gas used for forming the opening OP2 in the embodiment of the present invention is not limited to being used in the three-dimensional memory device having the stacked structure SK2 of the multi-level P1, P2, and P3. Another embodiment is described below with reference to FIGS. 4A to 4G . 4A to 4G are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

Referring to FIG. 4A , the stacked structure SK3 is formed on the substrate 400 according to the above-mentioned method for forming the stacked structure SK1 . The material and structure of the substrate 400 may be the same as or similar to those of the substrate 100 . The stacked structure SK3 includes multiple insulating layers 392 and a plurality of conductor layers 394 which are alternated with each other. The material of the insulating layer 392 includes silicon oxide; the material of the conductor layer 394 includes doped polysilicon.

After that, a stacked structure SK4 is formed on the stacked structure SK3, and the stacked structure SK3 is patterned to form a stepped structure (not shown). The stacked structure SK4 includes a plurality of insulating layers 402 and a plurality of sacrificial layers 404 stacked alternately. In one embodiment, the material of the insulating layer 402 includes silicon oxide, and the material of the sacrificial layer 404 includes silicon nitride. In FIGS. 4A to 4G , five insulating layers 402 and five sacrificial layers 404 are used for illustration, however, the present invention is not limited thereto. Then, a dielectric layer (not shown) is formed on the stepped structure. The material and formation method of the dielectric layer may be the same as or different from the material and formation method of the dielectric layer DL1 . Next, an insulating cap layer 415 is formed on the stacked structure SK4 and the dielectric layer on the stepped structure. The insulating capping layer 415 is, for example, silicon oxide. In some embodiments, the insulating cap layer 415 may also be referred to as a top insulating layer 415 . Afterwards, photolithography and etching processes are performed to form via holes OP5 in the stack structure SK4 and the stack structure SK3. The via hole OP5 exposes the bottommost conductor layer 394 of the stacked structure SK3.

Referring to FIG. 4B, a storage layer 408 and a channel column VC4 are formed in the channel hole OP5. The storage layer 408 is formed on the sidewall of the via hole OP5. In one embodiment, the storage layer 408 is a composite layer (ONO) of oxide 408a, nitride 408b, and oxide 408c, so the storage layer 408 may also be referred to as a charge storage structure. The channel column VC4 includes a channel layer 410 , an insulating column 412 and a conductor plug 414 . The materials and forming methods of the channel layer 410 , the insulating pillars 412 and the conductor plugs 414 may be the same or different from those of the above-mentioned channel layer 110 , the insulating pillars 112 and the conductor plugs 114 . In some embodiments, the storage layer 408 , the channel pillar VC4 and the top surface of the top insulating layer 415 are substantially coplanar.

Next, a substitution process is performed. The replacement process includes removing the sacrificial layer 404 of the stacked structure SK4 to form a horizontal opening (not shown), and filling the horizontal opening with a conductor layer to form a gate layer 426 . The conductor layer serving as the gate layer 426 includes, for example, the barrier layer 422 and the metal layer 424 . The materials and forming methods of the barrier layer 422 and the metal layer 424 may be the same or different from those of the barrier layer 122 and the metal layer 124 .

Afterwards, the conductor layer 394 in the middle of the stacked structure SK3 is removed, and the insulating layers 392 located above and below the conductor layer 394 are removed to form a horizontal opening (not shown) in the stacked structure SK3. Then, the conductor layer 394' is filled in the horizontal opening. The conductor layer 394' in the horizontal opening together with the conductor layer 394 above and below it forms a source line 396. So far, the channel layer 410 is electrically connected to the source line 396 .

Thereafter, referring to FIG. 4C , a dielectric layer 430 is formed on the substrate 400 . The dielectric layer 430 is, for example, silicon oxide. In some embodiments, an etch stop layer is not included in the dielectric layer 430 . The etch stop layer is, for example, a silicon nitride layer. The ratio of the thickness T2 of the dielectric layer 430 to the thickness T1 of the top insulating layer 415 is greater than 2, eg, 2 to 4, or more. In some embodiments, the thickness T2 of the dielectric layer 430 is 140 nm to 1000 nm; the thickness T1 of the top insulating layer 415 is 70 nm to 200 nm.

In other embodiments, referring to FIG. 5 , the dielectric layer 430 includes an etch stop layer 432 . The etch stop layer 432 is between the dielectric layer 430a and the dielectric layer 430b of the dielectric layer 430 . The etch stop layer 432 is, for example, a silicon nitride layer. The ratio of the thickness T2' of the dielectric layer 430a to the thickness T1 of the top insulating layer 415 is greater than 2, for example, 2 to 4, or more. In some embodiments, the thickness T2' of the dielectric layer 430a is 30 nm to 200 nm; the thickness T1 of the top insulating layer 415 is 70 nm to 200 nm.

Next, referring to FIG. 4C , a hard mask layer MK is formed on the dielectric layer 430 . The material of the hard mask layer MK is, for example, carbon. The hard mask layer MK is patterned through a lithography and etching process to have a plurality of openings OP6.

After that, referring to FIGS. 4C to 4E , an etching process is performed to form an opening OP7 . The etching process is, for example, dry etching, wet etching or a combination thereof. Dry etching is, for example, plasma etching. The etching process includes a main etching process ME2 and an over-etching process OE2. In some embodiments, the main etch process ME2 may be controlled using a time mode to remove a portion of the dielectric layer 430 , as shown in FIG. 4C . The over-etching process OE2 may continue to etch the remaining dielectric layer 430 until the channel column VC4 is exposed.

However, in some embodiments, misalignment occurs during the lithography process, so that the sidewall SW7' of the opening OP7' formed by the main etching process ME2 is offset from the sidewall SW6 of the corresponding channel column VC4, as shown in FIG. 4D Show. In the subsequent over-etching process OE2, a part of the formed opening OP7 will not land on the channel column VC4, and this area is called an unlanded area UA2. If the etching rate of the unlanded area UA2 is too high, the multi-layer gate layer 426 will be etched, resulting in electrical problems. The present invention alleviates or solves the problems of misalignment and the high etching rate of the unlanded area UA2 through the selection of the etching gas in the over-etching process OE2.

Referring to FIG. 4E , the second etching gas used in the over-etching process OE2 according to the embodiment of the present invention is different from the first etching gas used in the main etching process ME2 . Both the first etching gas and the second etching gas are carbides containing fluorine. The first etching gas has a first ratio of fluorine to carbon (F/C), and the second etching gas has a second ratio of fluorine to carbon, and the second ratio is greater than the first ratio. The second etching gas used in the over-etching process OE2 has a high fluorocarbon (F/C) ratio, which can generate a by-product PM2 with a sufficient thickness (a large amount) during the etching process, such as a fluorocarbon polymer, and cover the opening OP7. to protect the channel layer 410, the storage layer 408 and the top insulating layer 415 around the channel pillar VC4, thereby slowing down the etching rate of the unlanded area UA2, or even stopping the etching of the unlanded area UA2, while the landed area LA2 continues to be etched. In this way, etching uniformity across the wafer can be ensured. In some embodiments, the first etching gas used in the main etching process ME2 includes fluorinated hydrocarbons, such as CHF ₃ , CH ₂ F ₂ , CH ₃ F or a combination thereof; the second etching gas used in the over-etching process OE2 Contains perfluorocarbons C _x F _y where y/x is less than 3. _{Perfluorocarbon CxFy such} as _C4F6 , _C4F8 , _C5F8 , _C3F8 , or _{combinations thereof} . _In some embodiments, the main etch process ME2 uses a fluorinated hydrocarbon such as _CHF3 , _CH2F2 , _CH3F , or a combination thereof, while the overetch process _{OE2 uses a perfluorocarbon CxFy such} as C _4F6 , _C4F8 , _C5F8 , _C3F8 , or combinations thereof, without the use _{of fluorinated} hydrocarbons ₍ eg, _CHF3 , _CH2F2 , _{CH3F ,} or combinations thereof ₎ . In other embodiments, the main etch process ME2 uses fluorinated hydrocarbons such as CHF ₃ , CH ₂ F ₂ , CH ₃ F or a combination thereof, while the over-etch process OE2 uses perfluorocarbons C _x F _y such as C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , C ₃ F ₈ , or combinations thereof, and fluorinated hydrocarbons (eg, CHF ₃ , CH ₂ F ₂ , CH ₃ F , or combinations thereof) are used, but The content of fluorinated hydrocarbons used in the overetch process OE2 is lower than that used in the main etch process ME2.

Furthermore, during the over-etching process OE2, diluting the oxygen concentration or reducing the oxygen flow rate with a large amount of carrier gas such as Ar can facilitate the deposition of by-product (polymer) PM2. In addition, the over-etching process OE2 is performed at a higher pressure, eg, 20 mTorr to 200 mTorr, to facilitate the deposition of by-products (eg, polymers) PM2.

In some exemplary embodiments, the main etch process ME2 includes using 60 to 80 seem of CHF ₃ , 15 to 25 seem of C ₄ F ₈ , 120 to 180 seem of Ar, and 20 to 24 seem of O ₂ at a pressure of 20 mTorr; The overetch process OE2 involves the use of 15 to 20 seem of _C4F6 , ₈ to 12 seem of _C4F8 , 600 to ₈₀₀ seem of Ar, and 20 to 30 seem of _O2 at a pressure of 30 mTorr.

Referring to FIG. 4F, the mask layer MK is removed. The mask layer MK can be removed by ashing, wet etching, or a combination thereof. Afterwards, the cleaning process is performed. After the cleaning process is performed, the bottom of the opening OP7 exposes the channel column VC4 and the storage layer 408 and the top insulating layer 415 around the channel column VC4. In other words, the over-etch process OE2 may stop at the top insulating layer 415 above the topmost gate layer 426 . In the embodiment of the present invention, the contour of the upper side wall SW7 _U of the formed opening OP7 is different from the contour of the lower side wall SW7 _L. The outline of the upper side wall SW7 _U is substantially straight, and the outline of the lower side wall SW7 _L is a curved line.

During the over-etching process OE2, the by-product PM2 covers the bottom of the opening OP7 to protect the channel layer 410, the storage layer 408 and the top insulating layer 415 around the channel column VC4, thereby slowing down the etching rate of the unlanded area UA2, even The etching of the unlanded area UA2 is stopped, as shown in Figure 4E. Therefore, in the embodiment of the present invention, it is not necessary to increase the thickness T1 of the top insulating layer 415 in order to prevent the topmost gate layer 426 from being damaged by etching. Therefore, the dielectric layer 430 and the top insulating layer 415 may have a larger thickness ratio (T2/T1).

Next, referring to FIG. 4G, a contact window C4 is formed in the contact window opening OP7. The contact window C4 is electrically connected to the conductor plug 414 of the channel column VC4. In one embodiment, each of the contact windows C4 may include a barrier layer 416 and a conductor layer 418 . The material of the barrier layer 416 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the conductor layer 418 is, for example, tungsten (W).

In some embodiments, the contact window C4 wraps the top angle α of the conductor plug 414 and is partially embedded between the via post VC4 and the storage layer 408 . More specifically, the contact window C4 includes a main body portion MP and an extension portion EP. The main body portion MP is landed on the top surface of the conductor plug 414 , and its sidewalls are surrounded by the dielectric layer 430 . The extension part EP is located below the main body part MP and is connected to the main body part MP. The extension EP lands on a portion of the storage layer 408 . The sidewalls of the extension EP are covered by the conductor plugs 414 and the storage layer 408 . The bottom surface of the extension EP is higher than the top surface of the topmost gate layer 426 . In some embodiments, the height H2 of the body portion MP is approximately equal to the thickness T2 of the dielectric layer 430 ; the height H1 of the extension portion EP is less than or equal to the thickness T1 of the top insulating layer 415 .

To sum up, the embodiments of the present invention can alleviate or solve the problems of misalignment and high etching rate of the unlanded area by the arrangement of the grounded conductor post and the selection of the etching gas in the over-etching process.

10: Semiconductor substrate 12: Doping region 20: Element layer 30: Metal interconnect structure 32, 103, 130, 430, 430a, 430b, DL1, DL2, DL3: Dielectric layer 33: Metal interconnect 34: Insert Plug 36: wires 92, 102, 202, 302, 392, 402: insulating layer 94, 94', 394, 394', 418: conductor layer 95: dielectric layer 96, 396: source line 100, 400: substrate 104 , 204, 304, 404: sacrificial layer 104: second insulating layer 106, O1, OP1, OP2, OP2', OP3, OP6, OP7, OP7': openings 108, 408: storage layer 110, 410: channel layer 112, 412: insulating posts 114, 414: conductor plugs 115: insulating cap layer 415: insulating cap layer/top insulating layer 122, 416, 422: barrier layers 124, 424: metal layers 126, 426, 126 ₁ , 126 ₂ : Gate layers 408a, 408c: Oxide 408b: Nitride 415: Top insulating layer 432: Etch stop layer B: Blocks C1, C2, C4: Contacts CL1, CL2: Center line CR: Conductive region DCC: Conductor Pillar EP: Extension H1, H2: Height LA1, LA2: Landing area ME1, ME2: Main etching process MK: Mask layer MP: Main body OE1, OE2: Over-etching process OP4, OP5: Via hole P1: First level P2: Second level P3: Third level PM1, PM2: By-products R1, R2, R3: Regions SC1, SC2, SC3: Ladder structure SK1, SK2, SK3, SK4: Stacked structure SLT: Array by walls SP1, SP2: Sacrificial pillars SW2 _L , SW3 _L , SW7 _L : lower side walls SW2 _U , SW3 _U , SW7 _U : upper side walls SW2 ′, SW7 ′: side walls T1 , T2 , T2 ′: thicknesses UA1 , UA2 : non-landing areas VC1 , VC4 : Channel column d1, d2: distance α: vertex angle I-I': line S1: first section S2: second section S3: third section

1A to 1N are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. 2A is a partial cross-sectional schematic diagram of a three-dimensional memory device according to an embodiment of the present invention. 2B is a schematic partial cross-sectional view of a three-dimensional memory device according to another embodiment of the present invention. 3A-3F are schematic cross-sectional views of conductor posts according to various embodiments of the present invention. Fig. 3G is a partial perspective schematic view of the line I-I' of Fig. 1M. 4A to 4G are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. 5 is a schematic cross-sectional view of another three-dimensional memory device according to an embodiment of the present invention.

DL1, DL2: Dielectric layer

92, 102, 202: insulating layer

94: Conductor layer

95: Dielectric layer

100: base

204: Sacrificial Layer

104: Insulation layer

CR: Conductive region

DCC: Conductor Post

LA1: Landing Area

UA1: Unlanded area

OE1: Over-etching process

OP2: Opening

SP1: Sacrificial Column

SK1, SK2: Stacked structure

P1: Level 1

P2: Second level

PM1: By-products

Claims (9)

A memory device includes: a first stack structure including a first insulating layer and a first conductor layer on the first insulating layer; a second stack structure on the first stack structure, the second stack structure The stacked structure includes a plurality of second conductor layers and a plurality of second insulating layers alternated with each other; a channel column passes through the second stacked structure and extends to the first stacked structure; a storage layer is located on the channel column and the first stack structure and between the channel post and the second stack structure; and a conductor post, disposed in the first conductor layer, and electrically connected to the first conductor layer and the substrate connected, wherein the conductor post is electrically insulated from the plurality of second conductor layers and passes through the first insulating layer and is grounded. The memory device of claim 1, wherein a top surface of the conductor post is lower than a top surface of the channel post and a length of the conductor post is less than a length of the channel post. The memory device of claim 1, wherein the channel column includes a first segment and a second segment, and a centerline of the first segment has a non-zero distance from a centerline of the second segment. A memory element, comprising: a stacked structure located above a substrate, the stacked structure comprising alternating a plurality of conductor layers and a plurality of insulating layers; a top insulating layer, located on the stacked structure; a channel column, located in the top insulating layer and the stacked structure; a storage layer, located on the channel column and the multiple Between the conductor layers; a dielectric layer on the top insulating layer; and a contact window, passing through the dielectric layer and the top insulating layer, and electrically connected to the via post, wherein the dielectric The ratio of the thickness of the layer to the thickness of the top insulating layer is greater than 2. The memory element of claim 4, wherein the dielectric layer is free of an etch stop layer. A method for manufacturing a memory element, comprising: forming a first stack structure on a substrate, the first stack structure comprising a plurality of first conductor layers and a plurality of first insulating layers alternated with each other; forming in the first stack structure a conductor post to ground one of the plurality of first conductor layers; a first level of a second stack structure is formed on the first stack structure, and the first level of the second stack structure includes A plurality of sacrificial layers and a plurality of second insulating layers alternate with each other; a first opening is formed in the first level of the second stack structure and the first stack structure; a sacrificial layer is formed in the first opening column, the sacrificial column is provided by the first The one of the conductor layers is electrically connected to the conductor post and then grounded; the second level of the second stack structure is formed on the first level of the second stack structure; and a patterning process is performed to A second opening is formed in the second level of the second stack structure, wherein the second opening exposes the sacrificial column; the sacrificial column is removed to expose the first opening forming a storage layer and a channel column in the first opening and the second opening; and replacing part of the plurality of first insulating layers and part of the plurality of first conductor layers with a plurality of second conductor layers , making the remaining plurality of first conductor layers and the plurality of second conductor layers form source lines. The method for manufacturing a memory device according to claim 6, wherein the patterning process includes a plasma etching process. The method for manufacturing a memory device according to claim 7, wherein the plasma etching process includes a main etching process and an over-etching process, and a first etching gas used in the main etching process and a second etching gas used in the over-etching process Etching gases are different. The method of manufacturing a memory element according to claim 8, wherein the first etching gas has a first ratio of fluorine to carbon, the second etching gas has a second ratio of fluorine to carbon, and the second ratio greater than the first ratio.

Images