TWI773036B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a semiconductor structure is provided, including: forming a thermoelectric structure on a substrate. A dielectric layer is formed on the substrate to cover the thermoelectric structure. A first photoresist pattern including a first opening is formed on the dielectric layer. The dielectric layer is etched with the first photoresist pattern as an etching mask to remove the dielectric layer under the first opening and expose an exposed region of the substrate. The first photoresist pattern is removed. A protecting layer is conformally formed on the dielectric layer and the exposed region. A second photoresist pattern including a second opening is formed on the protecting layer. The second opening is smaller than the first opening. The protecting layer is etched with the second photoresist pattern as an etching mask to remove the protecting layer under the second opening.

Description

Semiconductor structure and method of making the same

The present disclosure relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a semiconductor structure and a manufacturing method thereof capable of improving yield and reliability.

In general, a thermoelectric sensor can sense temperature by using a thermoelectric material that produces a thermoelectric effect. Different from using metal conductors with different free electron densities as thermoelectric materials, semiconductor materials with more sensitive carriers are often used as thermoelectric materials. Therefore, the resistance of different thermoelectric materials can be selected to adjust the performance of the thermal sensor.

However, in the current thermoelectric sensor, the heat-generating thermoelectric material is suspended on the substrate by providing a cavity. Since the thermoelectric material is suspended on the substrate by the cavity disposed therebetween, and the cavity itself has excellent thermal insulation properties, the temperature sensed by the thermoelectric material can be completely converted into electrical signals, so it can reduce the thermal conductivity caused by the phenomenon of thermal conductivity. Detectable temperature distortion issues.

Therefore, an etching process is used to form the cavity in the conventional manufacturing method of the thermal sensor. However, during the etching process, the pyroelectric material in the pyroelectric sensor or other layers disposed around the pyroelectric material are often damaged by the etching process, resulting in a decrease in the performance of the overall pyroelectric sensor, or even failure of the pyroelectric sensor. Thus, although existing semiconductor structures have gradually fulfilled their intended uses, they have not yet fully met the requirements in all respects. Therefore, there are still some problems to be overcome with respect to semiconductor structures that can be subsequently processed into pyroelectric sensors and methods of making them.

In view of the above-mentioned problems, some embodiments of the present disclosure use a two-stage etching process to form a protective layer that can well protect the multilayer structure on the substrate, so as to avoid the etching process from damaging the thermoelectric structure including the thermoelectric material, so that a good Reliable semiconductor structures.

According to some embodiments, methods of fabricating semiconductor structures are provided. The manufacturing method of the aforementioned semiconductor structure includes: forming a thermoelectric structure on a substrate. A dielectric layer is formed on the substrate so that the dielectric layer covers the thermoelectric structure. A first photoresist pattern is formed on the dielectric layer, and the first photoresist pattern includes a first opening. The dielectric layer is etched using the first photoresist pattern as an etch mask to remove the dielectric layer under the first opening and expose exposed regions of the substrate. The first photoresist pattern is removed. A protective layer is conformally formed on the dielectric layer and the exposed area. A second photoresist pattern is formed on the protective layer. The second photoresist pattern includes a second opening, and the second opening is smaller than the first opening. Using the second photoresist pattern as an etch mask, the protective layer is etched to remove the protective layer under the second opening.

According to some embodiments, semiconductor structures are provided. The aforementioned semiconductor structure includes a substrate, a thermoelectric structure, a dielectric layer and a protective layer. The thermoelectric structure is arranged on the substrate. The dielectric layer is disposed on the substrate and exposes exposed areas of the substrate. A dielectric layer covers the thermoelectric structure. The protective layer is disposed on the dielectric layer and covers a portion of the exposed area of the substrate.

The semiconductor structures of some embodiments of the present disclosure can be applied to various types of sensing devices. In order to make the features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are hereinafter described, together with the accompanying drawings. Details are as follows.

The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor structures. Specific examples of elements and their configurations are described below to simplify the disclosed embodiments. Of course, these are just examples, and are not intended to limit the present disclosure. For example, if the description mentions that the first element is formed on the second element, it may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. In addition, the same or similar reference numerals are used to designate the same or similar elements in the different drawings and the illustrated embodiments. In addition, the embodiments of the present disclosure may repeat reference numerals and/or letters in different examples. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed. It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or deleted for other embodiments of the method.

Referring to FIG. 1 , a substrate 100 is provided, and an insulating layer 200 is formed on the substrate 100 . In some embodiments, the substrate 100 may be a wafer, such as a silicon (Si) wafer, a bulk semiconductor, or a semiconductor-on-insulation (SOI) substrate. Generally speaking, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material, which provides an insulating layer on a silicon or glass substrate. Other types of substrates 100 include, for example, multi-layer or gradient substrates. In some embodiments, the substrate 100 may be an elemental semiconductor including silicon and germanium; the substrate 100 may also be a compound semiconductor including, for example, silicon carbide, gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide) and/or indium antimonide (indium antimonide), but not limited thereto; the substrate 100 can also be The alloy semiconductor includes, for example, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP or any combination thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate 100 may be a doped or undoped semiconductor substrate. In some embodiments, the substrate 100 may be a silicon substrate.

In some embodiments, the insulating layer 200 may optionally be formed on the substrate 100 by a deposition process. In some embodiments, the deposition process may be or may include a chemical vapor deposition (CVD) process or a thermal oxidation process. The aforementioned CVD process may be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (rapid thermal chemical vapor deposition) , RTCVD), PECVD, atomic layer deposition (atomic layer deposition, ALD) or other suitable CVD process.

In some embodiments, the insulating layer 200 may be or may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable insulating materials, but the present disclosure is not limited thereto. For example, the insulating layer 200 may be silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, the insulating layer 200 may be silicon nitride. In some embodiments, the insulating layer 200 acts as an electrical connection to isolate the substrate 100 and other layers, elements or features subsequently formed over the insulating layer 200 .

Referring to FIG. 2 , the thermoelectric structure 300 is formed on the substrate 100 . Specifically, the thermoelectric structure 300 is formed on the insulating layer 200 so that the insulating layer 200 is located between the substrate 100 and the thermoelectric structure 300 . In some embodiments, the thermoelectric structure 300 is a structure capable of producing a thermoelectric effect. In some embodiments, the thermoelectric structures 300 are formed on the insulating layer 200 in an island shape. In some embodiments, different numbers of thermoelectric structures 300 can be provided in the subsequently formed dielectric layer according to the user's needs and the expected size of the thermoelectric sensing unit. In some embodiments, the plurality of thermoelectric structures 300 may be disposed on the insulating layer 200 at substantially the same distance. In some embodiments, the number of thermoelectric structures 300 as shown in FIG. 2 should not be used to limit the number of thermoelectric structures of the present disclosure.

In some embodiments, the thermoelectric structure 300 may include a thermoelectric material layer 310 and a thermoelectric insulating layer 320 . In some embodiments, the thermoelectric material layer 310 may be or may include aluminum, chromium, gold, copper, platinum, nickel, bismuth, Antimony, doped silicon such as n-type polysilicon or p-type polysilicon, combinations of the above, or other suitable thermoelectric materials. In some embodiments, since n-type polysilicon has a very low seebeck coefficient, the thermoelectric material layer 310 may be n-type polysilicon. In some embodiments, the resistance value of the thermoelectric material layer 310 is adjusted by the type and doping concentration of the dopant, so as to control the thermoelectric effect of the subsequently formed semiconductor structure.

In some embodiments, thermoelectric insulating layer 320 may comprise the same or different materials as insulating layer 200 . In some embodiments, the thermoelectric insulating layer 320 may be or may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable insulating material, but the present disclosure is not limited thereto. For example, the thermoelectric insulating layer 320 may be silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, the thermoelectric insulating layer 320 may be silicon nitride. In some embodiments, the process of forming the thermoelectric insulating layer 320 may be the same as or different from the process of forming the insulating layer 200 . In some embodiments, the thermoelectric insulating layer 320 covers the thermoelectric material layer 310 , and the thermoelectric insulating layer 320 exposes a portion of the insulating layer 200 .

Specifically, in some embodiments, a thermoelectric material is formed on the insulating layer 200 , and then a patterned photoresist pattern is formed on the thermoelectric material, and the thermoelectric material is etched by using the patterned photoresist pattern as an etching mask, to form the thermoelectric material layer 310 . After that, the aforementioned patterned photoresist pattern layer for forming the thermoelectric material layer 310 is removed. Then, a thermoelectric insulating material is formed on the thermoelectric material layer 310 , for example, a thermoelectric insulating material is conformally formed on the thermoelectric material layer 310 and the insulating layer 200 . Next, a patterned photoresist pattern is formed on the thermoelectric insulating material, and the thermoelectric insulating material is etched by using the patterned photoresist pattern as an etching mask to form a patterned thermoelectric insulating material, that is, the thermoelectric insulating layer 320 . Similarly, the aforementioned patterned photoresist pattern layer for forming the thermoelectric insulating layer 320 is removed. In some embodiments, the aforementioned thermoelectric insulating layer 320 covers the thermoelectric material layer 310 and exposes a portion of the insulating layer 200 .

Referring to FIG. 3 , a first dielectric layer 410 is formed on the substrate 100 so that the first dielectric layer 410 covers the thermoelectric structure 300 . Specifically, the first dielectric layer 410 is formed on the insulating layer 200 and the thermoelectric structure 300 . In other words, the thermoelectric structure 300 may be disposed in the first dielectric layer 410 . In some embodiments, the first dielectric layer 410 may be or may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable dielectric materials, but the present disclosure is not limited thereto. For example, the first dielectric layer 410 may be silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, the first dielectric layer 410 may be silicon oxide. In some embodiments, the first dielectric layer 410 may serve as a functional layer in a subsequently formed semiconductor structure, for example, may serve as an interlayer dielectric layer or an insulating layer.

Referring to FIG. 4 , a second dielectric layer 420 and a third dielectric layer 430 may be further disposed on the first dielectric layer 410 . In some embodiments, other dielectric layers may be further included. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may serve as functional layers having the same or different functions as the first dielectric layer 410 in a subsequently formed semiconductor structure. In some embodiments, the thermoelectric structure 300 may be disposed in the first dielectric layer 410 , the second dielectric layer 420 and the third dielectric layer 430 at the same time, or may be disposed only in the first dielectric layer 410 and the second dielectric layer 430 in the electrical layer 420 . In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may include the same or different materials as the first dielectric layer 410 . In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may be silicon oxide. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may be formed by the same or different processes as the first dielectric layer 410 . In some embodiments, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 may be formed in the same or different processes. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may be omitted.

For the sake of detailed description, the following description will be given in the case of including the first dielectric layer 410 , the second dielectric layer 420 and the third dielectric layer 430 . Hereinafter, the first dielectric layer 410 , the second dielectric layer 420 and the third dielectric layer 430 are collectively referred to as “dielectric layers”.

Referring to FIG. 5, a first photoresist pattern 500 is formed on the above-mentioned dielectric layer, and the first photoresist pattern 500 includes a first opening OP1. In some embodiments, the first photoresist pattern 500 is formed on the third dielectric layer 430, and a portion of the third dielectric layer 430 is exposed through the first opening OP1. In some embodiments, the first photoresist pattern 500 covers the thermoelectric material 310 and the thermoelectric insulating layer 320 , in other words, the thermoelectric material 310 and the thermoelectric insulating layer 320 are located under the first photoresist pattern 500 . In some embodiments, the thermoelectric material 310 and the thermoelectric insulating layer 320 are not disposed under the first opening OP1 , so the complete structure of the thermoelectric material 310 and the thermoelectric insulating layer 320 can be maintained.

In some embodiments, the first photoresist pattern 500 may be or may include oxide, nitride, or a combination thereof. In some embodiments, the step of forming the first photoresist pattern 500 on the third dielectric layer 430 may further include: depositing a first photoresist pattern material layer such as an oxide layer on the third dielectric layer 430; forming A photoresist layer is placed on the first photoresist pattern material layer; the photoresist layer is exposed to light as required to obtain a patterned photoresist layer; and the patterned photoresist layer is used as an etching mask to etch the first photoresist pattern material layer to form a patterned first photoresist pattern material layer to obtain the first photoresist pattern 500 on the third dielectric layer 430 . It can be understood that suitable photoresist pattern materials can be matched according to process conditions, so the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 6 , the first photoresist pattern 500 is used as an etching mask, and the insulating layer 200 and the dielectric layer are etched to remove the insulating layer 200 and the dielectric layer located under the first opening OP1 of the first photoresist pattern 500 layer, and expose the exposed area of the substrate 100 . That is, the insulating layer 200 , the first dielectric layer 410 , the second dielectric layer 420 and the third dielectric layer 430 located under the first opening OP1 of the first photoresist pattern 500 are removed, and the substrate 100 is exposed part. In some embodiments, the dielectric layer is etched to form a plurality of dielectric structures disposed on the substrate 100 in an island shape. In some embodiments, vias are formed between the plurality of dielectric structures, for example, tapered vias with inclined sidewalls, or vias with vertical sidewalls.

In some embodiments, the substrates 100 exposed through the first photoresist patterns 500 have a first width W1 between them, and the aforementioned first width W1 corresponds to the width of the first opening OP1 . In some embodiments, the shape of the first opening OP1 can be any suitable shape, for example, a square, a rectangle, a polygon, and an irregular shape, and the first width W1 is only the first opening OP1 as shown in FIG. 5 . examples in cross-sectional views, and should not limit the present disclosure.

Referring to FIG. 7, the first photoresist pattern 500 is removed by an etching process. In some embodiments, the etching process may be or may include dry etching, wet etching, or other etching methods (eg, reactive ion etching). In some embodiments, the etching process may also be pure chemical etching (plasma etching), pure physical etching (ion milling), or a combination thereof. In some embodiments, a dry etching process is used to remove the first photoresist pattern 500 , and also remove a portion of the dielectric layer and a portion of the insulating layer 200 , that is, after removing the first photoresist pattern 500 At the same time, the insulating layer 200 , the first dielectric layer 410 , the second dielectric layer 420 and the third dielectric layer 430 are removed. In some embodiments, the area of the removed third dielectric layer 430 may be larger than the area of the removed second dielectric layer 420; the area of the removed second dielectric layer 420 may be larger than the area of the removed second dielectric layer 420 and the area of the removed first dielectric layer 410 may be larger than the area of the removed insulating layer 200 . In some embodiments, the insulating layer 200 , the first dielectric layer 410 , the second dielectric layer 420 , and the third dielectric layer 430 may have a trapezoidal shape with a narrow upper portion and a wider lower portion.

In detail, in some embodiments, the parameters of the dry etching process are adjusted such that the area of the top surface of the dielectric layer is smaller than the area of the bottom surface of the dielectric layer. In some embodiments, the dielectric layer has sloped side surfaces S. FIG. In some embodiments, the dielectric layer has a gradually decreasing area along a direction away from the substrate 100 . For example, the area of the top surface of the third dielectric layer 430 is made smaller than the area of the bottom surface of the first dielectric layer 410, and the first dielectric layer 410, the second dielectric layer 420 and the third dielectric layer are made The 430 collectively have inclined side surfaces S with substantially the same slope. In some embodiments, the smaller angle α between the aforementioned inclined side surface S and the top surface of the dielectric layer may be 45˜85 degrees, although the present disclosure is not limited thereto. In some embodiments, the smaller angle α may be substantially 90 degrees. In some embodiments, the dielectric layer and the insulating layer 200 together have an inclined side surface S, and the smaller angle α between the inclined side surface S and the top surface of the dielectric layer may be 45-85 degrees.

In some embodiments, a plurality of island-shaped dielectric structures may be formed as shown in FIG. 6 and FIG. 7 . The maximum area of each dielectric structure in the plurality of island-shaped dielectric structures, for example, the area of the bottom surface of the dielectric structure is substantially the same as the area of the first photoresist pattern 500. However, the present disclosure does not limited to this. In other embodiments, a plurality of island-shaped dielectric structures can be formed by adjusting parameters in the etching process, such as the etching selectivity ratio. The minimum area of each of the plurality of island-shaped dielectric structures, for example, the area of the top surface of the dielectric structure is substantially the same as the area of the first photoresist pattern 500 .

Referring to FIG. 8 , a protective layer 600 is compliantly formed on the dielectric layer and the exposed area of the substrate 100 to cover the dielectric layer and the exposed area of the substrate 100 . In some embodiments, the protective layer 600 is formed on the top surface of the exposed area of the substrate 100 , on the inclined side surfaces S of the dielectric layer and the insulating layer 200 , and on the top surface of the dielectric layer, that is, the protective layer The 600 series is conformally formed on the dielectric layer. In some embodiments, the protective layer 600 is formed by the aforementioned deposition process.

In the present disclosure, a "protective layer" refers to a layer with better etching resistance to a specific etchant and/or etching gas, that is, a layer with a lower etching selectivity ratio. In some embodiments, the protective layer 600 may be or may include oxides, nitrides, oxynitrides, combinations thereof, or any other suitable materials, but the present disclosure is not limited thereto. For example, the protective layer 600 may be silicon nitride.

It should be noted that, since the dielectric layer and the insulating layer 200 have inclined side surfaces S, and the inclined side surfaces S and the top surface of the dielectric layer have a specific angle of 45-85 degrees, the protective layer is formed compliantly When 600 is formed on the dielectric layer, although the thickness of the protective layer 600 formed on the inclined side surface S may still be slightly smaller than the thickness of the protective layer 600 formed on the dielectric layer and the top surface of the substrate 100, it is formed on the inclined side surface S. The thickness of the protective layer 600 on the side surface S is very close to the thickness of the protective layer 600 formed on the dielectric layer and the top surface of the substrate 100 . Therefore, the protective layer 600 can effectively protect the dielectric layer and the insulating layer 200 under the inclined side surface S from being damaged by the etching process during subsequent multiple etching processes for forming the pyroelectric sensing device.

Referring to FIG. 9, a second photoresist pattern 700 is formed on the protective layer 600, and the second photoresist pattern 700 includes a second opening OP2. In some embodiments, the second opening OP2 of the second photoresist pattern 700 is smaller than the first opening OP1 of the first photoresist pattern 500 . In some embodiments, the second photoresist pattern 700 covers a portion of the protective layer 600 and exposes another portion of the protective layer 600 . In some embodiments, the second opening OP2 exposes a portion of the protection layer 600 , and the area of the protection layer 600 exposed through the second opening OP2 is smaller than the area of the substrate 100 exposed through the first opening OP1 . In some embodiments, the second photoresist pattern 700 covers a portion of the exposed area of the substrate 100 . In some embodiments, the second photoresist pattern 700 also covers the thermoelectric material 310 and the thermoelectric insulating layer 320 , in other words, the thermoelectric material 310 and the thermoelectric insulating layer 320 are also located under the second photoresist pattern 700 .

In some embodiments, the second photoresist pattern 700 may include the same or different materials as the first photoresist pattern 500 . In some embodiments, the second photoresist pattern 700 may be or may include oxide, nitride, or a combination thereof. In some embodiments, the process of forming the second photoresist pattern 700 may be the same as or different from the process of forming the first photoresist pattern 500 . It can be understood that suitable photoresist pattern materials and processes can be matched according to process conditions, so the embodiments of the present disclosure are not limited thereto.

It should be noted that the area covered by the second photoresist pattern 700 on the protective layer 600 is larger than the area covered by the first photoresist pattern 500 on the dielectric layer. In other words, all the features previously located under the first photoresist pattern 500 All are located under the second photoresist pattern 700 . In some embodiments, the area where the first photoresist pattern 500 is projected onto the substrate 100 is located in the area where the second photoresist pattern 700 is projected onto the substrate 100 , that is, the area where the second photoresist pattern 700 is projected onto the substrate 100 covers the area where the second photoresist pattern 700 is projected onto the substrate 100 The first photoresist pattern 500 is projected to a region of the substrate 100 .

It should also be noted that, in some embodiments, the second photoresist pattern 700 covers the inclined side surface S and the top surface of the dielectric layer, and covers the protective layer 600 adjacent to the inclined side surface S and located on the substrate 100 . part. That is to say, the second photoresist pattern 700 covers even a part of the protective layer 600 adjacent to the inclined side surface S and on the substrate 100 in addition to covering all the features previously located under the first photoresist pattern 500 , and thus can The aforementioned portion of the protective layer 600 adjacent to the inclined side surface S and located on the substrate 100 remains, in other words, the protective layer 600 may include an extension provided on the exposed portion of the substrate 100 to further protect the substrate 100 by the extension Not damaged by subsequent processes. For example, according to some embodiments of the present disclosure, since the aforementioned portion of the protective layer 600 adjacent to the inclined side surface S is still disposed on the substrate 100 , subsequent multiple etching processes are performed in order to form the pyroelectric sensing device. When etchant and/or etching gas is easily concentrated near the substrate 100, so that the features near the substrate 100 are more easily damaged, the aforementioned portion of the protective layer 600 can still effectively protect the features near the substrate 100 from being etched destruction of the process.

Referring to FIG. 10 , the second photoresist pattern 700 is used as an etching mask, and the protective layer 600 is etched to remove the protective layer 600 located under the second opening OP2 of the second photoresist pattern 700 . In some embodiments, the substrates 100 exposed by the second photoresist patterns 700 have a second width W2 between them, and the aforementioned second width W2 corresponds to the width of the second opening OP2 . In some embodiments, since the semiconductor structure according to some embodiments of the present disclosure can be subsequently processed into a pyroelectric sensing device or a pyroelectric sensing unit, the second width W2 can be a plurality of pyroelectric sensing units subsequently processed. separation distance between. That is, the size of the pyroelectric sensing unit can be defined by the second width W2, that is, by the second opening OP2.

In some embodiments, since there is a width difference W3 between the second width W2 and the first width W1, the width of the aforementioned portion of the protective layer 600 adjacent to the inclined side surface S and located on the substrate 100 may be substantially the same as Width difference W3.

Referring to FIG. 11 , the second photoresist pattern 700 is removed by an etching process, and a semiconductor structure 1 according to some embodiments of the present disclosure is obtained. In some embodiments, the process of removing the second photoresist pattern 700 may be the same as or different from the process of removing the first photoresist pattern 500 . In some embodiments, the second photoresist pattern 700 is removed, leaving features under the second photoresist pattern 700 . In some embodiments, after the second photoresist pattern 700 is removed, the protective layer 600 may be disposed on the substrate 100 , the insulating layer 200 and the dielectric layer, and a part of the substrate 100 is exposed, that is, the protective layer 600 may correspond to The width of the width difference W3 is disposed on the substrate 100 adjacent to the inclined side surface S, and is also disposed on the inclined sides of the insulating layer 200 , the first dielectric layer 410 , the second dielectric layer 420 and the third dielectric layer 430 On the surface S and on the top surface of the third dielectric layer 430 , and expose a portion of the substrate 100 . In some embodiments, a portion of the protective layer 600 may extend along the top surface of the substrate 100 in a direction away from the thermoelectric structure including the thermoelectric material 310 and the thermoelectric insulating layer 320 . In some embodiments, the width of the protective layer 600 extending in a direction away from the thermoelectric structure corresponds to the aforementioned width difference W3.

Continuing from the above, a schematic cross-sectional view of further processes performed on the semiconductor structure 1 is further described below.

Referring to FIG. 12 , a via hole CT is formed penetrating the protective layer 600 and exposing the thermoelectric structure including the thermoelectric material 310 and the thermoelectric insulating layer 320 .

Referring to FIG. 13 , the conductive material is filled in the via hole CT to form a contact plug 800 in contact with the thermoelectric structure including the thermoelectric material 310 and the thermoelectric insulating layer 320 . In some embodiments, the contact plug 800 is disposed in the dielectric layer, that is, the contact plug 800 is disposed in the first dielectric layer 410 , the second dielectric layer 420 and the third dielectric layer 430 . In some embodiments, the conductive material can be or can include a metallic material, a conductive material, or other suitable conductive material. In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process may be further performed and/or a metal layer formation process may be further performed.

Referring to FIG. 14 , a first etching process 910 is performed on the semiconductor structure 1 of some embodiments of the present disclosure to form trenches 920 on the substrate 100 exposed by the protective layer 600 to obtain the semiconductor structure 2 . In some embodiments, the trench 920 is disposed in another portion of the exposed area of the substrate 100 . In some embodiments, the trenches 920 are disposed on both sides of the thermoelectric structure including the thermoelectric material 310 and the thermoelectric insulating layer 320 . In some embodiments, the trenches 920 may be provided in pairs on both sides of the thermoelectric structure. In some embodiments, the first etching process 910 may be the same as or different from the aforementioned etching process. In some embodiments, after the first etching process 910 is performed, the sidewalls of the trenches 920 are substantially aligned with the side surfaces of the protective layer 600 on the exposed area of the substrate 100 , in other words, by the exposed area of the substrate 100 The extended portion of the protective layer 600 on the substrate 100 protects the substrate 100 from being damaged by the first etching process 910 .

In some embodiments, since the thickness of the protective layer 600 on the inclined side surface S is close to the thickness of the protective layer 600 on the dielectric layer and the top surface of the substrate 100 , the protective layer 600 can effectively prevent the first etching process 910 Destruction of features under protective layer 600. As shown in FIG. 14, since the protective layer 600 with the first thickness T1 is disposed on the substrate 100, and the protective layer 600 and the substrate 100 have different etching selectivity ratios, even if the trenches with the second thickness T2 have been formed, On the exposed substrate 100, features under the protective layer 600 are still protected from damage. In addition, in some embodiments, since the protective layer 600 includes a portion adjacent to the inclined side surface S and located on the substrate 100 , the etchant and/or the etching gas used in the first etching process 910 may be affected by gravity or density. When concentrated near the substrate 100 , the protective layer 600 can still effectively protect the features located under the protective layer 600 .

Referring to FIG. 15 to FIG. 17, through the second etching process 930, along the direction from the protective layer 600 to the substrate 100, and through the aforementioned trench 920, the exposed substrate 100 is etched to form a cavity 940, and obtained The semiconductor structure 3 can be used as a thermoelectric induction device. In some embodiments, the cavity 940 is located below the thermoelectric structure including the thermoelectric material 310 and the thermoelectric insulating layer 320 . In some embodiments, the cavity 940 allows pairs of the aforementioned grooves 920 to communicate with each other. In some embodiments, the size of the pyroelectric sensing unit may be defined by the cavity 940 . In some embodiments, the second etching process 930 may be the same as or different from the aforementioned etching process. Similarly, even if the second etching process 930 is further performed, the protective layer 600 can still effectively protect the features located under the protective layer 600 .

In some embodiments, the second etching process 930 is an anisotropic etching process. In some embodiments, since the semiconductor structure 3 of the present disclosure includes the cavity 940 , the semiconductor structure 3 of the present disclosure can be used as a floating arm supported pyroelectric sensing device as shown in FIG. 16 . In detail, since the semiconductor structure 3 has the trench 920 and the cavity 940 , the thermoelectric structure 300 disposed on the insulating layer 200 can be suspended above the cavity 940 to serve as a floating arm supported thermoelectric sensing device. In some embodiments, the number of pyroelectric sensing units that can be included in one floating arm in the floating arm-supported pyroelectric sensing device can be determined according to the quantity of the thermoelectric structures included in the semiconductor structure 3 . In some embodiments, the floating arm supported thermoelectric sensing device may include one floating arm, two floating arms, four floating arms or eight floating arms, but the present disclosure is not limited thereto. As shown in FIG. 17 , the floating-arm-supported pyroelectric sensing device may include only one floating arm, and the aforementioned one floating arm may include a plurality of semiconductor structures 3 arranged in parallel. In some embodiments, if the floating arm supported thermoelectric sensing device may include four floating arms, the four floating arms may be arranged in an X-shape when viewed from a top view.

To sum up, according to some embodiments of the present disclosure, the present disclosure uses a two-stage etching process, that is, using photoresist patterns with openings of different sizes as etching masks for etching, to form a substrate that can well protect A protective layer of a multilayer structure such as an insulating layer, a first dielectric layer, a second dielectric layer, and a third dielectric layer on the upper layer is used to provide a semiconductor structure with good reliability and a manufacturing method thereof. In some embodiments, the area where the first photoresist pattern with the larger opening size, that is, the coverage area is smaller, is projected onto the substrate is smaller than the area where the second photoresist pattern with the smaller opening size, that is, the coverage area is larger, is projected onto the substrate Therefore, in addition to protecting all the features corresponding to the first photoresist pattern under the protective layer, the protective layer adjacent to the inclined side surface and disposed on the substrate can further avoid etching damage that is easily generated adjacent to the substrate.

Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can learn some implementations from the present disclosure. In the disclosure of the examples, it is understood that processes, machines, manufactures, compositions of matter, devices, methods and steps developed in the present or in the future, as long as substantially the same functions can be implemented or substantially the same results can be obtained in the embodiments described herein. Some embodiments of the present disclosure are used. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods and steps. In addition, each claimed scope constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each claimed scope and the embodiments.

Several embodiments are summarized above, so that those with ordinary knowledge in the technical field to which the present invention pertains can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present invention pertains should appreciate that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and they can, without departing from the spirit and scope of the present disclosure, Make all kinds of changes, substitutions, and substitutions.

1: Semiconductor structure 100: Substrate 200: Insulation layer 300: Thermoelectric Structures 310: Thermoelectric Material Layer 320: Thermoelectric insulating layer 410: First Dielectric Layer 420: Second Dielectric Layer 430: Third Dielectric Layer 500: First photoresist pattern 600: protective layer 700: Second photoresist pattern 800: Contact plug 910: The first etching process 920: Groove 930: Second etching process 940: Cavity α: included angle CT: Through hole OP1: The first opening OP2: Second Opening S: Sloped side surface T1: first thickness T2: Second thickness W1: first width W2: Second width W3: Width difference

With the following detailed description in conjunction with the accompanying drawings, we can better understand the viewpoints of the embodiments of the present disclosure. Notably, according to standard industry practice, some features may not be drawn to scale. In fact, the dimensions of various components may be increased or decreased for clarity of discussion. FIGS. 1-11 are schematic cross-sectional views illustrating the formation of a semiconductor structure at various stages according to some embodiments of the present disclosure; and FIGS. 12 to 15 are schematic cross-sectional views illustrating further processes performed on the semiconductor structure 1 according to some embodiments of the present disclosure. FIGS. 16 to 17 are schematic diagrams and top views, respectively, illustrating further processes performed on the semiconductor structure 1 according to some embodiments of the present disclosure.

1: Semiconductor structure 100: Substrate 200: Insulation layer 310: Thermoelectric Material Layer 320: Thermoelectric insulating layer 410: First Dielectric Layer 420: Second Dielectric Layer 430: Third Dielectric Layer 600: protective layer S: Sloped side surface

Claims (16)

A method of manufacturing a semiconductor structure, comprising: forming a thermoelectric structure on a substrate; forming a dielectric layer on the substrate so that the dielectric layer covers the thermoelectric structure; forming a first photoresist pattern on the dielectric On the electrical layer, the first photoresist pattern includes a first opening; the first photoresist pattern is used as an etching mask, and the dielectric layer is etched to remove the dielectric layer under the first opening and exposing an exposed area of the substrate; removing the first photoresist pattern; conformally forming a protective layer on the dielectric layer and the exposed area; forming a second photoresist pattern on the protective layer, the first photoresist pattern The two photoresist patterns include a second opening, and the second opening is smaller than the first opening; and the second photoresist pattern is used as an etching mask, and the protective layer is etched to remove the underside of the second opening. The protective layer exposes the substrate. The manufacturing method of claim 1, wherein the area where the first photoresist pattern is projected onto the substrate is located in the area where the second photoresist pattern is projected onto the substrate. The manufacturing method of claim 1, wherein the step of removing the first photoresist pattern further comprises: removing a portion of the dielectric layer so that the top surface of the dielectric layer is smaller than the bottom surface of the dielectric layer, and The dielectric layer is made to have an inclined side surface. The manufacturing method of claim 3, wherein a smaller angle between the inclined side surface and the top surface of the dielectric layer is 45-85 degrees. The method of manufacture as claimed in claim 3, wherein the protective film is compliantly formed In the step of forming a protective layer on the dielectric layer and the exposed area, the protective layer is formed on the top surface of the exposed area, on the inclined side surface and on the top surface of the dielectric layer. The manufacturing method of claim 3, wherein the second photoresist pattern covers the inclined side surface and the top surface of the dielectric layer, and covers a portion of the protective layer adjacent to the inclined side surface and on the exposed area. The manufacturing method of claim 1, wherein: in the step of forming the first photoresist pattern on the dielectric layer, the first photoresist pattern is located above the thermoelectric structure; and in the step of forming the second photoresist pattern on the In the step on the protective layer, the second photoresist pattern is located above the thermoelectric structure. The manufacturing method of claim 1, further comprising: removing the second photoresist pattern; forming a via hole, the via hole penetrating the protective layer and exposing the thermoelectric structure; and filling a conductive material in the via hole, to form a contact plug in contact with the thermoelectric structure. The manufacturing method of claim 1, wherein before the step of forming the thermoelectric structure on the substrate, an insulating layer is formed on the substrate, and the insulating layer is located between the substrate and the thermoelectric structure. A semiconductor structure, comprising: a substrate: a thermoelectric structure disposed on the substrate; a dielectric layer disposed on the substrate and exposing an exposed region of the substrate, and the dielectric layer covering the thermoelectric structure; and A protective layer is disposed on the dielectric layer and covers a part of the exposed area of the substrate and exposes another part of the exposed area of the substrate. The semiconductor structure of claim 10, wherein the top surface of the dielectric layer is smaller than the bottom surface of the dielectric layer. The semiconductor structure of claim 10, wherein the dielectric layer has an inclined side surface, and the protective layer is disposed on the inclined side surface. The semiconductor structure of claim 12, wherein a smaller angle between the inclined side surface and the top surface of the dielectric layer is 45-85 degrees. The semiconductor structure of claim 10, further comprising: an insulating layer disposed between the substrate and the thermoelectric structure, and the insulating layer and the dielectric layer have an inclined side surface, the inclined side surface and the dielectric layer The smaller included angle of the top surface of the layer is 45-85 degrees. The semiconductor structure of claim 10, further comprising: a pair of trenches disposed in another portion of the exposed region and on both sides of the thermoelectric structure; and a cavity disposed in the substrate and located in the thermoelectric structure under the structure, and make the pair of grooves communicate with each other. The semiconductor structure of claim 15, wherein sidewalls of the pair of trenches are substantially aligned with side surfaces of the protective layer on the exposed region.

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