TWI771943B - Semiconductor memory device and method of perfoming a write operation - Google Patents

Abstract

Embodiments provide a semiconductor memory device capable of improving operational reliability. A semiconductor memory device according to an embodiment includes a first region (BLK) including a plurality of first wirings (SGD) arranged side by side along the first direction (X direction), and adjacent first wirings (SGD) ) separated between the first insulating film (SLT2), and the first pillar (MP) provided so as to span between the adjacent first wirings (SGD); and the second and third regions (SLT1), etc. It is provided so as to sandwich the first region (BLK) in the second direction (Y direction), and includes a second insulating film. The first pillar (MP) includes a conductive layer, a gate insulating film, and a charge accumulation layer. The number of the first wirings (SGD) arranged in the first area (BLK) is an odd number.

Description

Semiconductor memory device and method for performing writing operation

The embodiment relates to a semiconductor memory device.

There is known a semiconductor memory in which memory cells are arranged three-dimensionally.

Embodiments provide a semiconductor memory device capable of improving operational reliability. The semiconductor memory device according to the embodiment includes a first region including a plurality of first wirings arranged above the semiconductor substrate and along the in-plane direction of the semiconductor substrate, that is, in the first direction, and adjacent first wirings. A first insulating film separated from each other, a first pillar provided so as to span between adjacent first wirings; and second and third regions, which are equal to the in-plane direction of the semiconductor substrate and the first direction The second insulating film is provided so as to sandwich the first region in the different second directions, and includes a second insulating film provided on the semiconductor substrate to the height of the first wiring. The first pillar includes a conductive layer, a gate insulating film, and a charge accumulation layer. The number of the first wirings arranged in the first area is an odd number.

Hereinafter, embodiments will be described with reference to the drawings. In addition, in the following description, the common reference sign is attached|subjected to the component which has the same function and structure. 1. First Embodiment The memory system of the first embodiment will be described. Hereinafter, a memory system including a NAND (Not AND) type flash memory as a semiconductor memory device will be described as an example. 1.1 About the structure The structure of the NAND-type flash memory of the present embodiment will be described. 1.1.1 About the overall configuration First, the general overall configuration of the NAND-type flash memory of the present embodiment will be described with reference to FIG. 1 . As shown in the figure, the NAND-type flash memory 1 includes a cell array 2 , a column decoder 3 , and a sense amplifier 4 . The memory cell array 2 includes a plurality of blocks BLK. Only four blocks BLK0 to BLK3 are shown in FIG. 1 , but the number is not limited. A block BLK includes a plurality of memory cells that are associated in columns and rows and are three-dimensionally layered. Moreover, the block BLK is provided on the semiconductor substrate, and a slit SLT1 is provided between adjacent blocks. The details of the configuration of the memory cell array 2 will be described below. The column decoder 3 decodes the row address received from the outside. Then, the column decoder 3 selects the column direction of the memory cell array 2 based on the decoding result. More specifically, a voltage is applied to various wirings for selecting the column direction. When reading data, the sense amplifier 4 reads out the data read from any block BLK. In addition, when writing data, a voltage corresponding to the written data is applied to the memory cell array 2. 1.1.2 Configuration of the memory cell array 2 Next, the configuration of the memory cell array 2 of the present embodiment will be described. <About circuit configuration> First, the circuit configuration of the memory cell array 2 will be described with reference to FIG. 2 . FIG. 2 is an equivalent circuit diagram of the block BLK. As shown in the figure, the block BLK includes a plurality of memory groups MG (MG0, MG1, MG2, . . . ). Also, each memory group MG includes a plurality of NAND strings 50 . Hereinafter, the NAND strings of the even-numbered memory groups MGe (MG0, MG2, MG4, ...) are referred to as NAND strings 50e, and the NAND strings of the odd-numbered memory groups MGo (MG1, MG3, MG5, ...) are referred to as NAND strings NAND string 50o. Each NAND string 50 includes, for example, eight memory cell transistors MT ( MT0 - MT7 ) and selection transistors ST1 and ST2 . The memory cell transistor MT has a control gate and a charge accumulation layer to store data non-volatilely. Furthermore, the memory cell transistor MT is connected in series between the source electrode of the selection transistor ST1 and the drain electrode of the selection transistor ST2. The gates of the selection transistors ST1 in each memory group MGe are respectively connected to the selection gate lines SGD ( SGD0 , SGD1 , . . . ). The selection gate lines SGD series are independently controlled by the column decoder 3 . In addition, the gates of the selection transistors ST2 in each even-numbered memory group MGe (MG0, MG2, . ), the gate of the selection transistor ST2 is, for example, commonly connected to the selection gate line SGSo. The selection gate lines SGSe and SGSo may be connected in common, for example, and may be independently controlled. In addition, the control gates of the memory cell transistors MT ( MT0 - MT7 ) included in the memory group MGe in the same block BLK are respectively commonly connected to the word lines WLe ( WLe0 - WLe7 ). On the other hand, the control gates of the memory cell transistors MT ( MT0 - MT7 ) included in the memory group MGo are respectively commonly connected to the word lines WLo ( WLo0 - WLo7 ). The selection gate lines WLe and WLo are independently controlled by the column decoder 3 . The block BLK is, for example, a deletion unit of data. That is, the data held by the memory cell transistors MT included in the same block BLK is deleted at one time. Furthermore, the drains of the selection transistors ST1 of the NAND strings 50 in the same row in the memory cell array 2 are commonly connected to the bit lines BL(BL0 to BL(L-1), wherein (L-1) is equal to or greater than 2 Natural number). That is, the bit line BL commonly connects the NAND strings 50 among the plurality of memory groups MG. Furthermore, the sources of the plurality of selection transistors ST2 are commonly connected to the source line SL. That is, the memory group MG includes a plurality of NAND strings 50 connected to different bit lines BL and connected to the same select gate line SGD. Also, the block BLK includes a plurality of memory groups MG that share a plurality of word lines WL. Furthermore, the memory cell array 2 includes a plurality of blocks BLK sharing the bit line BL. Furthermore, in the memory cell array 2, the memory cell transistors MT are three-dimensionally laminated by laminating the above-mentioned select gate lines SGS, word lines WL, and select gate lines SGD above the semiconductor substrate. <Regarding the Plane Layout of the Memory Cell Array> Next, the plan configuration of the memory cell array 2 will be described. FIG. 3 shows the planar layout of the select gate lines SGD in the semiconductor substrate plane of a certain block BLK (referred to as the XY plane). In this example, the case where 8 selection gate lines SGD are included in one block BLK will be described. As shown in the figure, nine conductive layers 10 (10-0 to 10-7, wherein 10-0 includes 10-0a and 10-0b) extending along the X-direction are arranged along the Y-direction orthogonal to the X-direction. Each conductive layer 10 functions as a selection gate line SGD. In the example of FIG. 3 , the two wiring layers 10 - 0 a and 10 - 0 b located at both ends along the Y direction in the block BLK function as the selection gate line SGD0 . That is, the two wiring layers 10 located at both ends in the Y direction are commonly connected to each other, or are controlled in the same manner by the column decoder 3 . Furthermore, the seven wiring layers 10-1 to 10-7 located in between function as selection gate lines SGD1 to SGD7, respectively. Therefore, when viewed in the XY plane in the block BLK, the memory groups MG1 to MG7 are arranged along the Y direction, and the memory group MG0 is arranged on both sides thereof. The adjacent wiring layers 10 in the Y direction in the block BLK are separated by an insulating film not shown. The region where the insulating film is provided is referred to as a slit SLT2. In the slit SLT2, the insulating film is buried, for example, from the surface of the semiconductor substrate to at least the region where the wiring layer 10 is provided. Moreover, in the memory cell array 2, for example, a plurality of blocks BLK shown in FIG. 3 are arranged in the Y direction. In addition, blocks BLK adjacent to each other in the Y direction are also separated by an insulating film not shown. The region where the insulating film is provided is the slit SLT1 described in FIG. 1 . Slit SLT1 is also the same as SLT2. Furthermore, a plurality of memory pillars MP ( MP0 to MP15 ) respectively along the Z direction are provided between the adjacent wiring layers 10 in the Y direction. The Z direction is the direction perpendicular to the XY direction, that is, the direction perpendicular to the surface of the semiconductor substrate. Specifically, memory pillars MP0 and MP8 are arranged between the wiring layers 10-1 and 10-2, memory pillars MP1 and MP9 are arranged between the wiring layers 10-3 and 10-4, and memory pillars MP1 and MP9 are arranged between the wiring layers 10-5. Memory pillars MP2 and MP10 are arranged between the wiring layers 10-7 and 10-0b, and memory pillars MP3 and MP11 are arranged between the wiring layers 10-7 and 10-0b. The memory pillar MP forms the structure of the selection transistors ST1 and ST2 and the memory cell transistor MT, the details of which will be described below. The memory columns MP0 to MP3 are arranged along the Y direction. In addition, the memory pillars MP8 to MP11 are arranged in the Y direction so as to be adjacent to the memory pillars MP0 to MP3 in the X direction. That is, the memory pillars MP0 to MP3 and the memory pillars MP8 to MP11 are arranged side by side. Furthermore, the bit line BL0 is disposed above the wiring layer 10 so as to be commonly connected to the memory pillars MP0 to MP3. In addition, the bit line BL2 is provided above the wiring layer 10 so as to be connected to the memory pillars MP8 to MP11 in common. Hereinafter, the memory pillars MP0 to MP3, the memory pillars MP8 to MP11, and the bit lines BL0 and BL2 may be referred to as a group GR1. In addition, memory pillars MP4 and MP12 are provided between the wiring layers 10-0a and 10-1, memory pillars MP5 and MP13 are provided between the wiring layers 10-2 and 10-3, and memory pillars MP5 and MP13 are provided between the wiring layers 10-4 and 10. Memory pillars MP6 and MP14 are arranged between -5, and memory pillars MP7 and MP15 are arranged between the wiring layers 10-6 and 10-7. The memory columns MP4 to MP7 are arranged along the Y direction, and the memory columns MP12 to MP15 are also arranged along the Y direction. Moreover, the memory columns MP4 to MP7 are located between the memory columns MP0 to MP3 and the memory columns MP8 to MP11 in the X direction. In addition, the memory pillars MP12 to MP15 are provided so as to sandwich the memory pillars MP8 to MP11 together with the memory pillars MP4 to MP7 in the X direction. That is, the memory pillars MP4 to MP7 and the memory pillars MP12 to MP15 are arranged side by side. Furthermore, the bit line BL1 is disposed above the wiring layer 10 so as to be commonly connected to the memory pillars MP4 to MP7. In addition, the bit line BL3 is provided above the wiring layer 10 so as to be connected to the memory pillars MP12 to MP15 in common. Hereinafter, the memory pillars MP4 to MP7, the memory pillars MP12 to MP15, and the bit lines BL1 and BL3 may be referred to as a group GR2. That is, the memory pillars MP are provided so as to straddle the two wiring layers 10 in the Y direction and are embedded in a part of any one of the slits SLT2, and there is one slit between the adjacent memory pillars MP in the Y direction. SLT2. Further, the slit SLT2 for embedding the memory pillar MP belonging to the group GR1 is located between the two memory pillars MP belonging to the group GR2, and the slit SLT2 for embedding the memory pillar MP belonging to the group GR2 is located between the two memory pillars belonging to the group GR1. Between columns MP. Furthermore, the memory pillar MP is not provided between the adjacent wiring layers 10-0a and 10-0b via the slit SLT1. FIG. 4 shows the planar layout of the word lines WL in the XY plane, similarly to FIG. 3 . FIG. 4 corresponds to the area of the size of 1 block in FIG. 3 , and is a layout of the wiring layer 11 disposed at a lower level than the wiring layer 10 illustrated in FIG. 3 . As shown in the figure, nine conductive layers 11 (11-0 to 11-7, wherein 11-0 includes 11-0a and 11-0b) extending along the X direction are arranged along the Y direction. The respective wiring layers 11-0 to 11-7 are provided directly below the wiring layers 10-0 to 10-7 via an insulating film. Each conductive layer 10 functions as a word line WL7. The same applies to other word lines WL0 to WL6. In the example of FIG. 4, the wiring layers 11-0a, 11-3, 11-5, 11-7, and 11-0b function as word lines WLo7. And these wiring layers 11-0a, 11-3, 11-5, 11-7, and 11-0b are drawn out to an end portion along the X direction (the end portion is referred to as a first connection portion), and connected in common with each other. Furthermore, the wiring layers 11-0a, 11-3, 11-5, 11-7, and 11-0b are connected to the column decoder 3 in the first connection portion. In addition, the wiring layers 11-1, 11-3, 11-5, and 11-7 function as word lines WLe7. And these wiring layers 11-1, 11-3, 11-5, and 11-7 are drawn out to the 2nd connection part located on the opposite side to the 1st connection part in the X direction, and are mutually connected in common. Furthermore, the wiring layers 11 - 1 , 11 - 3 , 11 - 5 , and 11 - 7 are connected to the column decoder 3 in the second connection portion. And a memory cell part is provided between the 1st connection part and the 2nd connection part. In the memory cell portion, the adjacent wiring layers 11 in the Y direction are separated by the slit SLT2 illustrated in FIG. 3 . In addition, the wiring layers 11 between the adjacent blocks BLK in the Y direction are similarly separated by the slit SLT1. In addition, in the memory cell portion, memory pillars MP0 to MP15 are provided in the same manner as in FIG. 3 . The above configuration is also the same in other layers forming the word line WL and the select gate line SGS. <About the cross-sectional structure of the memory cell array> Next, the cross-sectional structure of the memory cell array 2 will be described. FIG. 5 is a cross-sectional view of the block BLK along the Y direction, and shows the cross-sectional structure of the region along the bit line BL0 in FIG. 3 as an example. As shown in the figure, a wiring layer 12 that functions as a selection gate line SGS is provided above a semiconductor substrate (eg, a p-type well region) 13 . Above the wiring layer 12, eight wiring layers 11 that function as word lines WL0 to WL7 are stacked along the Z direction. The plane layout of the wirings 11 and 12 is shown in FIG. 4 . Furthermore, the wiring layer 10 functioning as the selection gate line SGD is provided above the wiring layer 11 . The planar layout of the wiring layer 10 is illustrated in FIG. 3 . Further, the slits SLT2 and the memory pillars MP are alternately provided along the Y direction so as to reach the semiconductor substrate 13 from the wiring layer 10 . As described above, the substance of the slit SLT2 is an insulating film. However, a contact plug or the like for applying a voltage to a region provided in the semiconductor substrate 13 may also be provided in the slit SLT2. For example, a contact plug for connecting the source of the selection transistor ST2 to the source line may also be provided. Furthermore, the wiring layer 12 alternately functions as the selection gate line SGSo or SGSe with the slit SLT2 or the memory pillar MP therebetween. Similarly, the wiring layer 11 alternately functions as the word line WLo or WLe with the slit SLT2 or the memory pillar MP therebetween. In addition, a slit SLT1 is provided between the blocks BLK adjacent in the Y direction. As described above, the body of the slit SLT1 is also an insulating film. However, a contact plug or the like for applying a voltage to a region provided in the semiconductor substrate 13 may also be provided in the slit SLT1. For example, a contact plug or groove-shaped conductor for connecting the source of the selection transistor ST2 to the source line may also be provided. Furthermore, the width of the slit SLT1 along the Y direction is greater than the width of the slit SLT2 along the Y direction. Further, contact plugs 16 are provided on the memory pillars MP, and the wiring layer 15 functioning as the bit line BL is provided along the Y direction so as to be commonly connected to the contact plugs 16 . FIG. 6 is a cross-sectional view of the block BLK along the X direction, showing the cross-sectional structure of the region along the selection gate line SGD3 in FIG. 3 and passing through the memory pillars MP5 and MP13 as an example. As described in FIG. 5 , wiring layers 12 , 11 , and 10 are sequentially provided above the semiconductor substrate 13 . The memory cell portion is as described with reference to FIG. 5 . In the first connection portion, the wiring layers 10 to 12 are drawn out in a stepped shape, for example. That is, when viewed in the XY plane, the upper surfaces of the end portions of the seven-layer wiring layer 10 and the wiring layer 12 are exposed at the first connection portion. Furthermore, contact plugs 17 are provided on the exposed regions, and the contact plugs 17 are connected to the metal wiring layer 18 . And, the wiring layers 10 to 12 that function as the even-numbered selection gate lines SGD0, SGD2, SGD4, and SGD6, the even-numbered element lines WLo, and the even-numbered selection gate lines SGSo are electrically connected to the metal wiring layer 18. Column decoder 3. On the other hand, in the second connection portion, the wiring layers 11 and 12 are drawn out, for example, in a stepped shape in the same manner. Furthermore, contact plugs 19 are provided on the exposed regions of the wiring layers 11 and 12 , and the contact plugs 19 are connected to the metal wiring layer 20 . Furthermore, the wiring layers 11 and 12 that function as odd-numbered selection gate lines SGD1 , SGD3 , SGD5 , and SGD7 , odd-numbered element lines WLe, and odd-numbered selection gate lines SGSe are electrically connected to the metal wiring layer 20 . Column decoder 3. Furthermore, the wiring layer 10 may be electrically connected to the column decoder 3 via the second connection portion instead of the first connection portion, or may be connected via both the first connection portion and the second connection portion. <About the structures of memory pillars and memory cell transistors> Next, the structures of the memory pillars MP and the memory cell transistors MT will be described.・About the first example First, the first example will be described with reference to FIGS. 7 and 8 . FIG. 7 is a cross-sectional view in the XY plane of the memory pillar MP, and FIG. 8 is a cross-sectional view in the YZ plane, especially showing a region where two memory cell transistors MT are disposed. In the first example, an insulating film is used for the charge accumulation layer of the memory cell transistor MT. As shown in the figure, the memory pillar MP includes an insulating layer 30 , a semiconductor layer 31 , and insulating layers 32 to 34 arranged along the Z direction. The insulating layer 30 is, for example, a silicon oxide film. The semiconductor layer 31 is provided so as to surround the periphery of the insulating layer 30, and functions as a region for forming a channel of the memory cell transistor MT. The semiconductor layer 31 is, for example, a polysilicon layer. The insulating layer 32 is provided so as to surround the periphery of the semiconductor layer 31, and functions as a gate insulating film of the memory cell transistor MT. The insulating layer 32 has, for example, a laminated structure of a silicon oxide film and a silicon nitride film. The insulating layer 33 is provided so as to surround the periphery of the semiconductor layer 31, and functions as a charge accumulation layer of the memory cell transistor MT. The insulating layer 33 is, for example, a silicon nitride film. The insulating layer 34 is provided so as to surround the periphery of the insulating layer 33, and functions as a blocking insulating film of the memory cell transistor MT. The insulating layer 34 is, for example, a silicon oxide film. An insulating layer 37 is embedded in the slit SLT2 except for the memory pillar MP portion. The insulating layer 37 is, for example, a silicon oxide film. Further, an AlO layer 35, for example, is provided around the memory pillar MP configured as described above. A shield metal layer (TiN film or the like) 36 is formed around the AlO layer 35, for example. The conductive layer 11 functioning as the word line WL is provided around the shield metal layer 36 . The conductive layer 11 is made of, for example, tungsten. According to the above configuration, in one memory pillar MP, two memory cell transistors MT are provided along the Y direction. The selection transistors ST1 and ST2 also have the same configuration. - About the second example Next, the second example will be described with reference to Figs. 9 and 10 . FIG. 9 is a cross-sectional view of the memory pillar MP in the XY plane, and FIG. 10 is a cross-sectional view in the YZ plane, especially showing a region where two memory cell transistors MT are disposed. In the second example, a conductive film is used in the charge accumulation layer of the memory cell transistor MT. As shown in the figure, the memory pillar MP includes insulating layers 48 and 43 , a semiconductor layer 40 , an insulating layer 41 , a conductive layer 42 , and insulating layers 46 a to 46 c disposed along the Z direction. The insulating layer 48 is, for example, a silicon oxide film. The semiconductor layer 40 is provided so as to surround the periphery of the insulating layer 43-1. The semiconductor layer 40 is, for example, a polysilicon layer, and functions as a region for forming a channel of the memory cell transistor MT, and is not separated between the memory cell transistors MT located in the same memory pillar MP as in the example of FIG. 7 . The insulating layer 41 is provided around the conductive layer 40 and functions as a gate insulating film of each memory cell transistor MT. That is, the insulating layer 41 is divided into two regions in the XY plane shown in FIG. 9, and each functions as the gate insulating film of the two memory cell transistors MT in the same memory pillar MP. The insulating layer 41 has, for example, a laminated structure of a silicon oxide film and a silicon nitride film. The conductive layer 42 is disposed around the insulating layer 41 and is separated into two regions along the Y direction by the insulating layer 43 . The conductive layer 42 is, for example, a polysilicon layer, and the two separated regions function as charge accumulation layers of the two memory cell transistors MT, respectively. In addition, the insulating layer 43 is, for example, a silicon oxide film. Insulating layers 46 a , 46 b , and 46 c are sequentially disposed around the conductive layer 42 . The insulating layers 46a and 46c are, for example, a silicon oxide film, and the insulating layer 46b is, for example, a silicon nitride film, and these function as a blocking insulating film of the memory cell transistor MT. The insulating layers 46a to 46b are also separated into two regions along the Y direction, and the insulating layer 43 is provided between them. Moreover, the insulating layer 43 is buried in the slit SLT2. The insulating layer 43 is, for example, a silicon oxide film. Furthermore, an AlO layer 45, for example, is provided around the memory pillar MP configured as described above. Further, around the AlO layer 45, for example, a shield metal layer (TiN film or the like) 47 is formed. Furthermore, the conductive layer 11 that functions as the word line WL is provided around the shield metal layer 47 . According to the above configuration, in one memory pillar MP, two memory cell transistors MT are provided along the Y direction. The selection transistors ST1 and ST2 also have the same configuration. Furthermore, an insulating layer (not shown) is provided between the adjacent memory cell transistors in the Z direction, and through the insulating layer and the insulating layers 43 and 46, the charge accumulating layer 42 and each memory cell transistor are connected to each other. Every insulation.・About the equivalent circuit FIG. 11 is an equivalent circuit diagram of the memory pillar MP constructed as described above. As shown in the figure, two NAND strings 50o and 50e are formed in one memory pillar MP. That is, the selection transistor ST1 disposed on the same memory column MP is connected to the mutually different selection gate lines SGD, the memory cell transistor MT is connected to the mutually different word lines WLo and WLe, and the selection transistor ST2 is also connected to The selection gate lines SGSo and SGSe are different from each other. Furthermore, the two NAND strings 50o and 50e in the same memory column MP are connected to the same bit line BL, and are also connected to the same source line SL. However, the current paths are electrically separated from each other. 1.2 About the readout operation Next, a method for readout of the data in the NAND-type flash memory having the above configuration will be described. First, a state in which the selection gate line SGD is selected will be described with reference to FIGS. 12 and 13 . FIGS. 12 and 13 are plan layout views of the selection gate line SGD in the XY plane corresponding to FIG. 3 described above, and the wiring layer 10 corresponding to the selected selection gate line SGD is marked with oblique lines to indicate . As shown in FIG. 12 , when any one of the selection gate lines SGD1 to SGD7 is selected, any one of the corresponding wiring layers 10 - 1 to 10 - 7 is selected. FIG. 12 shows the case where the selection gate line SGD1 is selected. By selecting the wiring layer 10-1, the four memory cell transistors MT provided in the memory pillars MP0, MP4, MP8, and MP12 are selected. That is, one page is formed by four memory cell transistors MT belonging to the wiring layer 11-1 disposed directly under the wiring layer 10-1 and corresponding to any word line WL. The same applies to the case where the selection gate lines SGD2 to SGD7 are selected. On the other hand, both the wiring layers 10-0a and 10-0b located at both ends in the block BLK are simultaneously selected. This case corresponds to the case where the selection gate line SGD0 is selected. This state is shown in FIG. 13 . As shown in the figure, when the selection gate line SGD0 is selected, the two memory cell transistors MT located directly under the wiring layer 10-0a and disposed in the memory pillars MP4 and MP12 and the two memory cell transistors MT located directly under the wiring layer 10-0b and located in the memory pillars MP12 are selected. Two memory cell transistors MT are arranged on the memory pillars MP3 and MP11. That is, one page is formed by these four memory cell transistors MT. 14 is a timing chart showing voltage changes of various wirings when the odd-numbered selection gate line SGDo (ie, the odd-numbered memory group MG) and the word line WLo0 are selected. As shown in the figure, first, at time t1, the voltage VSG is applied to all the selection gate lines SGD in the selection block BLK, and the selection transistor ST1 is turned on. Furthermore, the voltage VREAD is applied to all the word lines, and the memory cell transistor MT is turned on regardless of the data being held. Furthermore, the voltage VSG is applied to all the selection gate lines SGS, and the selection transistor ST2 is turned on. Thereby, in the selected block BLK, all the NAND strings 50 are turned on, and VSS (eg, 0 V) is transmitted to the channel. Then, at time t3, the sense amplifier 4 precharges the bit line BL. At this time, the even bit lines BL0 and BL2 belonging to the group GR1 are precharged to the voltage VBL2, and the odd bit lines BL1 and BL3 belonging to the group GR2 are precharged to the voltage VBL1 higher than the voltage VBL2. Then, at time t4, the voltage VSG is applied to the selected selected gate lines SGD and SGSo, the read voltage VCGRV is applied to the selected word line WLo0, the voltage VNEG is applied to the unselected word line WLe0, and other unselected words are applied Element lines WL1 to WL7. The voltage VCGRV is a voltage corresponding to the readout level, and is a voltage used to determine whether the holding data of the selected memory cell transistor MT is "0" or "1". The voltage VNEG is, for example, a negative voltage or 0 V, and is a voltage for turning off the memory cell transistor MT. The result of the above is that if the selected memory cell transistor MT is turned on, current will flow from the bit line BL to the source line SL, and if the selected memory cell transistor MT is turned off, no current will flow . Thereby, the retention data of the selected memory cell transistor MT can be determined. 1.3 Effects of the present embodiment According to the present embodiment, it is possible to correct variations in memory cell characteristics among the memory groups MG, thereby improving the operational reliability of the semiconductor memory device. This effect will be described below. In the semiconductor memory device of the present embodiment, as described in FIGS. 3 and 4 , one memory column MP consists of two select gate lines SGD and two word lines WL arranged across the XY plane way to set. Furthermore, two memory cell transistors MT are arranged in the memory pillar MP, and are controlled by the above-mentioned two selection gate lines SGD and word lines WL. Furthermore, in this configuration, there is a case where the positional relationship between the memory pillar MP and the corresponding two word lines WL (and the selection gate line SGD) deviates. More specifically, in FIGS. 3 and 4 , when focusing on a certain memory column MP, it is preferable that the central part of the memory column MP in the Y direction is located in the middle of the corresponding two word lines. The reason for this is that by arranging the memory pillars MP in this way, the sizes of the two memory cell transistors MT controlled by the corresponding two word lines WL become equal. However, if the positions of the memory pillars MP are shifted, the sizes of the corresponding two memory cell transistors MT are different. For example, in the example of FIGS. 3 and 4 , the memory pillar MP is shifted toward the wiring layer 10 - 0 a along the Y direction. As a result, when looking at the wiring layers 10-1 and 11-1 and the memory pillars MP0 and MP4, the memory pillar MP0 and the wiring layers 10-1 and 11-1 overlap by the distance d1, and the memory pillar MP4 and the wiring layer 10-1 overlap. and 11-1 overlap the distance d2, and there is a relationship of d1>d2. In this case, the same relationship exists between the memory columns MP8 and MP12. That is, when looking at the case of the memory group MG1, the cell size of the memory cell transistor MT connected to the even-numbered bit line BLe is larger, and the cell size of the memory cell transistor MT connected to the odd-numbered bit line BLo is smaller . The size of the cell size can also be said to be the size of the current driving capability of the memory cell transistor MT. That is, according to FIG. 3 , when the even-numbered selection gate line SGDe is selected, the size of the memory cell transistors MT connected to the bit lines BL0 and BL2, that is, the memory cell transistors MT belonging to the group GR1 smaller. On the other hand, the size of the memory cell transistors MT connected to the bit lines BL1 and BL3, that is, the memory cell transistors belonging to the group GR2 is larger. On the contrary, when the odd-numbered select gate line SGDo is selected, the size of the memory cell transistors MT connected to the bit lines BL0 and BL2, that is, the memory cell transistors MT belonging to the group GR1 is larger. On the other hand, the size of the memory cell transistors MT connected to the bit lines BL1 and BL3, that is, the memory cell transistors belonging to the group GR2 is smaller. As described above, when the positions of the memory pillars MP are shifted, in the same page, the memory cell transistors MT of different sizes are alternately arranged. Therefore, in the present embodiment, the sense amplifier 4 controls the precharge potential during the read operation according to the size of the selected memory cell transistor MT. More specifically, when the even-numbered selection gate line SGDe, that is, the even-numbered memory group MGe, is selected, the sense amplifier 4 applies a larger precharge potential VBL1 to the bit line BL of the group GR1, and applies a larger precharge potential VBL1 to the group GR2. A smaller precharge potential VBL2 is applied to the bit line BL. On the other hand, when the odd-numbered selection gate line SGDo, that is, the odd-numbered memory group MGo, is selected, the sense amplifier 4 applies a relatively small precharge potential VBL2 to the bit line BL of the group GR1, and applies a smaller precharge potential VBL2 to the bit line BL of the group GR2. A larger precharge potential VBL1 is applied to the bit line BL. As a result, the difference in current driving force due to the cell size of the memory cell transistor MT can be offset by the precharge potential, so that the cell current flowing to the bit line BL during the read operation can be reduced between the bit lines. difference. That is, the cell transistor MT which does not easily flow the cell current is given the condition for flowing a sufficiently large cell current, and the cell transistor MT which is easy to flow the cell current is given the condition for suppressing the cell current. Thereby, the occurrence of erroneous reading especially from the memory cell transistor MT which is difficult to flow the cell current can be suppressed, so that the operational reliability of the semiconductor memory device can be improved. Furthermore, according to the configuration of this embodiment, as shown in FIG. 3, the wiring layers 10-0a and 10-0b located at both ends of the block BLK are simultaneously selected, and both function as the selection gate line SGD0. This is because four memory pillars MP (memory cell transistors MT) are formed on the other wiring layers 10-1 to 10-7, respectively, whereas only two are formed on the wiring layers 10-0a and 10-0b. Memory pillar MP (memory cell transistor MT). Therefore, with regard to both ends of the block BLK, the two wiring layers 10-0a and 10-0b electrically function as one selection gate line SGD, so that even when the selection gate line SGD0 is selected , the size of one page can be made the same as when other selection gate lines SGD1 to SGD7 are selected. Furthermore, as a result of making the page sizes consistent as described above, as shown in FIG. 3 , the number of wiring layers 10 functioning as selection gate lines SGD in one block BLK becomes an odd number in the XY plane. This also applies to the wiring layer 11 that functions as the word line WL as shown in FIG. 4 . In other words, when viewed in the XY plane, the number of wiring layers located between the slits SLT1 is an odd number. Furthermore, the offset manner of the memory pillar MP can be reversed to that of FIG. 3 and FIG. 4 . The state in this case is shown in FIG. 15 . FIG. 15 shows a plan layout of the selection gate line SGD in a modification of the present embodiment. As shown in the figure, in this example, the position of the memory pillar MP is opposite to that of FIG. 3 , and is shifted toward the wiring layer 10 - 0 b along the Y direction. As a result, when looking at the wiring layers 10-1 and 11-1 and the memory pillars MP0 and MP4, the memory pillar MP0 and the wiring layers 10-1 and 11-1 overlap by the distance d2, and the memory pillar MP4 and the wiring layer 10-1 overlap. And 11-1 overlap distance d1. In this case, the voltage applied to the bit line BL during readout is opposite to that of the above-described embodiment. That is, when the even-numbered selection gate line SGDe, that is, the even-numbered memory group MGe, is selected, the sense amplifier 4 applies the smaller precharge potential VBL2 to the bit line BL of the group GR1, and applies the smaller precharge potential VBL2 to the bit line BL of the group GR2. Line BL applies a larger precharge potential VBL1. On the other hand, when the odd-numbered selection gate line SGDo, that is, the odd-numbered memory group MGo, is selected, the sense amplifier 4 applies a larger precharge potential VBL1 to the bit line BL of the group GR1, and applies a larger precharge potential VBL1 to the bit line BL of the group GR2. A relatively small precharge potential VBL2 is applied to the bit line BL. 2. Second Embodiment Next, the semiconductor memory device of the second embodiment will be described. The present embodiment relates to the writing operation in the above-mentioned first embodiment. Hereinafter, only the points different from the first embodiment will be described. 2.1 First Example First, the first example will be described. The data writing operation includes a programming operation, which injects electrons into the charge accumulation layer to change the threshold value, and a program verification operation, which confirms whether the threshold value, which is the result of the programming operation, has reached a predetermined value. In the first example, during the programming operation, the voltage applied to the bit line BL is different between the groups GR1 and GR2. 16 is a timing chart showing voltage changes of various wirings when the odd-numbered selection gate line SGDo (ie, the odd-numbered memory group MG) and the word line WLo0 are selected during data writing. As shown in FIG. 12 and FIG. 13 , when the odd-numbered selection gate line SGDo is selected, the memory cell transistors MT belonging to the group GR1 (BL0, BL2) are larger in size and belong to the group GR2 (BL1, BL3) The memory cell transistor MT is smaller. Since the larger the overlapping area of the word line WL and the memory column MP is, the larger the coupling ratio is, so the writing speed of the memory cell transistor MT is faster. That is, the writing speed of the group GR1 is fast, and the group GR2 is slow. Therefore, at time t2, the sense amplifier 4 applies a relatively high voltage VCH2 to the bit lines BL0 and BL2 belonging to the group GR1, and applies a low voltage VCH1 to the bit lines BL1 and BL3 belonging to the group GR2. Of course, VCH2>VCH1. Next, at time t3, the column decoder 3 applies the voltage VPASS to all the word lines WL0-WL7, and further increases the voltage of the selected word line WLo0 from VPASS to VPGM at time t5. The voltage VPASS is the voltage that enables the memory cell transistor MT to turn on regardless of the data being held and that in the non-selected NAND string 50 can sufficiently raise the channel potential by coupling. In addition, the voltage VPGM is a high voltage for injecting electrons into the charge accumulation layer by FN (Fowler-Nordheim) tunneling, and VPGM>VPASS. According to the present method, by increasing the bit line voltage corresponding to the memory cell transistor MT having a higher writing speed, the writing speed thereof can be reduced. Thereby, the difference in writing speed between the groups GR1 and GR2 can be reduced. 2.2 Second Example Next, the second example will be described. The second example is to change the value of the voltage VPGM applied to the selected word line WL in the groups GR1 and GR2 during the programming operation. 17 is a timing chart showing potential changes of the selected word line WL and the bit line BL in this example, and shows the case where the even-numbered memory group MG, that is, the even-numbered selection gate line SGDe is selected. As described above, the write action includes a program action and a program verify action. This combination is called a programming loop. In addition, in the writing operation, data for one page is written by repeating the programming cycle a plurality of times. In this example, during the programming operation, two kinds of programming voltages VPGM1 and VPGM2 are applied to the selected word line WL, and there is a relationship of VPGM2>VPGM1. When the even-numbered memory group MG is selected, the writing speed of the memory cell transistors MT belonging to the group GR1 (BL0, BL2) is slower, and the memory cell transistors MT belonging to the group GR2 (BL1, BL3) are slower. Write faster. Therefore, the voltage VPGM1 is used as the programming voltage for the group GR2, and the voltage VPGM2 is used as the programming voltage for the group GR1. Specifically, during the period in which the voltage VPGM1 is applied, the write inhibit voltage VBL is applied to the bit lines BL0 and BL2 of the group GR1, and the write voltage (eg, 0 V, less than 0 V) is applied to the bit lines BL1 and BL3 of the group GR2. voltage of VBL). As a result, data is programmed to the memory cell transistors MT connected to the bit lines BL1 and BL3. On the other hand, during the period in which the voltage VPGM2 is applied, the write inhibit voltage VBL is applied to the bit lines BL1 and BL3 of the group GR2, and the write voltage is applied to the bit lines BL0 and BL2 of the group GR1. As a result, data is programmed to the memory cell transistors MT connected to the bit lines BL0 and BL2. According to this method, a higher programming voltage is used for the memory cell transistor MT with a slower writing speed, and a lower programming voltage is used for the memory cell transistor MT with a faster writing speed. Thereby, the difference in writing speed between the groups GR1 and GR2 can be reduced. Furthermore, the boosting amplitude ΔVPGM of the programming voltage VPGM can also be changed in the groups GR1 and GR2. Of course, in the group where the writing speed is slow, ΔVPGM is set to be larger. 2.3 Third Example Next, the third example will be described. In the third example, during the program verification operation, the precharge potential of the group with a slower writing speed is lowered, thereby reducing the cell current relatively. That is, the method of applying the voltage to the bit line BL is the same as that of FIG. 14 described in the first embodiment. According to this method, in a memory cell transistor with a relatively slow writing speed, as the programming cycle is repeated many times, the threshold value of the cell becomes higher, so that it becomes difficult for the cell current to flow, so that it is easy to pass the program verification. As a result, the difference in writing speed between the groups GR1 and GR2 can be reduced. 2.4 Effects of the present embodiment According to the present embodiment, even when the writing speed is different among the memory cell transistors belonging to the same page, the number of programming cycles required to pass the program verification can be made the same. Therefore, the number of programming loops can be reduced, so that the buy-in speed can be improved. In addition, the memory cell transistor with the faster writing speed can be prevented from being disturbed by the writing operation to the memory cell transistor with the slower writing speed for a long time after passing the program verification quickly, thereby improving the writing speed. Operation reliability. 3. Third Embodiment Next, a semiconductor memory device according to a third embodiment will be described. The present embodiment is different from the above-mentioned first and second embodiments in terms of the plane layout. As an example, two bit lines are provided on one memory column. Hereinafter, only the points different from the first and second embodiments will be described. 3.1 About the plane layout Figures 18 and 19 show the plane layout of the selection gate line SGD in the XY plane of a block BLK. FIG. 18 corresponds to FIG. 3 described in the first embodiment, and also shows the state of the bit line BL. In FIG. 19 , the illustration of the memory cell portion is simplified, and the structure of the first connection portion and the second connection portion is particularly focused. In addition, in this example, the case where four selection gate lines SGD are included in one block BLK will be described. As shown in the figure, also in this example, like the configuration described in FIG. 3 , nine conductive layers 10 extending in the X direction are included. However, in this example, the wiring layers 10-1 to 10-7 and 10-0b illustrated in FIG. 3 are respectively renamed as wiring layers 10-1a, 10-2a, 10-3a, 10-0b, and 10- 1b, 10-2b, 10-3b, and 10-0c. The point in which the slit SLT2 is provided between each wiring layer 10 is also the same as that of the first embodiment. Furthermore, the two wiring layers 10-0a and 10-0c located at both ends along the Y direction in the block BLK and the wiring layer 10-0b located at the center function as the selection gate line SGD0. As shown in FIG. 19 , the three wiring layers 10 - 0 are commonly connected to each other by, for example, the contact plug 49 and the metal wiring layer 51 in the first connection portion, and are further connected to the column decoder 3 . In addition, the wiring layers 10 - 1 a and 10 - 2 b are connected in common through the contact plug 52 and the metal wiring layer 53 in the second connection portion, and are further connected to the column decoder 3 . Furthermore, the wiring layers 10 - 2 a and 10 - 2 b are connected in common through the contact plug 52 and the metal wiring layer 53 in the second connection portion, and are further connected to the column decoder 3 . Furthermore, the wiring layers 10 - 3 a and 10 - 3 b are commonly connected by the contact plug 49 and the metal wiring layer 51 in the first connection portion, and are further connected to the column decoder 3 . Also, as shown in FIG. 18, two bit lines BL pass over one memory pillar MP. Among the two bit lines BL, the bit line connected to the memory column MP is only any one of them. That is, two bit lines BL0 and BL1 are disposed above the memory pillars MP0 to MP3. The bit line BL0 is commonly connected to the memory columns MP1 and MP2, and the bit line BL1 is commonly connected to the memory columns MP0 and MP3. In addition, two bit lines BL2 and BL3 are provided above the memory pillars MP4 to MP7. The bit line BL2 is commonly connected to the memory columns MP4 and MP5, and the bit line BL3 is commonly connected to the memory columns MP6 and MP7. Furthermore, two bit lines BL4 and BL5 are arranged above the memory pillars MP8-MP11. The bit line BL4 is commonly connected to the memory columns MP9 and MP10, and the bit line BL5 is commonly connected to the memory columns MP8 and MP11. Furthermore, two bit lines BL6 and BL7 are disposed above the memory pillars MP12 to MP15. The bit line BL6 is commonly connected to the memory columns MP12 and MP13, and the bit line BL7 is commonly connected to the memory columns MP14 and MP15. Therefore, in the case of this example, the bit lines BL0, BL1, BL4 and BL5 and the memory columns MP0-MP3 and MP8-MP11 belong to the group GR1, the bit lines BL2, BL3, BL6 and BL7 and the memory columns MP4-MP7 and MP12 to MP15 belong to group GR2. Other structures are as described in the first embodiment. 3.2 Page Selection Method Next, the page selection method when data is read and written will be described. As described in 3.1 above, in this example, two or three wiring layers 10 are connected in common. Therefore, a plurality of wiring layers 10 connected in common are selected at the same time. 20 and 21 are plan layout views of the selection gate line SGD in the XY plane corresponding to FIG. 18 described above, and the wiring layer 10 corresponding to the selected selection gate line SGD is marked with oblique lines. As shown in FIG. 20 , when any one of the selection gate lines SGD1 to SGD3 is selected, the corresponding two wiring layers 10 are selected. In FIG. 20, the case where the selection gate line SGD1 is selected is shown. In this case, by selecting the two wiring layers 10-1a and 10-1b, 8 memory cells disposed in the memory columns MP0, MP4, MP8, and MP12 and the memory columns MP2, MP6, MP10, and MP14 are selected. Transistor MT. That is, one page is formed by eight memory cell transistors MT belonging to the wiring layers 11-1a and 11-1b disposed directly under the wiring layers 10-1a and 10-1b corresponding to any word line WL. The same is true in the case where the gate lines SGD2 and SGD3 are selected. On the other hand, when the gate line SGD0 is selected, as shown in FIG. 21, the wiring layers 10-0a and 10-0c at both ends of the block BLK and the wiring at the center of the block BLK are simultaneously selected Three wiring layers 10 of layer 10-0b. Thereby, two memory cell transistors MT located directly under the wiring layer 10-0a and disposed on the memory pillars MP4 and MP12, and two memory cells located directly under the wiring layer 10-0c and located in the memory pillars MP3 and MP11 are selected The transistor MT, and the four memory cell transistors MT located directly under the wiring layer 10-0b and disposed on the memory pillars MP1, MP6, MP9, and MP14. That is, one page is formed by these eight memory cell transistors MT. The method of reading data and the method of writing data are as described in the first and second embodiments. 3.3 Effects of the present embodiment According to the present embodiment, the size of one page can be increased by allowing two or more wiring layers 10 to function as one selection gate line SGD. In addition, if the wiring method for selecting the gate line SGD in this example is used, when a plurality of wiring layers 10 are selected, the inter-unit interference effect ( Including the effect of capacitance or resistance) is almost equal between wiring layers. For example, in FIG. 19, when the case where the gate line SGD2 is selected is selected, the wiring layers 10-2a and 10-2b are driven. The wiring layer 10 adjacent to the wiring layer 10-2a in the Y direction is 10-1a and 10-3a which function as the wiring layer SGD1 and function as the wiring layer SGD3. Also, the wiring layers 10 adjacent to the other wiring layer 10-2b selected at the same time in the Y direction are also wiring layers 10-1b and 10-3b that function as the selection gate lines SGD1 and SGD3. In this way, one selection gate line SGD is separated into two wirings in the memory cell portion, and the combination of adjacent selection gate lines in the Y direction is common between the two separated wirings. That is, the two wirings obtained by separation have almost the same influence from the adjacent wirings. The situation is the same when any one of the selection gate lines SGD is selected. Therefore, variation in characteristics among the selected gate lines SGD can be suppressed, thereby improving operational reliability. FIG. 22 is a top view in the XY plane of the selection gate line SGD of a modification of the present embodiment. As shown in the figure, this example shows a case where the number of wirings 10 in one block BLK is set to 17. As shown in the figure, for example, wiring layers 10-0a, 10-1a, 10-2a, 10-3a, 10-4a, 10-5a, 10-6a, 10-7a, and 10-0b are arranged in this order along the Y direction. , 10-1b, 10-2b, 10-3b, 10-4b, 10-5b, 10-6b, 10-7b, and 10-0c. Furthermore, the wiring layers 10-0a and 10-0c at both ends and the wiring layer 10-b at the center function as the selection gate line SGD0. In addition, the wiring layers 10-1a and 10-1b function as the selection gate line SGD1, and the wiring layers 10-2a and 10-2b function as the selection gate line SGD2, and the same applies hereinafter. In this way, the number of wiring layers 10 can be appropriately increased. When expressed in a generalized manner, it can be explained as shown in FIG. 23 . FIG. 23 is also a plane layout of the selection gate line SGD. As shown in the figure, (2n+1) wiring layers 10-1 to 10-(2n+1) are arranged along the Y direction. Among them, n is a natural number of 2 or more. Moreover, the wiring layer 10-1 of the first layer, the wiring layer 10-(n+1) located in the center, and the wiring layer 10-(2n+1) located at the end are connected in common. Regarding the remaining wiring layers 10, the i-th layer and the (i+n)-th layer are connected in common. Among them, i is a natural number from 2 to n. 4. Fourth Embodiment Next, a semiconductor memory device according to a fourth embodiment will be described. The present embodiment is an example in which the wiring method of the wiring layer 10 functioning as the selection gate line SGD is different from that of the third embodiment described above. Hereinafter, only the points different from the first to third embodiments will be described. 4.1 About the Plane Layout Fig. 24 shows the plan layout of the selection gate lines SGD in the XY plane of a block BLK, which corresponds to Fig. 19 described in the third embodiment. Although the illustration of the bit line BL is omitted, it is the same as the third embodiment. As shown in the figure, in the layout of this example, two wiring layers 10 - 0 a and 10 - 0 c along the Y direction and one wiring layer 10 along the Y direction and the two wiring layers 10 - One wiring layer 10-0b adjacent to 0a or 10-0c is drawn out to the first connection portion and connected in common. Furthermore, these three wiring layers 10-0a, 10-0b, and 10-0c function as the selection gate line SGD0. Regarding the remaining wiring layers 10 , two adjacent wiring layers 10 in the Y direction are connected to each other in common at the connection portion with one wiring layer 10 interposed therebetween. That is, as shown in FIG. 24 , the wiring layers 10-1a and 10-1b are drawn out to the second connection portion, are connected in common, and function as the selection gate line SGD1. In addition, the wiring layers 10-2a and 10-2b are drawn out to the first connection portion, are connected in common, and function as the selection gate line SGD2. Furthermore, the wiring layers 10 - 3 a and 10 - 3 b are drawn out to the second connection portion, are connected in common, and function as the selection gate line SGD3 . At the time of reading and writing, two or three wiring layers 10 that are commonly connected to the first connection portion or the second connection portion are driven simultaneously. 4.2 Effects of the present embodiment As described above, the wiring method of the selective gate line SGD described in the third embodiment can be applied to the method of the present embodiment. Furthermore, according to the present embodiment, since there is no case where the plurality of wiring layers 10 intersect with each other, the plurality of wiring layers 10 can be connected in common among the layers of the wiring layers 10 . That is, it is not necessary to use other layers by contact plugs and metal wiring layers as in FIG. 19 . Thereby, the manufacturing method can be simplified. FIG. 25 is a plan layout of the selection gate line SGD according to a modification of the present embodiment, and shows an example of the case where the number of wiring layers 10 in one block BLK is set to 17 similarly to FIG. 22 . As shown in the figure, the two wiring layers 10 at both ends along the Y direction and the wiring layer 10 which is the third layer from the end in the Y direction are drawn out to the first connection portion and used as selection gate lines SGD0 functions. The other wiring layers are the same as in FIG. 24 , and two wiring layers 10 adjacent to each other in the Y direction with a certain wiring layer 10 interposed therebetween are connected in common at the first connection portion or the second connection portion. FIG. 26 shows a state in which (2n+1) wiring layers 10-1 to 10-(2n+1) are arranged along the Y direction. Among them, n is a natural number of 2 or more. Furthermore, the first wiring layer 10-1, the third wiring layer 10-3, and the last wiring layer 10-(2n+1) are connected in common. Regarding the remaining wiring layers 10, the k-th layer and the (k+2)-th layer are connected in common. Among them, k is 2, 5, 6, 7, 10, ... 10-(2n-3) and 10-(2n-2). 5. Modifications, etc. As described above, the semiconductor memory device of the above-described embodiment includes a first region (BLK in FIG. 3 ) including a first region disposed above the semiconductor substrate and along the in-plane direction of the semiconductor substrate A plurality of first wirings (SGD in FIG. 3 ) are arranged side by side in the direction (X direction in FIG. 3 ), and a first insulation separating adjacent first wirings (SGD in FIG. 3 ) Membrane (SLT2 in FIG. 3), and a first column (MP in FIG. 3) arranged so as to straddle the adjacent first wirings (SGD in FIG. 3); and second, The third region (SLT1 in FIG. 3 ) is equal to sandwich the first region (BLK) in the in-plane direction of the semiconductor substrate and in a second direction (Y direction in FIG. 3 ) different from the first direction It is provided in between, and includes the second insulating film provided from the semiconductor substrate to the height of the first wiring (SGD in FIG. 3 ). The first pillar (MP) includes a conductive layer, a gate insulating film, and a charge accumulation layer (FIGS. 7-10). The number of the first wirings (SGD) arranged in the first area (BLK in FIG. 3 ) is an odd number ( FIG. 3 ). According to this configuration, the operational reliability of the semiconductor memory device can be improved. In addition, the embodiment demonstrated above is only an example, and various changes are possible. For example, in the above-mentioned embodiment, the case where there are one or two bit lines BL passing through the memory pillar MP has been described as an example, but it may be three or four, or four or more. In addition, the number of gate lines SGD selected is not limited to 9 or 17. Furthermore, the configuration in which two NAND strings are provided in the memory column MP is not limited to the configuration described in the above-mentioned first embodiment. Such a structure is described, for example, in US Patent Application No. 14/819,706 filed on August 6, 2015, entitled "SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME". The entirety of the patent application is incorporated into the specification of this application by reference. In addition, in the above-mentioned embodiment, the plane layout of the word line WL has been described with reference to FIG. 4 . However, the number of word lines WL included in one block BLK can be appropriately selected, and the connection method of the word lines WL can also be appropriately selected. Moreover, as shown in FIG. 27, for example, the structure shown in FIG. 4 may be arranged in two stages in the Y direction. In this configuration, the slit SLT1 is provided not only at both ends along the Y direction of one block BLK, but also at the center of the block BLK. Furthermore, in the example of FIG. 27 , four word lines WL are connected in common at the first connection portion on one side across the slit SLT1, and the remaining three word lines WL are connected at the second connection portion. Commonly connected. On the other hand, on the other side across the slit SLT1, four word lines WL are commonly connected at the second connection portion, and the remaining three word lines WL are commonly connected at the first connection portion. Furthermore, the two groups of word lines WL with the slit SLT1 interposed therebetween are connected by the wiring layers 60 and 61 . With this configuration, the number of word lines WL driven from the first connection portion side (nine in FIG. 27 ) can be equal to the number of word lines WL driven from the second connection portion side. Furthermore, the selection transistor ST2 may include, for example, a two-transistor structure. FIG. 28 is an equivalent circuit diagram corresponding to one memory column MP. As shown in the figure, the selection transistor ST2 may also include two transistors ST2-1 and ST2-2 connected in common. FIG. 29 is a cross-sectional view of the selection transistor ST2. As shown, the selection transistor ST2 - 1 is formed on the memory pillar MP, but the selection transistor 2 - 2 is formed on the p-type well region 13 . That is, the gate insulating film 70 is formed on the well region 13 , and the gate electrode 12 is provided on the gate insulating film 70 . Furthermore, an n-type impurity diffusion layer 71 functioning as a source region is provided in the well region 13 . According to this configuration, a potential can be applied to the back gate of the transistor ST2-2 by, for example, the diffusion layer 71 or the like. Furthermore, in various embodiments related to the present invention, (1) For example, the memory cell transistor MT can hold 2-bit data, and its threshold voltages are "Er", "A", "Er", "A", " B" and "C" levels, when the "Er" level is in the deletion state, the voltage applied to the word line selected in the readout operation of the "A" level is, for example, 0 V to 0.55 V between. It is not limited to this, and can be set to any range of 0.1 V to 0.24 V, 0.21 V to 0.31 V, 0.31 V to 0.4 V, 0.4 V to 0.5 V, and 0.5 V to 0.55 V. The voltage applied to the word line selected in the read operation of the "B" level is, for example, between 1.5 V and 2.3 V. It is not limited to this, and can be set to any range of 1.65 V to 1.8 V, 1.8 V to 1.95 V, 1.95 V to 2.1 V, and 2.1 V to 2.3 V. The voltage applied to the word line selected in the read operation of the "C" level is, for example, between 3.0 V and 4.0 V. It is not limited to this, and can be set to any range of 3.0 V to 3.2 V, 3.2 V to 3.4 V, 3.4 V to 3.5 V, 3.5 V to 3.6 V, and 3.6 V to 4.0 V. The time (tR) of the readout operation may be, for example, between 25 μs to 38 μs, 38 μs to 70 μs, and 70 μs to 80 μs. (2) The writing action includes a programming action and a verifying action. During the writing operation, the voltage initially applied to the word line selected during the programming operation is, for example, between 13.7 V and 14.3 V. It is not limited to this, For example, it may be set to any range of 13.7 V to 14.0 V and 14.0 V to 14.6 V. It is also possible to change the voltage initially applied to the selected word line when writing the odd word line and the voltage initially applied to the selected word line when writing the even word line. When the programming operation is set to the ISPP (Incremental Step Pulse Program, incremental step pulse programming) method, the boosted voltage can be, for example, about 0.5 V. The voltage applied to the non-selected word lines may be set to, for example, between 6.0 V and 7.3 V. Not limited to this case, for example, it may be set between 7.3 V and 8.4 V, or 6.0 V or less. The pass voltage to be applied can also be changed according to whether the non-selected word line is the odd-numbered word line or the even-numbered word line. The time (tProg) of the writing operation may be set to, for example, between 1700 μs to 1800 μs, 1800 μs to 1900 μs, and 1900 μs to 2000 μs. (3) In the erasing operation, the voltage initially applied to the well formed on the upper portion of the semiconductor substrate and on which the memory cell is arranged is, for example, between 12 V and 13.6 V. Not limited to this case, for example, it may be between 13.6 V to 14.8 V, 14.8 V to 19.0 V, 19.0 to 19.8 V, and 19.8 V to 21 V. The erasing time (tErase) may be, for example, between 3000 μs to 4000 μs, 4000 μs to 5000 μs, and 4000 μs to 9000 μs. (4) The structure of the memory cell has a charge accumulation layer disposed on a semiconductor substrate (silicon substrate) through a tunnel insulating film with a thickness of 4-10 nm. The charge accumulating layer can be a laminated structure of an insulating film such as SiN or SiON with a thickness of 2 to 3 nm and polysilicon with a thickness of 3 to 8 nm. In addition, a metal such as Ru may be added to the polysilicon. An insulating film is provided on the charge accumulation layer. The insulating film has, for example, a silicon oxide film with a thickness of 4 to 10 nm sandwiched by a lower High-k film with a thickness of 3 to 10 nm and an upper High-k film with a thickness of 3 to 10 nm. HfO etc. are mentioned as a High-k film. In addition, the film thickness of the silicon oxide film may be thicker than that of the High-k film. A control electrode with a film thickness of 30 nm to 70 nm is formed on the insulating film through a material for adjusting a work function with a film thickness of 3 to 10 nm. Here, the material for work function adjustment is a metal oxide film such as TaO or a metal nitride film such as TaN. As the control electrode, W or the like can be used. Also, an air gap can be formed between the memory cells. Furthermore, in the above-mentioned embodiments, the NAND type flash memory is used as an example of the semiconductor memory device, but it is not limited to the NAND type flash memory, and can be applied to all other semiconductor memories. It is applied to various memory devices other than semiconductor memory. Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or variations thereof are included in the scope or gist of the invention, and are also included in the inventions described in the scope of the claims and their equivalents. [Related Applications] This application enjoys the priority of Japanese Patent Application No. 2017-61208 (filing date: March 27, 2017) and Japanese Patent Application No. 2017-168249 (application date: September 1, 2017) as basic applications right. The present application includes the entire contents of the basic application by referring to the basic application.

1: NAND type flash memory 2: Memory cell array 3: Column Decoder 4: Sense Amplifier 10: Wiring layer 10-0a: Wiring layer 10-0b: Wiring layer 10-1: Wiring layer 10-2: Wiring layer 10-3: Wiring layer 10-4: Wiring layer 10-5: Wiring layer 10-6: Wiring layer 10-7: Wiring layer 10-8: Wiring layer 10-1a: Wiring layer 10-2a: Wiring layer 10-3a: Wiring layer 10-4a: Wiring layer 10-5a: Wiring layer 10-6a: Wiring layer 10-7a: Wiring layer 10-1b: Wiring layer 10-2b: Wiring layer 10-3b: Wiring layer 10-4b: Wiring layer 10-5b: Wiring layer 10-6b: Wiring layer 10-7b: Wiring layer 10-0c: Wiring layer 10-n: wiring layer 10-(n+1): wiring layer 10-(n+2): wiring layer 10-(n+3): wiring layer 10-2n: wiring layer 10-(2n+1): wiring layer 10-(2n-1): wiring layer 10-(2n-2): wiring layer 10-(2n-3): wiring layer 11: Conductive layer 11-0a: Wiring layer 11-0b: Wiring layer 11-1: Wiring layer 11-2: Wiring layer 11-3: Wiring layer 11-4: Wiring layer 11-5: Wiring layer 11-6: Wiring layer 11-7: Wiring layer 12: Wiring layer 13: Semiconductor substrate 15: Wiring layer 16: Contact plug 17: Contact plug 18: Wiring layer 19: Wiring layer 19: Contact plug 20: Metal wiring layer 30: Insulation layer 31: Semiconductor layer 32: Insulation layer 33: Insulation layer 34: Insulation layer 35: Insulation layer 36: Conductive layer 37: Insulation layer 40: Conductive layer 41: Insulation layer 42: Conductive layer 43: Insulation layer 45: Insulation layer 46a: Insulation layer 46b: Insulation layer 46c: Insulation layer 47: Conductive layer 48: Insulation layer 49: Contact plug 50: NAND string 50e: NAND string 50o: NAND string 51: Metal wiring layer 52: Contact plug 53: Metal wiring layer 60: wiring layer 61: wiring layer 70: Gate insulating film 71: n-type impurity diffusion layer BL: bit line BL0: bit line BL1: bit line BL2: bit line BL3: bit line BL4: bit line BL5: bit line BL6: bit line BL7: bit line BL(L-1): bit line BLK: block d1: overlap distance d2: overlap distance GR1: Group GR2: Group MG0: memory group MG1: Memory Group MG2: Memory Group MG3: Memory Group MG4: Memory Group MG5: Memory Group MG6: Memory Group MG7: Memory Group MP: Memory Column MP0: Memory column MP1: Memory column MP2: Memory Column MP3: Memory Column MP4: Memory Column MP5: Memory Column MP6: Memory Column MP7: Memory Column MP8: Memory column MP9: Memory Column MP10: Memory column MP11: Memory Column MP12: Memory column MP13: Memory Column MP14: Memory Column MP15: Memory Column MT: Memory Cell Transistor MT0: memory cell transistor MT1: Memory Cell Transistor MT2: Memory Cell Transistor MT3: Memory Cell Transistor MT4: Memory Cell Transistor MT5: Memory Cell Transistor MT6: Memory Cell Transistor MT7: Memory Cell Transistor SGSo: select gate line SGSe: select gate line SGD: select gate line SGD0: select gate line SGD1: select gate line SGD2: select gate line SGD3: select gate line SGD4: select gate line SGD5: select gate line SGD6: select gate line SGD7: select gate line SGDn: select gate line SGD(n－1): select gate line SGS: select gate line SL: source line SLT1: Slit SLT2: Slit ST1: select transistor ST2: select transistor ST2-1: Transistor ST2-2: Transistor t0: time t1: time t2: time t3: time t4: time t5: time t6: time t7: time t8: time VBL: inhibit voltage VCGRV: Voltage VCH1: Voltage VCH2: Voltage VNEG: Voltage VPASS: Voltage VPGM: Voltage VPGM1: Voltage VPGM2: Voltage VREAD: Voltage VSG: Voltage VSS: Voltage WL: word line WL1: word line WL2: word line WL3: word line WL4: word line WL5: word line WL6: word line WL7: word line WLe0: word line WLe1: word line WLe2: word line WLe3: word line WLe4: word line WLe5: word line WLe6: word line WLe7: word line WLo0: word line WLo1: word line WLo2: word line WLo3: word line WLo4: word line WLo5: word line WLo6: word line WLo7: word line △VPGM: Boost amplitude

FIG. 1 is a block diagram of a semiconductor memory device according to the first embodiment. FIG. 2 is a circuit diagram of the memory cell array of the first embodiment. FIG. 3 is a plan layout of the selection gate line of the first embodiment. Fig. 4 is a plan layout of the word line of the first embodiment. Fig. 5 is a cross-sectional view of a block of the first embodiment. Fig. 6 is a cross-sectional view of a block of the first embodiment. Fig. 7 is a cross-sectional view of the memory cell transistor of the first embodiment. Fig. 8 is a cross-sectional view of the memory cell transistor of the first embodiment. Fig. 9 is a cross-sectional view of the memory cell transistor of the first embodiment. Fig. 10 is a cross-sectional view of the memory cell transistor of the first embodiment. FIG. 11 is an equivalent circuit diagram of the memory column of the first embodiment. FIG. 12 is a plan layout of the selection gate line of the first embodiment. FIG. 13 is a plan layout of the selection gate line of the first embodiment. FIG. 14 is a timing chart of various signals during the readout operation of the first embodiment. FIG. 15 is a plan layout of a selection gate line in a first modification of the first embodiment. FIG. 16 is a timing chart of various signals during the writing operation of the second embodiment. FIG. 17 is a timing chart of various signals during the writing operation of the second embodiment. FIG. 18 is a plan layout of the selection gate line of the third embodiment. FIG. 19 is a plan layout of the selection gate line of the third embodiment. FIG. 20 is a plan layout of the selection gate line of the third embodiment. FIG. 21 shows the plan layout of the selection gate line of the third embodiment. FIG. 22 is a plan layout of a selection gate line in a first modification of the third embodiment. FIG. 23 is a plan layout of a selection gate line in a second modification of the third embodiment. FIG. 24 is a plan layout of the selection gate line of the fourth embodiment. FIG. 25 is a plan layout of a selection gate line in a first modification of the fourth embodiment. FIG. 26 is a plan layout of a selection gate line in a second modification of the fourth embodiment. FIG. 27 is a plan layout of a word line according to a first modification of the first to fourth embodiments. FIG. 28 is an equivalent circuit diagram of a memory column according to a second modification of the first to fourth embodiments. FIG. 29 is a cross-sectional view of a part of a region of a memory column according to a third modification of the first to fourth embodiments.

10-0a: Wiring layer

10-0b: Wiring layer

10-1: Wiring layer

10-2: Wiring layer

10-3: Wiring layer

10-4: Wiring layer

10-5: Wiring layer

10-6: Wiring layer

10-7: Wiring layer

BL0: bit line

BL1: bit line

BL2: bit line

BL3: bit line

BLK: block

d1: overlap distance

d2: overlap distance

GR1: Group

GR2: Group

MG0: memory group

MG1: Memory Group

MG2: Memory Group

MG3: Memory Group

MG4: Memory Group

MG5: Memory Group

MG6: Memory Group

MG7: Memory Group

MP0: Memory column

MP1: Memory column

MP2: Memory Column

MP3: Memory Column

MP4: Memory Column

MP5: Memory Column

MP6: Memory Column

MP7: Memory Column

MP8: Memory column

MP9: Memory Column

MP10: Memory column

MP11: Memory Column

MP12: Memory column

MP13: Memory Column

MP14: Memory Column

MP15: Memory Column

SGD0: select gate line

SGD1: select gate line

SGD2: select gate line

SGD3: select gate line

SGD4: select gate line

SGD5: select gate line

SGD6: select gate line

SGD7: select gate line

SLT1: Slit

SLT2: Slit

Claims (36)

A semiconductor memory device, comprising: a plurality of wirings, which are equal to the same level on a semiconductor substrate, and each extend in parallel along a first direction and are spaced apart from each other in a second direction , the plurality of wirings include: a first wiring, a second wiring, which is adjacent to the first wiring, and a third wiring, which is adjacent to the second wiring, and the second wiring is located in the second direction. Between the first wiring and the third wiring; a plurality of pillars, each of which extends in a third direction toward the semiconductor substrate, the third direction intersects the first direction and the second direction, and the plurality of pillars include : a first post located between the first wiring and the second wiring, a second post located between the second wiring and the third wiring, a third post located between the first wiring and the third wiring between 2 wires and aligned with the first post along the first direction, and a fourth post located between the second wire and the third wire and along the first direction with the second post Alignment; a plurality of bit lines, each extending in parallel along the second direction and spaced apart from each other in the first direction, the plurality of bit lines comprising: a first bit line connected to the first 1 bar, the 2nd bit line, which connects to the 2nd bar above, the 3rd bit line, which connects to the 3rd bar above, and A fourth bit line connected to the fourth column; and a fourth wiring located at a different level from the first, second and third wirings, the fourth wiring extending in the first direction and being different from the above The 1st, 2nd, 3rd and 4th columns are adjacent; wherein during the programming operation in which each of the above-mentioned 1st to 4th bit lines is selected: the first selection voltage is applied to the above-mentioned fourth line; the first A programming voltage is applied to the second wiring, a first selected bit line voltage is applied to the first and third bit lines, and a second selected bit line voltage is applied to the second and the fourth bit line, the voltage of the second selected bit line is different from the voltage of the first selected bit line. The semiconductor memory device of claim 1, wherein the voltage of the first selected bit line is greater than the voltage of the second selected bit line. The semiconductor memory device of claim 1, further comprising: a plurality of selection gate lines equal to the plurality of wirings in the first direction, the plurality of selection gate lines including at least two commonly controlled indivual. The semiconductor memory device of claim 1, further comprising: a first gap located between the first pillar and the second word line, a second gap located between the second pillar and the second word Between the element lines, a third gap is located between the third column and the second word line, and a fourth gap is located between the fourth column and the second word line. The semiconductor memory device of claim 4, wherein the planar area of the first gap viewed from the third direction is larger than the planar area of the second gap viewed from the third direction, and the planar area of the first gap viewed from the third direction The plane area of the third gap observed is larger than the plane area of the fourth gap observed from the third direction. The semiconductor memory device of claim 5, wherein the planar area of the first gap is substantially the same as the planar area of the third gap, and the planar area of the second gap is substantially the same as the planar area of the fourth gap . The semiconductor memory device of claim 4, wherein the planar area of the first gap viewed from the third direction is substantially equal to the planar area of the third gap viewed from the third direction, and the planar area viewed from the third direction The plane area of the second gap is substantially equal to the plane area of the fourth gap viewed from the third direction. The semiconductor memory device of claim 1, wherein during the programming operation, a first pass voltage is applied to the first wiring and the third wiring. A method for performing a writing operation on a semiconductor memory device, the semiconductor memory device having: a plurality of wirings, which are equal to and at the same level on a semiconductor substrate, and each extend in parallel along a first direction and in a second direction spaced from each other, the above-mentioned plural wirings include: 1 wiring, a second wiring adjacent to the first wiring, and a third wiring adjacent to the second wiring, wherein the second wiring is located between the first wiring and the third wiring in the second direction a plurality of pillars, each of which extends toward the semiconductor substrate in a third direction, the third direction intersects with the first direction and the second direction, and the pillars include: located in the first wiring and the second A first pillar between the wirings, a second pillar located between the second wiring and the third wiring, located between the first wiring and the second wiring and aligned with the first pillar along the first direction the third pillar, and a fourth pillar located between the second wiring and the third wiring and aligned with the second pillar along the first direction; and a plurality of bit lines, each of which is along the first 2 directions extend in parallel and are spaced apart from each other in the first direction, the plurality of bit lines include: a first bit line connected to the first column, a second bit line connected to the second column, The 3rd bit line connected to the above-mentioned 3rd column, and the 4th bit line connected to the above-mentioned 4th column; and the 4th wiring, which is located at a different level from the above-mentioned 1st, 2nd and 3rd wirings, the above-mentioned The fourth wiring extends in the first direction and is adjacent to the first, second, third and fourth pillars; the method includes: applying a first selection voltage to the fourth wiring; at the first to fourth positions During the programming operation in which the bit line is selected, the first programming voltage is applied to the second wiring; the first selected bit line voltage is applied to the first and third bit lines, and the second selected bit line voltage is applied to the above For the second and fourth bit lines, the voltage of the second selected bit line is different from the voltage of the first selected bit line. The method of claim 9, wherein the voltage of the first selected bit line is greater than the voltage of the second selected bit line. The method of claim 9, wherein the semiconductor memory device further comprises: a first gap located between the first pillar and the second word line, a second gap located between the second pillar and the second word Between the lines, a third gap is located between the third column and the second word line, and a fourth gap is located between the fourth column and the second word line. The method of claim 11, wherein the planar area of the first slit viewed from the third direction is larger than the planar area of the second slit viewed from the third direction, and the third slit viewed from the third direction The plane area is larger than the plane area of the fourth gap viewed from the third direction. The method of claim 12, wherein the planar area of the first slit is substantially the same as the planar area of the third slit, and the planar area of the second slit is substantially the same as the planar area of the fourth slit. The method of claim 9, wherein during the programming operation, a first pass voltage is applied to the first and third wirings. A semiconductor memory device, comprising: a plurality of wirings on a semiconductor substrate and at the same level, each extending in parallel along a first direction and spaced apart from each other in a second direction, the plurality of wirings Wiring includes: 1st wiring, a second wiring that is adjacent to the first wiring, a third wiring that is adjacent to the second wiring, and a plurality of pillars each extending toward the semiconductor substrate in a third direction, the third direction and the The first direction and the second direction intersect, and the plurality of pillars include a first pillar located between the first wiring and the second wiring, and a second pillar located between the second wiring and the third wiring in between, a third pillar located between the first wiring and the second wiring and aligned with the first pillar along the first direction, and a fourth pillar located between the second wiring and the third between wirings and aligned with the second column along the first direction; a first gap, located between the first column and the second word line; a second gap, located between the second column and the first between 2 word lines; a 3rd slot, which is located between said 3rd column and said 2nd word line; a 4th gap, which is located between said 4th column and said 2nd word line; and a plurality of bit lines, each of which extends in parallel along the second direction and is spaced apart from each other in the first direction, the plurality of bit lines comprising: a first bit line connected to the first pillar, a second The 2-bit line is connected to the above-mentioned second column, the third-bit line is connected to the above-mentioned third column, and the fourth-bit line is connected to the above-mentioned fourth column; wherein during the programming operation: the first a programming voltage is applied to the second wiring, a first voltage is applied to the first and third bit lines, and A second voltage is applied to the second and fourth bit lines, and the second voltage is different from the first voltage; the planar area of the first gap viewed from the third direction is larger than the planar area of the first gap viewed from the third direction The plane area of the second gap, and the plane area of the third gap viewed from the third direction is larger than the plane area of the fourth gap viewed from the third direction. The semiconductor memory device of claim 15, wherein the planar area of the first gap viewed from the third direction is substantially equal to the planar area of the third gap viewed from the third direction, and the planar area viewed from the third direction The plane area of the second gap is substantially equal to the plane area of the fourth gap viewed from the third direction. The semiconductor memory device of claim 15, wherein the first voltage is greater than the second voltage. The semiconductor memory device of claim 15, further comprising: a fourth wiring located at a different level from the first, second, and third wirings, the fourth wiring extending in the first direction and being different from the first, second, and third wirings. The 2nd, 3rd and 4th pillars are adjacent. The semiconductor memory device of claim 18, wherein each of the first to fourth bit lines is selected during the programming operation. The semiconductor memory device of claim 19, wherein during the programming operation, the first selection voltage is applied to the fourth wiring. A semiconductor memory device, comprising: a semiconductor substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of odd-numbered element lines stacked on a plane intersecting the first and second directions In the third direction, each of the plurality of odd-numbered element lines includes: a plurality of first line portions extending in the first direction and spaced at a distance in the second direction intervals), and a first connecting portion, which extends in the above-mentioned second direction, and is electrically connected to the above-mentioned plurality of first line portions; a plurality of even digital element lines, which are stacked in the above-mentioned third direction, the above-mentioned plurality of even Each of the digital element lines includes: a plurality of second line portions, which extend in the first direction and are spaced apart in the second direction, the plurality of first line portions and the plurality of second line portions Alternately arranged in the above-mentioned second direction, and a second connection portion extending in the above-mentioned second direction and electrically connecting the above-mentioned plurality of second line portions; a plurality of pillars, each extending in the above-mentioned third direction, The plurality of pillars include: a first pillar that intersects with the gap between the odd digit line and the even digit line toward the semiconductor substrate; One side of one intersects, the second column, which in the second direction is intersected with the one of the above-mentioned plurality of second line portions The other side intersects, the 3rd column, which intersects the above-mentioned one side of the above-mentioned one of the above-mentioned plurality of second line portions in the above-mentioned second direction, and the 4th column, which intersects the above-mentioned plurality of the first line in the above-mentioned second direction. The above-mentioned other side of the above-mentioned one of the 2 line parts intersects, the 5th column, which intersects with one side of the other of the above-mentioned plural second line parts in the above-mentioned second direction, and the 6th column, which is in the above-mentioned No. 2 direction intersects with the other side of the above-mentioned other one of the above-mentioned plurality of second line parts, and a seventh pillar, which intersects the above-mentioned one side of the above-mentioned other one of the above-mentioned plurality of second line parts in the above-mentioned second direction intersecting, and an eighth pillar intersecting the other side of the other of the plurality of second line portions in the second direction, and the first to fourth pillars are sequentially arranged along the first direction , the above-mentioned 5th to 8th columns are sequentially arranged along the above-mentioned first direction; and a plurality of bit lines, which respectively extend in parallel along the above-mentioned second direction, and are spaced apart from each other in the above-mentioned first direction, the above-mentioned plural The one bit line includes: the first bit line, which is connected to the first bar, the second bit line, which is connected to the fifth bar, the third bit line, which is connected to the second bar, and the fourth bar. The bit line, which is connected to the above-mentioned 6th column, the 5th bit line, which is connected to the above-mentioned 3rd column, and the 6th bit line, which is connected to the above-mentioned 7th column, The seventh bit line is connected to the fourth column, and the eighth bit line is connected to the eighth column, and the first to eighth bit lines are sequentially arranged along the first direction. The semiconductor memory device of claim 21, wherein during a programming operation: a first programming voltage is applied to the second wiring, and a first voltage is applied to the first, second, fifth, and sixth bit lines, In addition, a second voltage is applied to the third, fourth, seventh and eighth bit lines, and the second voltage is different from the first voltage. The semiconductor memory device of claim 22, wherein the first voltage is greater than the second voltage. The semiconductor memory device of claim 21, further comprising: a plurality of select gate lines, each extending in parallel along the first direction, spaced apart from each other in the second direction, and extending in the third direction On the odd digit line and the even digit line, each of the plurality of selection gate lines is electrically connected to at least another one of the plurality of selection gate lines. The semiconductor memory device of claim 21, further comprising: a first gap located between said first pillar and said one of said plurality of second line portions; a second gap located between said second pillar and said between said one of said plurality of second line portions; a third gap located between said third column and said one of said plurality of second line portions; and A fourth gap is located between the fourth pillar and the one of the plurality of second line portions. The semiconductor memory device of claim 25, wherein the planar area of the first gap viewed from the third direction is larger than the planar area of the second gap viewed from the third direction, and the second gap viewed from the third direction The plane area of the third gap is larger than the plane area of the fourth gap viewed from the third direction. The semiconductor memory device of claim 26, wherein the planar area of the first gap is substantially the same as the planar area of the third gap, and the planar area of the second gap is substantially the same as the planar area of the fourth gap . The semiconductor memory device of claim 27, further comprising: a fifth gap located between the first pillar and the other of the plurality of second line portions; a sixth gap located between the second pillar and the between said other of said plurality of second line parts; a seventh gap located between said third column and said other of said plurality of second line parts; and an eighth gap located above said first Between the 4-pillar and the above-mentioned other one of the above-mentioned plurality of second line parts; wherein the plane area of the above-mentioned fifth gap viewed from the above-mentioned third direction is larger than the plane area of the above-mentioned sixth gap viewed from the above-mentioned third direction, The planar area of the seventh slot viewed from the third direction is larger than the planar area of the eighth slot viewed from the third direction, the planar area of the first slot, the planar area of the third slot, and the third slot. The above-mentioned plane area of the 5th slot and the above-mentioned plane area of the above-mentioned seventh slot are substantially the same, and the above-mentioned plane area of the above-mentioned second slot, the above-mentioned plane area of the above-mentioned fourth slot, the above-mentioned plane area of the sixth slot, and the above-mentioned eighth slot. The above-mentioned plane areas are substantially the same. The semiconductor memory device of claim 25, wherein the planar area of the first gap viewed from the third direction is substantially equal to the planar area of the third gap viewed from the third direction, and the planar area viewed from the third direction The plane area of the second gap is substantially equal to the plane area of the fourth gap viewed from the third direction. A method for performing a writing operation on a semiconductor memory device, the semiconductor memory device comprising: a semiconductor substrate extending in a first direction and a second direction crossing the first direction; a plurality of odd digital element lines, which are stacked on In a third direction intersecting with the first direction and the second direction, each of the plurality of odd-numbered element lines includes: a plurality of first line parts, which equally extend in the first direction and in the second direction spaced apart, and a first connection portion, which extends in the second direction and is electrically connected to the plurality of first line portions; a plurality of even digital element lines, which are stacked in the third direction, the plurality of even Each of the digital element lines includes: a plurality of second line portions, which are equally extended in the first direction and spaced apart in the second direction, the plurality of first line portions and the plurality of second line portions in Alternately arranged in the second direction, and a second connection portion, which extends in the second direction and is electrically connected to the plurality of second line portions; a plurality of pillars each extending in the third direction so as to face the semiconductor substrate to intersect with the gap between the odd digit line and the even digit line, the plurality of pillars including: in the second direction and the plurality of A first pillar intersecting one side of one of the second line portions, a second pillar intersecting the other side of the one of the plurality of second line portions in the second direction, in the second direction The third pillar intersecting the above-mentioned one side of the above-mentioned one of the above-mentioned plurality of second line parts, and the fourth column intersecting the above-mentioned other side of the above-mentioned one of the above-mentioned plurality of second line parts in the above-mentioned second direction A pillar, a fifth pillar that intersects with one side of the other of the plurality of second line portions in the second direction, and the other side of the other of the plurality of second line portions in the second direction A sixth pillar intersecting with one side, a seventh pillar intersecting with the one side of the other one of the plurality of second line portions in the second direction, and the plurality of second lines in the second direction In the eighth pillar intersecting the other side of the other one of the line parts, the first to fourth pillars are sequentially arranged along the first direction, and the fifth to eighth pillars are sequentially arranged along the first direction; and a plurality of bit lines each extending in parallel along the second direction and spaced apart from each other in the first direction, the plurality of bit lines comprising: a first bit line connected to the first pillar , the 2nd bit line connected to the 5th bar above, the 3rd bit line connected to the above 2nd bar, the 4th bit line connected to the above 6th bar, and the 5th bit line connected to the above 3rd bar Bit line, Bit line 6 connected to the 7th bar above, Bit line 7 connected to the 4th bar above, and Bit line 8 connected to the 8th bar above, Bit 1 to Bit 8 above The element lines are sequentially arranged along the first direction; the method includes: applying a first programming voltage to the second wiring, applying a first voltage to the first, second, fifth and sixth bit lines, and applying the first programming voltage to the second wiring. 2 voltages are applied to the third, fourth, seventh and eighth bit lines, and the second voltage is different from the first voltage. The method of claim 30, wherein the first voltage is greater than the second voltage. The method of claim 30, wherein the semiconductor memory device further comprises: a plurality of select gate lines each extending parallel along the first direction, spaced apart from each other in the second direction, and in the third direction Above the odd-digit element lines and the even-digit element lines in the direction, each of the plurality of selection gate lines is electrically connected to at least another one of the plurality of selection gate lines. The method of claim 30, wherein said semiconductor memory device further comprises: a first gap located between said first pillar and said one of said plurality of second line portions; a second gap located between said second pillar and between said one of said plurality of second line portions; a third gap located between said third column and said one of said plurality of second line portions; and a fourth gap located at said fourth between the column and the above-mentioned one of the above-mentioned plurality of second line portions. The method of claim 33, wherein the planar area of the first slit viewed from the third direction is larger than the planar area of the second slit viewed from the third direction, and the third slit viewed from the third direction The plane area is larger than the plane area of the fourth gap viewed from the third direction. The method of claim 34, wherein the planar area of the first slot is substantially the same as the planar area of the third slot, and the planar area of the second slot is substantially the same as the planar area of the fourth slot. The method of claim 35, wherein said semiconductor memory device further comprises: a fifth gap located between said first pillar and said other of said plurality of second line portions; a sixth gap located between said second between the column and the above-mentioned other of the plurality of second line portions; a seventh gap located between the third column and the above-mentioned other of the plurality of second line portions; and an eighth gap located at Between the fourth pillar and the other of the plurality of second line portions; wherein the plane area of the fifth gap viewed from the third direction is larger than the plane area of the sixth gap viewed from the third direction , the plane area of the seventh slot viewed from the third direction is larger than the plane area of the eighth slot viewed from the third direction, the plane area of the first slot, the plane area of the third slot, the The plane area of the fifth slot and the plane area of the seventh slot are substantially the same, and the plane area of the second slot, the plane area of the fourth slot, the sixth slot, and the eighth slot are substantially the same. The above-mentioned planar areas of the gaps are substantially the same.

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