TWI770649B - Source driver and polarity inversion control circuit - Google Patents

Abstract

A source driver and a polarity inversion control circuit are provided. The source driver includes a plurality of channel pairs and the polarity inversion control circuit. The polarity inversion control circuit includes a signal generating circuit and a routing circuit. The signal generating circuit generates a polarity control signal. The routing circuit outputs a plurality of switching control signals corresponding to the polarity control signal to a plurality of output switching circuits of the channel pairs. The routing circuit changes the correspondence between the polarity control signal and the switching control signals according to a polarity inversion configuration signal.

Description

Source driver and polarity inversion control circuit

The present invention relates to an electronic circuit, and more particularly, to a source driver and a polarity inversion control circuit.

In the display device, the source driver can drive the display panel according to the control of a timing controller to display images. In order to prevent the properties of liquid crystal molecules from being destroyed, the timing controller can control the source driver to perform polarity inversion. Generally speaking, the source driver includes a plurality of channel pairs for driving the display panel. Each of these channel pairs includes a positive polarity channel, a negative polarity channel and an output switching circuit. The positive channel is used to provide a positive driving voltage higher than the common voltage. The negative channel is used to provide a negative driving voltage lower than the common voltage.

FIG. 1 is a schematic diagram of a circuit block of a conventional source driver 20 . The source driver 20 shown in FIG. 1 can drive the display panel 10 to display images according to the control of a timing controller (not shown). The source driver 20 includes a plurality of channel pairs P_1, P_2, . . . , P_m, where m is an integer. The channel pair P_1 includes a positive polarity channel CH_1, a negative polarity channel CH_2, a signal generating circuit P1 and an output switching circuit OSW1. The first input terminal and the second input terminal of the output switching circuit OSW1 are respectively coupled to the output terminal of the positive polarity channel CH_1 and the output terminal of the negative polarity channel CH_2 . The channel pair P_2 includes a positive polarity channel CH_3, a negative polarity channel CH_4, a signal generating circuit P2 and an output switching circuit OSW2. The first input terminal and the second input terminal of the output switching circuit OSW2 are respectively coupled to the output terminal of the positive polarity channel CH_3 and the output terminal of the negative polarity channel CH_4 . By analogy, the channel pair P_m includes a positive polarity channel CH_n-1, a negative polarity channel CH_n, a signal generating circuit Pm and an output switching circuit OSWm. The first input terminal and the second input terminal of the output switching circuit OSWm are respectively coupled to the output terminal of the positive polarity channel CH_n-1 and the output terminal of the negative polarity channel CH_n.

The first output terminal and the second output terminal of the output switching circuits OSW1 ˜ OSWm are coupled to the data lines D1 , D2 , D3 , D4 , . . . , Dn-1 and Dn of the display panel 10 , as shown in FIG. 1 . Each of the positive polarity channels (eg CH_1, CH_3 and CH_n-1) has a latch LCH, a level shifter LS, a digital to analog converter DAC, and a positive polarity amplifier OP+. The positive-polarity amplifier OP+ is used to provide a positive-polarity driving voltage. Each of the negative polarity channels (eg CH_2, CH_4 and CH_n) has a latch LCH, a level converter LS, a digital to analog converter DAC, and a negative polarity amplifier OP-. The negative-polarity amplifier OP- is used to provide a negative-polarity driving voltage.

The timing controller (not shown) can output the polarity signal POL to the source driver 20 to control the polarity inversion operation of the source driver 20 . For example, when the polarity signal POL is the logic state "0", the polarity configuration of the data lines D1-Dn is "+ - + - + - + - ...", where "+" represents a positive driving voltage, and " -" indicates negative drive voltage. When the polarity signal POL is in the logic state "1", the polarity configuration of the data lines D1-Dn is "- + - + - + - + ...". However, according to the characteristics of the display panel 10 , design requirements and/or other considerations, the polarity configuration (polarity relationship) of the data lines D1 to Dn in other application scenarios may be different from the data line D1 in the aforementioned application scenarios Polarity configuration (polarity relationship) of ~Dn. For example, in another application scenario, when the polarity signal POL is the logic state "0", the polarity configuration of the data lines D1-Dn needs to be set to "+ - - + - + + - ..." (or, When the polarity signal POL is in the logic state "1", the polarity configuration of the data lines D1-Dn is "- + + - + - - + ...").

That is, in different application scenarios, the polarity configuration (polarity relationship) of the data lines D1 ˜Dn may be different. Therefore, the customized signal generating circuits P1 ˜Pm are configured in the channel pairs P_1 ˜P_m of the conventional source driver 20 . The signal generating circuits P1 ˜Pm can generate different switching control signals S1 , S2 , . . . , Sm to the output switching circuits OSW1 ˜ OSWm according to the polarity signal POL. Based on this, the output switching circuits OSW1 ˜ OSWm can output the driving voltages conforming to the customized polarity configuration (polarity relationship) to the data lines D1 ˜Dn of the display panel 10 .

Generally speaking, the polarity signal POL and the logic circuits of the signal generating circuits P1 ˜Pm operate in the low voltage range, while the switching control signals S1 ˜ Sm need to operate in the high voltage range. Therefore, a level converter needs to be configured in each of the signal generating circuits P1-Pm. When the number m of these channel pairs P_1 ˜P_m is larger, the number of the signal generating circuits P1 ˜Pm is larger. A large number of signal generating circuits P1 ˜Pm (level converters) occupy the limited chip area of the source driver 20 .

It should be noted that the content of the "prior art" paragraph is used to help understand the present invention. Some (or all) of the content (or all of the content) disclosed in the "prior art" paragraph may not be known by those of ordinary skill in the art. The content disclosed in the "Prior Art" paragraph does not mean that the content has been known to those with ordinary knowledge in the technical field before the application of the present invention.

The present invention provides a source driver and a polarity inversion control circuit to reduce the circuit area as much as possible.

In an embodiment of the present invention, the above-mentioned source driver includes a plurality of channel pairs and a polarity inversion control circuit. These channel pairs are suitable for driving display panels. Each of these channel pairs includes a positive polarity channel, a negative polarity channel and an output switching circuit. The first input end and the second input end of the output switching circuit are respectively coupled to the output end of the positive polarity channel and the output end of the negative polarity channel. The first output terminal and the second output terminal of the output switching circuit are coupled to the display panel. The polarity inversion control circuit includes a signal generating circuit and a routing circuit. The signal generating circuit is configured to generate the polarity control signal. The routing circuit is coupled to the signal generating circuit to receive the polarity control signal. The routing circuit is configured to output a plurality of switching control signals corresponding to the polarity control signals to the output switching circuits. The routing circuit changes the corresponding relationship between the polarity control signals and the switching control signals according to the polarity inversion configuration signal.

In an embodiment of the present invention, the above-mentioned polarity inversion control circuit includes a signal generating circuit and a routing circuit. The signal generating circuit is configured to generate the polarity control signal. The routing circuit is coupled to the signal generating circuit to receive the polarity control signal. The routing circuit is configured to output a plurality of switching control signals corresponding to the polarity control signals to a plurality of output switching circuits of the plurality of channel pairs of the source driver. The routing circuit changes the corresponding relationship between the polarity control signals and the switching control signals according to the polarity inversion configuration signal.

Based on the above, the multiple channel pairs described in the embodiments of the present invention can share the same signal generating circuit. Therefore, the circuit area of the source driver can be reduced as much as possible.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

The term "coupled (or connected)" as used throughout this specification (including the scope of the application) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through another device or some other device. indirectly connected to the second device by a connecting means. Terms such as "first" and "second" mentioned in the full text of the description (including the scope of the patent application) in this case are used to designate the names of elements or to distinguish different embodiments or scopes, rather than to limit the number of elements The upper or lower limit of , nor is it intended to limit the order of the elements. Also, where possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terminology in different embodiments may refer to relative descriptions of each other.

FIG. 2 is a schematic diagram of a circuit block of a source driver 200 according to an embodiment of the present invention. The source driver 200 shown in FIG. 2 can drive the display panel 10 to display images according to the control of a timing controller (not shown). The source driver 200 includes a plurality of channel pairs CHP_1, CHP_2, . . . , CHP_m, where m is an integer. The channel pair CHP_1 includes a positive polarity channel CH_1, a negative polarity channel CH_2 and an output switching circuit OSW_1. The first input terminal and the second input terminal of the output switching circuit OSW_1 are respectively coupled to the output terminal of the positive polarity channel CH_1 and the output terminal of the negative polarity channel CH_2 . The channel pair CHP_2 includes a positive polarity channel CH_3, a negative polarity channel CH_4 and an output switching circuit OSW_2. The first input terminal and the second input terminal of the output switching circuit OSW_2 are respectively coupled to the output terminal of the positive polarity channel CH_3 and the output terminal of the negative polarity channel CH_4 . By analogy, the channel pair CHP_m includes a positive polarity channel CH_n-1, a negative polarity channel CH_n and an output switching circuit OSW_m, where n is an integer. The first input terminal and the second input terminal of the output switching circuit OSW_m are respectively coupled to the output terminal of the positive polarity channel CH_n-1 and the output terminal of the negative polarity channel CH_n. The polar channels CH_1 ˜ CH_n shown in FIG. 2 can refer to the related descriptions of the polar channels CH_1 ˜ CH_n shown in FIG. 1 , and thus will not be repeated here.

The first output terminals and the second output terminals of the output switching circuits OSW_1 ˜ OSW_m are coupled to the data lines D1 , D2 , D3 , D4 , . . . , Dn−1 and Dn of the display panel 10 , as shown in FIG. 2 . The polarity inversion control circuit 210 can receive a line latch signal TP and a polarity signal POL provided by a timing controller (not shown). The line latch signal TP shown may be a start pulse for a line. According to the line latch signal TP and the polarity signal POL, the polarity inversion control circuit 210 can output a plurality of switching control signals SC1 , SC2 , . . . , SCm to the output switching circuits OSW_1 ˜OSW_m.

According to the characteristics of the display panel 10 , design requirements and/or other considerations, in different application scenarios, the polarity configurations (polarity relationships) of the data lines D1 ˜Dn may be different. For example, in a certain application scenario, when the polarity signal POL is the logic state "0", the polarity configuration of the data lines D1-Dn needs to be set to "+ - + - + - + - ...", where "+ " indicates a positive driving voltage, and "-" indicates a negative driving voltage. In another application scenario, when the polarity signal POL is also the logic state "0", the polarity configuration of the data lines D1-Dn needs to be set to "+ - - + - + + - ...".

The polarity inversion control circuit 210 can generate different switching control signals SC1 ˜SCm to the output switching circuits OSW_1 ˜OSW_m according to the line latch signal TP and the polarity signal POL. The polarity inversion control circuit 210 can change the logic configuration of the switching control signals SC1 ˜SCm according to the polarity inversion configuration signal DOTC, thereby controlling/changing the polarity configuration (polarity relationship) of the data lines D1 ˜Dn. For example, in the case where the polarity inversion configuration signal DOTC is the logic state "0" (in a certain application scenario), when the polarity signal POL is the logic state "0", the polarity inversion control circuit 210 can change these The logic configuration of the control signals SC1-SCm is switched to set the polarity configuration of the data lines D1-Dn as "+ - + - + - + - ...". In the case that the polarity inversion configuration signal DOTC is the logic state "1" (in another application scenario), when the polarity signal POL is also the logic state "0", the polarity inversion control circuit 210 can change the switching control The logic configuration of the signals SC1-SCm sets the polarity configuration of the data lines D1-Dn as "+ - - + - + + - ...".

The channel pairs CHP_1 ˜ CHP_m can share the same polarity inversion control circuit 210 , and the polarity inversion control circuit 210 can change the logic configuration of the switching control signals SC1 ˜ SCm according to different application scenarios. Based on the control of the switching control signals SC1 ˜SCm, the output switching circuits OSW_1 ˜OSW_m can output the driving voltages conforming to the customized polarity configuration (polarity relationship) to the data lines D1 ˜Dn of the display panel 10 .

In the embodiment shown in FIG. 2 , the polarity inversion control circuit 210 includes a signal generating circuit 211 and a routing circuit 212 . The signal generating circuit 211 can receive the line latch signal TP and the polarity signal POL provided by the timing controller (not shown). According to the line latch signal TP and the polarity signal POL, the signal generating circuit 211 can generate the polarity control signal SC to the routing circuit 212 . The signal generating circuit 211 can be implemented according to design requirements. For example, in some embodiments, when the line latch signal TP is at the logic state "1", the polarity control signal SC is at the logic state "1" regardless of the logic state of the polarity signal POL. When the line latch signal TP and the polarity signal POL are in the logic state "0", the polarity control signal SC is in the logic state "0". When the line latch signal TP is in the logic state "0" and the polarity signal POL is in the logic state "1", the polarity control signal SC is in the logic state "1".

The routing circuit 212 is controlled by the polarity inversion configuration signal DOTC. The routing circuit 212 is coupled to the signal generating circuit 211 to receive the polarity control signal SC. The routing circuit 212 can output a plurality of switching control signals SC1 ˜SCm corresponding to the polarity control signal SC to the output switching circuits OSW_1 ˜OSW_m of the channel pairs CHP_1 ˜CHP_m. The routing circuit 212 can change the corresponding relationship between the polarity control signal SC and the switching control signals SC1 ˜SCm according to the polarity inversion configuration signal DOTC.

For example, when the polarity reversal configuration signal DOTC is at the logic state "00" (in a certain application scenario), when the polarity control signal SC is at the logic state "0", the routing circuit 212 can change these switches The logic configuration of the control signals SC1-SCm is to set the polarity configuration of the data lines D1-Dn as "+ - + - + - + - ...". In the case where the polarity inversion configuration signal DOTC is the logic state "01" (in another application scenario), when the polarity control signal SC is also the logic state "0", the routing circuit 212 can change these switching control signals SC1 The logical configuration of ~SCm is to set the polarity configuration of data lines D1 to Dn as "+ - - + - + + - ...". In the case that the polarity inversion configuration signal DOTC is the logic state "10" (in another application scenario), when the polarity control signal SC is also the logic state "0", the routing circuit 212 can change these switching control signals SC1 The logical configuration of ~SCm is to set the polarity configuration of the data lines D1 to Dn as "+ - - + - + - + ...".

FIG. 3 is a circuit block diagram illustrating the signal generating circuit 211 shown in FIG. 2 according to an embodiment of the present invention. In the embodiment shown in FIG. 3 , the polarity control signal SC includes the original switching signals SWP, SWPB, SWN and SWNB. The original switching signal SWPB is the inverted signal of the original switching signal SWP, and the original switching signal SWNB is the inverted signal of the original switching signal SWN. In any case, the polarity control signal SC in other embodiments should not be limited to the polarity control signal SC shown in FIG. 3 .

The signal generating circuit 211 shown in FIG. 3 includes a logic circuit 310 , a level converter 320 and a level converter 330 . The logic circuit 310 can generate the logic signal SP and the logic signal SN according to the line latch signal TP and the polarity signal POL. The logic circuit 310 can be implemented according to design requirements. For example, in some embodiments, when the line latch signal TP is at the logic state "1", regardless of the logic state of the polarity signal POL, the logic signal SP is at the logic state "1" (eg, a high voltage level) and The logic signal SN is a logic state "0" (eg, a low voltage level). When the line latch signal TP and the polarity signal POL are both in the logic state "0", the logic signal SP and the logic signal SN are in the logic state "0". When the line latch signal TP is in the logic state "0" and the polarity signal POL is in the logic state "1", the logic signal SP and the logic signal SN are both in the logic state "1".

The level converter 320 is coupled to the logic circuit 310 to receive the logic signal SP. The level converter 320 can generate the original switching signal SWP and the original switching signal SWPB. The level converter 330 is coupled to the logic circuit 310 to receive the logic signal SN. The level converter 330 can generate the original switching signal SWN and the original switching signal SWNB.

FIG. 4 is a circuit block diagram illustrating the output switching circuit OSW_1 shown in FIG. 2 according to an embodiment of the present invention. Other output switching circuits OSW_2 ˜ OSW_m and switching control signals SC2 ˜ SCm shown in FIG. 2 can be deduced by referring to the related descriptions of the output switching circuit OSW_1 and switching control signal SC1 shown in FIG. In the embodiment shown in FIG. 4 , the switching control signal SC1 includes a switching signal SWP1 , a switching signal SWP1B, a switching signal SWN1 and a switching signal SWN1B. The switching signal SWP1B is an inverted signal of the switching signal SWP1. The switching signal SWN1B is an inverted signal of the switching signal SWN1.

Please refer to FIG. 2 and FIG. 4 . The output switching circuit OSW_1 of the channel pair CHP_1 shown in FIG. 4 includes a buffer 410 , a buffer 420 , a buffer 430 , a buffer 440 , a switch 450 , a switch 460 , a switch 470 and a switch 480 . The input end of the buffer 410 is coupled to the routing circuit 212 to receive the switching signal SWP1. The input end of the buffer 420 is coupled to the routing circuit 212 to receive the switching signal SWP1B. The input end of the buffer 430 is coupled to the routing circuit 212 to receive the switching signal SWN1. The input end of the buffer 440 is coupled to the routing circuit 212 to receive the switching signal SWN1B.

In the embodiment shown in FIG. 4 , the switches 450 and 480 may be p-channel metal oxide semiconductor (PMOS) transistors, and the switches 460 and 470 may be n-channel metal oxide semiconductors ( n-channel metal oxide semiconductor, NMOS) transistor. However, in other embodiments, the implementation of switch 450 , switch 460 , switch 470 , and switch 480 should not be limited to FIG. 4 .

The control terminal of the switch 450 is coupled to the output terminal of the buffer 410 . The first terminal of the switch 450 is coupled to the first input terminal of the output switching circuit OSW_1 , that is, coupled to the positive polarity amplifier OP+ of the positive polarity channel CH_1 . The second terminal of the switch 450 is coupled to the first output terminal of the output switching circuit OSW_1 , that is, coupled to the display panel 10 . The control terminal of the switch 460 is coupled to the output terminal of the buffer 420 . The first terminal of the switch 460 is coupled to the second input terminal of the output switching circuit OSW_1, that is, coupled to the negative amplifier OP- of the negative channel CH_2. The second terminal of the switch 460 is coupled to the second output terminal of the output switching circuit OSW_1 , that is, coupled to the display panel 10 . The control terminal of the switch 470 is coupled to the output terminal of the buffer 430 . The first terminal of the switch 470 is coupled to the second input terminal of the output switching circuit OSW_1. The second terminal of the switch 470 is coupled to the first output terminal of the output switching circuit OSW_1. The control terminal of the switch 480 is coupled to the output terminal of the buffer 440 . The first terminal of the switch 480 is coupled to the first input terminal of the output switching circuit OSW_1. The second terminal of the switch 480 is coupled to the second output terminal of the output switching circuit OSW_1.

FIG. 5 is a circuit block diagram illustrating the routing circuit 212 shown in FIG. 2 according to an embodiment of the present invention. The routing circuit 212 shown in FIG. 5 includes a plurality of switches, wherein the switches are controlled by the polarity inversion configuration signal DOTC. Please refer to FIG. 2 , FIG. 3 , FIG. 4 and FIG. 5 , the polarity control signal SC includes the original switching signals SWP, SWPB, SWN and SWNB. The switching control signal SC1 includes a switching signal SWP1, a switching signal SWP1B, a switching signal SWN1 and a switching signal SWN1B.

The routing circuit 212 can select to output the original switching signal SWP as the switching signal SWP1 to the output switching circuit OSW_1 . The routing circuit 212 can select and output the original switching signal SWPB as the switching signal SWP1B to the output switching circuit OSW_1. The routing circuit 212 can select and output the original switching signal SWN as the switching signal SWN1 to the output switching circuit OSW_1 . The routing circuit 212 can select and output the original switching signal SWNB as the switching signal SWN1B to the output switching circuit OSW_1 .

By analogy with the description of the switching control signal SC1, the switching control signal SC2 may include a switching signal SWP2, a switching signal SWP2B, a switching signal SWN2 and a switching signal SWN2B. The routing circuit 212 can select to output one of the original switching signal SWP and the original switching signal SWNB as the switching signal SWP2 to the output switching circuit OSW_2 according to the polarity inversion configuration signal DOTC. The routing circuit 212 can select to output one of the original switching signal SWPB and the original switching signal SWN as the switching signal SWP2B to the output switching circuit OSW_2 according to the polarity inversion configuration signal DOTC. The routing circuit 212 can select to output one of the original switching signal SWN and the original switching signal SWPB as the switching signal SWN2 to the output switching circuit OSW_2 according to the polarity inversion configuration signal DOTC. The routing circuit 212 can select to output one of the original switching signal SWNB and the original switching signal SWP as the switching signal SWN2B to the output switching circuit OSW_2 according to the polarity inversion configuration signal DOTC.

For example, when the polarity reversal configuration signal DOTC is in the first logic state, the routing circuit 212 can select the original switching SWP signal as the switching signal SWP2, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWP2B, and the routing circuit 212 can select the original switching signal SWPB as the switching signal SWP2B. 212 can select the original switching signal SWN as the switching signal SWN2, and the routing circuit 212 can select the original switching signal SWNB as the switching signal SWN2B. When the polarity inversion configuration signal DOTC is in the second logic state (different from the first logic state), the routing circuit 212 can select the original switching signal SWNB as the switching signal SWP2, and the routing circuit 212 can select the original switching signal SWN as the switching signal For the signal SWP2B, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWN2, and the routing circuit 212 can select the original switching signal SWP as the switching signal SWN2B.

By analogy with the description of the switching control signal SC1, the switching control signal SC3 (not shown) may include a switching signal SWP3, a switching signal SWP3B, a switching signal SWN3 and a switching signal SWN3B. The routing circuit 212 can select one of the original switching signal SWP and the original switching signal SWNB as the switching signal SWP3 according to the polarity inversion configuration signal DOTC. The routing circuit 212 can select one of the original switching signal SWPB and the original switching signal SWN as the switching signal SWP3B according to the polarity inversion configuration signal DOTC. The routing circuit 212 can select one of the original switching signal SWN and the original switching signal SWPB as the switching signal SWN3 according to the polarity inversion configuration signal DOTC. The routing circuit 212 can select one of the original switching signal SWNB and the original switching signal SWP as the switching signal SWN3B according to the polarity inversion configuration signal DOTC.

By analogy with the description of the switching control signal SC1, the switching control signal SC4 (not shown) may include a switching signal SWP4, a switching signal SWP4B, a switching signal SWN4 and a switching signal SWN4B. The routing circuit 212 can select the original switching signal SWP as the switching signal SWP4. The routing circuit 212 can select the original switching signal SWPB as the switching signal SWP4B. The routing circuit 212 can select the original switching signal SWN as the switching signal SWN4. The routing circuit 212 can select the original switching signal SWNB as the switching signal SWNB.

Therefore, when the polarity inversion configuration signal DOTC is in the first logic state (eg, logic state “0”) (in a certain application scenario), the routing circuit 212 can change the logic configuration of the switching control signals SC1 ˜SCm To set the polarity configuration of the data lines D1 to Dn as "+ - + - + - + - ..." or "- + - + - + - + ..." (determined by the original switching signals SWP and SWN). When the polarity inversion configuration signal DOTC is in the second logic state (eg, logic state “1”) (in another application scenario), the routing circuit 212 can change the logic configuration of the switching control signals SC1 ˜SCm to Set the polarity configuration of the data lines D1~Dn as "+ - - + - + + - ..." or "- + + - + - - + ..." (determined by the original switching signals SWP and SWN).

FIG. 6 is a circuit block diagram illustrating the routing circuit 212 shown in FIG. 2 according to another embodiment of the present invention. The routing circuit 212 shown in FIG. 6 includes a decoding circuit 610 and a plurality of switches, wherein the switches are all controlled by the decoding results of the decoding circuit 610 (control signals CT1 , CT2 and CT3 ). The decoding circuit 610 can decode the polarity inversion configuration signal DOTC to generate a decoding result. For example, the relationship between the polarity inversion configuration signal DOTC and the decoding result may be as shown in Table 1 below. Table 1: Relationship between the inputs and outputs of the decoding circuit 610 enter output DOTC2 DOTC1 CT1 CT2 CT3 0 0 1 0 0 0 1 0 1 0 1 0 or 1 0 0 1

In Table 1, the bits DOTC2 and DOTC1 of the polarity inversion configuration signal DOTC are in the logic state "0", while the control signals CT1, CT2 and CT3 (decoding result) are in the logic state "1", "0" and "0" 0". When the bits DOTC2 and DOTC1 of the polarity inversion configuration signal DOTC are in the logic states "0" and "1", the control signals CT1, CT2 and CT3 are in the logic states "0", "1" and "0". When the bits DOTC2 and DOTC1 of the polarity inversion configuration signal DOTC are in the logic states of "1" and "0" (or both are "1"), the control signals CT1, CT2 and CT3 are in the logic states of "0", "0" and "1".

Please refer to FIG. 2 , FIG. 3 , FIG. 4 and FIG. 6 , the polarity control signal SC includes the original switching signals SWP, SWPB, SWN and SWNB. The switching control signal SC1 includes a switching signal SWP1, a switching signal SWP1B, a switching signal SWN1 and a switching signal SWN1B. The routing circuit 212 can select to output the original switching signal SWP as the switching signal SWP1 to the output switching circuit OSW_1 . The routing circuit 212 can select and output the original switching signal SWPB as the switching signal SWP1B to the output switching circuit OSW_1. The routing circuit 212 can select and output the original switching signal SWN as the switching signal SWN1 to the output switching circuit OSW_1 . The routing circuit 212 can select and output the original switching signal SWNB as the switching signal SWN1B to the output switching circuit OSW_1 .

By analogy with the description of the switching control signal SC1, the switching control signal SC2 may include a switching signal SWP2, a switching signal SWP2B, a switching signal SWN2 and a switching signal SWN2B. The routing circuit 212 can select to output one of the original switching signal SWP and the original switching signal SWNB as the switching signal SWP2 to the output switching circuit OSW_2 according to the decoding results (the control signals CT1 , CT2 and CT3 ). The routing circuit 212 can select one of the original switching signal SWPB and the original switching signal SWN as the switching signal SWP2B to output to the output switching circuit OSW_2 according to the decoding result. The routing circuit 212 can select one of the original switching signal SWN and the original switching signal SWPB as the switching signal SWN2 to output to the output switching circuit OSW_2 according to the decoding result. The routing circuit 212 can select one of the original switching signal SWNB and the switching signal SWP as the switching signal SWN2B and output it to the output switching circuit OSW_2 according to the decoding result.

For example, when the decoding result is in the first logic state (for example, the control signals CT1, CT2 and CT3 are in logic states "1", "0" and "0"), the routing circuit 212 can select the original switching signal SWP as the switching signal SWP2, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWP2B, the routing circuit 212 can select the original switching signal SWN as the switching signal SWN2, and the routing circuit 212 can select the original switching signal SWNB as the switching signal SWN2B. When the decoding result is the second logic state or the third logic state (for example, the control signals CT1, CT2 and CT3 are logic states "0", "1" and "0", or the control signals CT1, CT2 and CT3 are logic states "0", "0" and "1"), the routing circuit 212 can select the original switching signal SWNB as the switching signal SWP2, the routing circuit 212 can select the original switching signal SWN as the switching signal SWP2B, and the routing circuit 212 can select the original switching signal SWPB As the switching signal SWN2, the routing circuit 212 can select the original switching signal SWP as the switching signal SWN2B.

By analogy with the description of the switching control signal SC1, the switching control signal SC3 (not shown) may include a switching signal SWP3, a switching signal SWP3B, a switching signal SWN3 and a switching signal SWN3B. When the decoding result is the first logic state (for example, the control signals CT1, CT2 and CT3 are logic states "1", "0" and "0"), the routing circuit 212 can select the original switching signal SWP as the switching signal SWP3, and the routing circuit 212 can select the original switching signal SWPB as the switching signal SWP3B, the routing circuit 212 can select the original switching signal SWN as the switching signal SWN3, and the routing circuit 212 can select the original switching signal SWNB as the switching signal SWN3B. When the decoding result is the second logic state or the third logic state (for example, the control signals CT1, CT2 and CT3 are logic states "0", "1" and "0", or the control signals CT1, CT2 and CT3 are logic states "0", "0" and "1"), the routing circuit 212 can select the original switching signal SWNB as the switching signal SWP3, the routing circuit 212 can select the original switching signal SWN as the switching signal SWP3B, and the routing circuit 212 can select the original switching signal SWPB As the switching signal SWN3, the routing circuit 212 can select the original switching signal SWP as the switching signal SWN3B.

By analogy with the description of the switching control signal SC1, the switching control signal SC4 (not shown) may include a switching signal SWP4, a switching signal SWP4B, a switching signal SWN4 and a switching signal SWN4B. When the decoding result is the first logic state or the second logic state (for example, the control signals CT1, CT2 and CT3 are logic states "1", "0" and "0", or the control signals CT1, CT2 and CT3 are logic states "0", "1" and "0"), the routing circuit 212 can select the original switching signal SWP as the switching signal SWP4, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWP4B, and the routing circuit 212 can select the original switching signal SWN As the switching signal SWN4, the routing circuit 212 can select the original switching signal SWNB as the switching signal SWN4B. When the decoding result is the third logic state (for example, the control signals CT1, CT2 and CT3 are logic states "0", "0" and "1"), the routing circuit 212 can select the original switching signal SWNB as the switching signal SWP4, and the routing circuit 212 can select the original switching signal SWN as the switching signal SWP4B, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWN4, and the routing circuit 212 can select the original switching signal SWP as the switching signal SWN4B.

Therefore, the relationship between the polarity inversion configuration signal DOTC and the polarity configuration of the data lines D1-Dn may be as shown in Table 2 below. In Table 2, when the polarity inversion configuration signal DOTC is in the first logic state (eg, logic state “00”) (in a certain application scenario), the routing circuit 212 can change the switching control signals SC1 ˜SCm logical configuration to set the polarity configuration of data lines D1~Dn as "+ - + - + - + - ..." or "- + - + - + - + ..." (determined by the original switching signals SWP and SWN) . When the polarity inversion configuration signal DOTC is in the second logic state (eg, logic state “01”) (in another application scenario), the routing circuit 212 can change the logic configuration of the switching control signals SC1 ˜ SCm to Set the polarity configuration of the data lines D1~Dn as "+ - - + - + + - ..." or "- + + - + - - + ..." (determined by the original switching signals SWP and SWN). When the polarity inversion configuration signal DOTC is in a third logic state (eg, logic state "10" or "11") (in another application scenario), the routing circuit 212 can change the switching control signals SC1 ˜SCm The logic configuration is to set the polarity configuration of the data lines D1-Dn as "+ - - + - + - + ..." or "- + + - + - + - ..." (determined by the original switching signals SWP and SWN). Table 2: The relationship between the polarity inversion configuration signal DOTC and the polarity configuration of the data lines D1~Dn DOTC D1 D2 D3 D4 D5 D6 D7 D8 00 + - + - + - + - 01 + - - + - + + - 10 or 11 + - - + - + - +

FIG. 7 is a circuit block diagram illustrating the routing circuit 212 shown in FIG. 2 according to still another embodiment of the present invention. The routing circuit 212 shown in FIG. 7 includes a decoding circuit 710 and a plurality of switches, wherein the switches are controlled by the decoding results of the decoding circuit 710 (control signals CA1, CA2, CB1, CB2, CC1, CC2, CD1 and CD2). The decoding circuit 710 can decode the polarity inversion configuration signal DOTC to generate a decoding result. For example, the relationship between the polarity inversion configuration signal DOTC and the decoding result may be as shown in Table 3 below. Table 3: Relationship between Input and Output of Decoding Circuit 710 enter output DOTC2 DOTC1 CA1 CA2 CB1 CB2 CC1 CC2 CD1 CD2 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 1 0 or 1 1 0 0 1 0 1 0 1

In Table 3, when the bits DOTC2 and DOTC1 of the polarity inversion configuration signal DOTC are both in logic state "0", the control signals CA1, CA2, CB1, CB2, CC1, CC2, CD1 and CD2 (the decoding result ) are the logical states "1", "0", "1", "0", "1", "0", "1" and "0". When the bits DOTC2 and DOTC1 of the polarity inversion configuration signal DOTC are in the logic state "0" and "1", the control signals CA1, CA2, CB1, CB2, CC1, CC2, CD1 and CD2 are in the logic state "1" ", "0", "0", "1", "0", "1", "1" and "0". When the bits DOTC2 and DOTC1 of the polarity inversion configuration signal DOTC are in the logic states of "1" and "0" (or both are "1"), the control signals CA1, CA2, CB1, CB2, CC1, CC2, CD1 and CD2 are logic states "1", "0", "0", "1", "0", "1", "0" and "1".

Please refer to FIG. 2 , FIG. 3 , FIG. 4 and FIG. 7 , the polarity control signal SC includes the original switching signals SWP, SWPB, SWN and SWNB. The switching control signal SC1 includes a switching signal SWP1, a switching signal SWP1B, a switching signal SWN1 and a switching signal SWN1B. The routing circuit 212 can select to output the original switching signal SWP as the switching signal SWP1 to the output switching circuit OSW_1 . The routing circuit 212 can select and output the original switching signal SWPB as the switching signal SWP1B to the output switching circuit OSW_1. The routing circuit 212 can select and output the original switching signal SWN as the switching signal SWN1 to the output switching circuit OSW_1 . The routing circuit 212 can select and output the original switching signal SWNB as the switching signal SWN1B to the output switching circuit OSW_1 .

By analogy with the description of the switching control signal SC1, the switching control signal SC2 may include a switching signal SWP2, a switching signal SWP2B, a switching signal SWN2 and a switching signal SWN2B. The routing circuit 212 can select to output one of the original switching signal SWP and the original switching signal SWNB as the switching signal SWP2 to the output switching circuit OSW_2 according to the decoding result (the control signals CB1 and CB2 ). The routing circuit 212 can select one of the original switching signal SWPB and the original switching signal SWN as the switching signal SWP2B to output to the output switching circuit OSW_2 according to the decoding result (the control signals CB1 and CB2 ). The routing circuit 212 can select one of the original switching signal SWN and the original switching signal SWPB as the switching signal SWN2 to output to the output switching circuit OSW_2 according to the decoding result (the control signals CB1 and CB2 ). The routing circuit 212 can select one of the original switching signal SWNB and the switching signal SWP as the switching signal SWN2B to output to the output switching circuit OSW_2 according to the decoding result (the control signals CB1 and CB2 ).

For example, when the decoding result is the first logic state (eg, the control signals CB1 and CB2 are logic states "1" and "0"), the routing circuit 212 can select the original switching signal SWP as the switching signal SWP2, and the routing circuit 212 can Selecting the original switching signal SWPB as the switching signal SWP2B, the routing circuit 212 can select the original switching signal SWN as the switching signal SWN2, and the routing circuit 212 can select the original switching signal SWNB as the switching signal SWN2B. When the decoding result is the second logic state or the third logic state (for example, the control signals CB1 and CB2 are logic states "0" and "1"), the routing circuit 212 can select the original switching signal SWNB as the switching signal SWP2, and the routing circuit 212 The original switching signal SWN can be selected as the switching signal SWP2B, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWN2, and the routing circuit 212 can select the original switching signal SWP as the switching signal SWN2B.

By analogy with the description of the switching control signal SC1, the switching control signal SC3 (not shown) may include a switching signal SWP3, a switching signal SWP3B, a switching signal SWN3 and a switching signal SWN3B. When the decoding result is the first logic state (for example, the control signals CC1 and CC2 are logic states "1" and "0"), the routing circuit 212 can select the original switching signal SWP as the switching signal SWP3, and the routing circuit 212 can select the original switching signal SWPB is used as the switching signal SWP3B, the routing circuit 212 can select the original switching signal SWN as the switching signal SWN3, and the routing circuit 212 can select the original switching signal SWNB as the switching signal SWN3B. When the decoding result is the second logic state or the third logic state (for example, the control signals CC1 and CC2 are logic states "0" and "1"), the routing circuit 212 can select the original switching signal SWNB as the switching signal SWP3, and the routing circuit 212 The original switching signal SWN can be selected as the switching signal SWP3B, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWN3, and the routing circuit 212 can select the original switching signal SWP as the switching signal SWN3B.

By analogy with the description of the switching control signal SC1, the switching control signal SC4 (not shown) may include a switching signal SWP4, a switching signal SWP4B, a switching signal SWN4 and a switching signal SWN4B. When the decoding result is the first logic state or the second logic state (for example, the control signals CD1 and CD2 are logic states "1" and "0"), the routing circuit 212 can select the original switching signal SWP as the switching signal SWP4, and the routing circuit 212 The original switching signal SWPB can be selected as the switching signal SWP4B, the routing circuit 212 can select the original switching signal SWN as the switching signal SWN4, and the routing circuit 212 can select the original switching signal SWNB as the switching signal SWN4B. When the decoding result is the third logic state (for example, the control signals CD1 and CD2 are logic states "0" and "1"), the routing circuit 212 can select the original switching signal SWNB as the switching signal SWP4, and the routing circuit 212 can select the original switching signal SWN is used as the switching signal SWP4B, the routing circuit 212 can select the original switching signal SWPB as the switching signal SWN4, and the routing circuit 212 can select the original switching signal SWP as the switching signal SWN4B.

Therefore, when the polarity inversion configuration signal DOTC is in the first logic state (eg, logic state “00”) (in a certain application scenario), the routing circuit 212 can change the logic configuration of the switching control signals SC1 ˜SCm To set the polarity configuration of the data lines D1 to Dn as "+ - + - + - + - ..." or "- + - + - + - + ..." (determined by the original switching signals SWP and SWN). When the polarity inversion configuration signal DOTC is in the second logic state (eg, logic state “01”) (in another application scenario), the routing circuit 212 can change the logic configuration of the switching control signals SC1 ˜ SCm to Set the polarity configuration of the data lines D1~Dn as "+ - - + - + + - ..." or "- + + - + - - + ..." (determined by the original switching signals SWP and SWN). When the polarity inversion configuration signal DOTC is in a third logic state (eg, logic state "10" or "11") (in another application scenario), the routing circuit 212 can change the switching control signals SC1 ˜SCm The logic configuration is to set the polarity configuration of the data lines D1 to Dn as "+ - - + - + - + ..." or "- + + - + - + - ..." (determined by the original switching signals SWP and SWN).

According to different design requirements, the implementation of the blocks of the polarity inversion control circuit 210 , the signal generation circuit 211 and/or the routing circuit 212 may be hardware, firmware, software, namely program) or a combination of more of the above three.

In terms of hardware, the above-mentioned blocks of the polarity inversion control circuit 210 , the signal generating circuit 211 and/or the routing circuit 212 can be implemented as logic circuits on an integrated circuit. The above-mentioned related functions of the polarity inversion control circuit 210 , the signal generating circuit 211 and/or the routing circuit 212 can be implemented as hardware using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages. body. For example, the above-mentioned related functions of the polarity inversion control circuit 210, the signal generation circuit 211 and/or the routing circuit 212 can be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits circuit (Application-specific integrated circuit, ASIC), digital signal processor (digital signal processor, DSP), Field Programmable Gate Array (Field Programmable Gate Array, FPGA) and/or various logic blocks in other processing units, modules and circuits.

In the form of software and/or firmware, the above-mentioned related functions of the polarity inversion control circuit 210 , the signal generating circuit 211 and/or the routing circuit 212 can be implemented as programming codes. For example, the above-mentioned polarity inversion control circuit 210 , signal generating circuit 211 and/or routing circuit 212 can be implemented using common programming languages (eg, C, C++ or assembly language) or other suitable programming languages. The programming code may be recorded/stored in a recording medium, for example, the recording medium includes a read only memory (Read Only Memory, ROM), a storage device and/or a random access memory (Random Access Memory, RAM) . A computer, a central processing unit (CPU), a controller, a microcontroller or a microprocessor can read and execute the programming code from the recording medium, thereby achieving related functions. As the recording medium, a "non-transitory computer readable medium" can be used, and for example, a tape, a disk, a card, a semiconductor memory, a Programming logic circuits, etc. Furthermore, the program may be provided to the computer (or CPU) via any transmission medium (communication network, broadcast waves, or the like). The communication network is, for example, the Internet, wired communication, wireless communication, or other communication media.

To sum up, the signal generating circuit 211 of the above embodiments is configured to generate the polarity control signal SC (eg, the original switching signals SWP, SWPB, SWN and SWNB). The routing circuit 212 is coupled to the signal generating circuit 211 to receive the polarity control signal SC. The routing circuit 212 is configured to output a plurality of switching control signals SC1 ˜SCm corresponding to the polarity control signal SC to a plurality of output switching circuits OSW_1 ˜OSW_m of the multiple channel pairs CHP_1 ˜CHP_m of the source driver 200 . The routing circuit 212 can change the corresponding relationship between the polarity control signal SC and the switching control signals SC1 ˜SCm according to the polarity inversion configuration signal DOTC. Therefore, the polarity inversion control circuit 210 can adapt to different application situations to change the logic configuration of the switching control signals SC1 ˜SCm, so as to set the polarity configuration of the data lines D1 ˜Dn to the polarity configuration that meets customer requirements.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Display panel 20, 200: source driver 210: Polarity Inversion Control Circuit 211: Signal Generation Circuit 212: Routing Circuits 310: Logic Circuits 320, 330: Level converter 410, 420, 430, 440: Buffer 450, 460, 470, 480: switch 610, 710: Decoding circuit CH_1, CH_3, CH_n-1: Positive polarity channels CH_2, CH_4, CH_n: Negative polarity channels CHP_1, CHP_2, CHP_m, P_1, P_2, P_m: channel pair CA1, CA2, CB1, CB2, CC1, CC2, CD1, CD2, CT1, CT2, CT3: Control signals D1, D2, D3, D4, Dn-1, Dn: Data lines DAC: Digital to Analog Converter DOTC: Polarity Reversal Configuration Signal DOTC2, DOTC1: bits LCH: Latch LS: Level Converter OP+: Positive polarity amplifier OP-: Negative Polarity Amplifier OSW_1, OSW_2, OSW_m, OSW1, OSW2, OSWm: Output switching circuit P1, P2, Pm: Signal generation circuit POL: Polarity signal S1, S2, Sm, SC1, SC2, SCm: Switch control signal SC: Polarity Control Signal SN, SP: logic signal SWN, SWNB, SWP, SWPB: original switching signal SWN1, SWN1B, SWP1, SWP1B: Switch signal TP: Wire Latch Signal

FIG. 1 is a schematic diagram of a circuit block of a conventional source driver. FIG. 2 is a circuit block diagram of a source driver according to an embodiment of the present invention. FIG. 3 is a circuit block diagram illustrating the signal generating circuit shown in FIG. 2 according to an embodiment of the present invention. FIG. 4 is a circuit block diagram illustrating the output switching circuit shown in FIG. 2 according to an embodiment of the present invention. FIG. 5 is a circuit block diagram illustrating the routing circuit shown in FIG. 2 according to an embodiment of the present invention. FIG. 6 is a circuit block diagram illustrating the routing circuit shown in FIG. 2 according to another embodiment of the present invention. FIG. 7 is a circuit block diagram illustrating the routing circuit shown in FIG. 2 according to yet another embodiment of the present invention.

10: Display panel 200: source driver 210: Polarity Inversion Control Circuit 211: Signal Generation Circuit 212: Routing Circuits CH_1, CH_3, CH_n-1: Positive polarity channels CH_2, CH_4, CH_n: Negative polarity channels CHP_1, CHP_2, CHP_m: channel pair D1, D2, D3, D4, Dn-1, Dn: Data lines DAC: Digital to Analog Converter DOTC: Polarity Reversal Configuration Signal LCH: Latch LS: Level Converter OP+: Positive polarity amplifier OP-: Negative Polarity Amplifier OSW_1, OSW_2, OSW_m: Output switching circuit POL: Polarity signal SC: Polarity Control Signal SC1, SC2, SCm: switch control signal TP: Wire Latch Signal

Claims (19)

A source driver, comprising: a plurality of channel pairs suitable for driving a display panel, wherein each of the channel pairs includes a positive polarity channel, a negative polarity channel and an output switching circuit, a first of the output switching circuit An input terminal and a second input terminal are respectively coupled to an output terminal of the positive polarity channel and an output terminal of the negative polarity channel, and a first output terminal and a second output terminal of the output switching circuit are coupled to the display panel; and a polarity inversion control circuit, comprising: a signal generating circuit configured to generate a polarity control signal; and a routing circuit coupled to the signal generating circuit to receive the polarity control signal, configured as According to a polarity inversion configuration signal, one of the plurality of original switching signals in the polarity control signal is selected as one of the plurality of switching control signals to be output to the output switching circuits, wherein the routing circuit is based on the The polarity inversion configuration signal changes the logic configuration of the switching control signals to change the corresponding relationship between the polarity control signal and the switching control signals. The source driver of claim 1, wherein the original switching signals include a first original switching signal and a second original switching signal, and the second original switching signal is an inverted signal of the first original switching signal , and the signal generating circuit includes: a logic circuit configured to generate a first logic signal according to a one-line latch signal and a polarity signal; and a first level converter coupled to the logic circuit to receive the The first logic signal is configured to generate the first original switching signal and the second original switching signal. The source driver of claim 2, wherein the logic circuit further generates a second logic signal according to the line latch signal and the polarity signal, and the original switching signals further include a third original switching signal and a first Four original switching signals, the fourth original switching signal is an inverted signal of the third original switching signal, and the signal generating circuit further includes: a second level converter, coupled to the logic circuit for receiving the first Two logic signals are configured to generate the third original switching signal and the fourth original switching signal. The source driver of claim 1, wherein any one of the switching control signals includes a first switching signal, a second switching signal, a third switching signal and a fourth switching signal, the second switching signal is an inversion signal of the first switching signal, the fourth switching signal is an inversion signal of the third switching signal, and the output switching circuit of any one of the channel pairs includes: a first buffer having An input terminal is coupled to the routing circuit to receive the first switching signal; a second buffer has an input terminal coupled to the routing circuit to receive the second switching signal; a third buffer has an input The terminal is coupled to the routing circuit to receive the third switching signal; a fourth buffer has an input terminal coupled to the routing circuit to receive the fourth switching signal; a first switch has a control terminal coupled to to an output end of the first buffer, wherein a first end of the first switch is coupled to the first input of the output switching circuit terminal, and a second terminal of the first switch is coupled to the first output terminal of the output switching circuit; a second switch has a control terminal coupled to an output terminal of the second buffer, wherein the A first end of the second switch is coupled to the second input end of the output switching circuit, and a second end of the second switch is coupled to the second output end of the output switching circuit; a third switch , has a control end coupled to an output end of the third buffer, wherein a first end of the third switch is coupled to the second input end of the output switching circuit, and a first end of the third switch Two terminals are coupled to the first output terminal of the output switching circuit; and a fourth switch has a control terminal coupled to an output terminal of the fourth buffer, wherein a first terminal of the fourth switch is coupled to The first input terminal of the output switching circuit and a second terminal of the fourth switch are coupled to the second output terminal of the output switching circuit. The source driver of claim 1, wherein the original switching signals include a first original switching signal, a second original switching signal, a third original switching signal and a fourth original switching signal, and the switching control One of the first switching control signals of the signals includes a first switching signal, a second switching signal, a third switching signal and a fourth switching signal, and the routing circuit selects the first original switching signal as the first switching signal signal, the routing circuit selects the second original switching signal as the second switching signal, the routing circuit selects the third original switching signal as the third switching signal, and the routing circuit selects the fourth original switching signal as the fourth switching signal. The source driver of claim 5, wherein a second switching control signal of the switching control signals comprises a fifth switching signal, a sixth switching signal, a seventh switching signal and an eighth switching signal, The routing circuit selects one of the first original switching signal and the fourth original switching signal as the fifth switching signal according to the polarity inversion configuration signal, and the routing circuit selects the first original switching signal according to the polarity inversion configuration signal One of the two original switching signals and the third original switching signal is used as the sixth switching signal, and the routing circuit selects one of the third original switching signal and the second original switching signal as the sixth switching signal according to the polarity inversion configuration signal The seventh switching signal, and the routing circuit selects one of the fourth original switching signal and the first original switching signal as the eighth switching signal according to the polarity inversion configuration signal. The source driver of claim 6, wherein when the polarity inversion configuration signal is a first logic state, the routing circuit selects the first original switching signal as the fifth switching signal, and the routing circuit selects the The second original switching signal is used as the sixth switching signal, the routing circuit selects the third original switching signal as the seventh switching signal, and the routing circuit selects the fourth original switching signal as the eighth switching signal; and when the When the polarity reversal configuration signal is a second logic state, the routing circuit selects the fourth original switching signal as the fifth switching signal, the routing circuit selects the third original switching signal as the sixth switching signal, and the routing circuit selects the third original switching signal as the sixth switching signal. The circuit selects the second original switching signal as the seventh switching signal, and the routing circuit selects the first original switching signal as the eighth switching signal. The source driver of claim 5, wherein the routing circuit comprises: a decoding circuit configured to decode the polarity inversion configuration signal to generate a decoding result; wherein a first of the switching control signals The two switching control signals include a fifth switching signal, a sixth switching signal, a seventh switching signal and an eighth switching signal, and the routing circuit selects the first original switching signal and the fourth original switching signal according to the decoding result One of the signals is used as the fifth switching signal, the routing circuit selects one of the second original switching signal and the third original switching signal as the sixth switching signal according to the decoding result, and the routing circuit selects according to the decoding result One of the third original switching signal and the second original switching signal is used as the seventh switching signal, and the routing circuit selects one of the fourth original switching signal and the first original switching signal as the first switching signal according to the decoding result Eight switching signals. The source driver of claim 8, wherein when the decoding result is a first logic state, the routing circuit selects the first original switching signal as the fifth switching signal, and the routing circuit selects the second original switching signal signal as the sixth switching signal, the routing circuit selects the third original switching signal as the seventh switching signal, and the routing circuit selects the fourth original switching signal as the eighth switching signal; and when the decoding result is a In the second logic state or a third logic state, the routing circuit selects the fourth original switching signal as the fifth switching signal, the routing circuit selects the third original switching signal as the sixth switching signal, and the routing circuit selects the second The original switching signal is used as the seventh switching signal, and the routing circuit selects the first original switching signal as the eighth switching signal. The source driver of claim 8, wherein when the decoding result is a first logic state or a second logic state, the routing circuit selects the first original switching signal as the fifth switching signal, and the routing circuit selecting the second original switching signal as the sixth switching signal, the routing circuit selecting the third original switching signal as the seventh switching signal, and the routing circuit selecting the fourth original switching signal as the eighth switching signal; and When the decoding result is a third logic state, the routing circuit selects the fourth original switching signal as the fifth switching signal, the routing circuit selects the third original switching signal as the sixth switching signal, and the routing circuit selects The second original switching signal is used as the seventh switching signal, and the routing circuit selects the first original switching signal as the eighth switching signal. A polarity inversion control circuit, comprising: a signal generation circuit configured to generate a polarity control signal; and a routing circuit coupled to the signal generation circuit to receive the polarity control signal, configured to be configured according to a polarity inversion a configuration signal to select one of the plurality of original switching signals in the polarity control signal as one of the plurality of switching control signals to output to a plurality of output switching circuits of a plurality of channel pairs of a source driver, wherein The routing circuit changes the logic configuration of the switching control signals according to the polarity inversion configuration signal to change the corresponding relationship between the polarity control signal and the switching control signals. The polarity inversion control circuit of claim 11, wherein the original switching signals include a first original switching signal and a second original switching signal, and the second original switching signal is an inverse of the first original switching signal a phase signal, and the signal generating circuit includes: a logic circuit configured to generate a first logic signal according to a one-line latch signal and a polarity signal; and a first level converter coupled to the logic circuit to The first logic signal is received and configured to generate the first original switching signal and the second original switching signal. The polarity inversion control circuit of claim 12, wherein the logic circuit further generates a second logic signal according to the line latch signal and the polarity signal, and the original switching signals further comprise a third original switching signal and a fourth original switching signal, the fourth original switching signal is an inverted signal of the third original switching signal, and the signal generating circuit further includes: a second level converter, coupled to the logic circuit for receiving The second logic signal is configured to generate the third original switching signal and the fourth original switching signal. The polarity inversion control circuit of claim 11, wherein the original switching signals include a first original switching signal, a second original switching signal, a third original switching signal and a fourth original switching signal, and the One of the first switching control signals of the switching control signals includes a first switching signal, a second switching signal, a third switching signal and a fourth switching signal, and the routing circuit selects the first original switching signal as the first switching signal. a switching signal, the routing circuit selects the second original switching signal as the second switching signal, and the routing circuit selects the third original switching signal as the third switching signal a switching signal, and the routing circuit selects the fourth original switching signal as the fourth switching signal. The polarity inversion control circuit of claim 14, wherein a second switching control signal of the switching control signals comprises a fifth switching signal, a sixth switching signal, a seventh switching signal and an eighth switching signal signal, the routing circuit selects one of the first original switching signal and the fourth original switching signal as the fifth switching signal according to the polarity inversion configuration signal, and the routing circuit selects according to the polarity inversion configuration signal One of the second original switching signal and the third original switching signal is used as the sixth switching signal, and the routing circuit selects one of the third original switching signal and the second original switching signal according to the polarity inversion configuration signal As the seventh switching signal, and the routing circuit selects one of the fourth original switching signal and the first original switching signal as the eighth switching signal according to the polarity inversion configuration signal. The polarity inversion control circuit of claim 15, wherein when the polarity inversion configuration signal is a first logic state, the routing circuit selects the first original switching signal as the fifth switching signal, and the routing circuit selecting the second original switching signal as the sixth switching signal, the routing circuit selecting the third original switching signal as the seventh switching signal, and the routing circuit selecting the fourth original switching signal as the eighth switching signal; and When the polarity inversion configuration signal is a second logic state, the routing circuit selects the fourth original switching signal as the fifth switching signal, and the routing circuit selects the third original switching signal as the sixth switching signal, The routing circuit selects the second primary switch The signal is used as the seventh switching signal, and the routing circuit selects the first original switching signal as the eighth switching signal. The polarity inversion control circuit of claim 14, wherein the routing circuit comprises: a decoding circuit configured to decode the polarity inversion configuration signal to generate a decoding result; wherein among the switching control signals A second switching control signal includes a fifth switching signal, a sixth switching signal, a seventh switching signal and an eighth switching signal, and the routing circuit selects the first original switching signal and the fourth switching signal according to the decoding result One of the original switching signals is used as the fifth switching signal, the routing circuit selects one of the second original switching signal and the third original switching signal as the sixth switching signal according to the decoding result, and the routing circuit is based on the decoding result One of the third original switching signal and the second original switching signal is selected as the seventh switching signal, and the routing circuit selects one of the fourth original switching signal and the first original switching signal as the decoding result according to the decoding result the eighth switching signal. The polarity inversion control circuit of claim 17, wherein when the decoding result is a first logic state, the routing circuit selects the first original switching signal as the fifth switching signal, and the routing circuit selects the second switching signal The original switching signal is used as the sixth switching signal, the routing circuit selects the third original switching signal as the seventh switching signal, and the routing circuit selects the fourth original switching signal as the eighth switching signal; and when the decoding result When it is a second logic state or a third logic state, the routing circuit the routing circuit selects the fourth original switching signal as the fifth switching signal, the routing circuit selects the third original switching signal as the sixth switching signal, the routing circuit selects the second original switching signal as the seventh switching signal, and The routing circuit selects the first original switching signal as the eighth switching signal. The polarity inversion control circuit of claim 17, wherein when the decoding result is a first logic state or a second logic state, the routing circuit selects the first original switching signal as the fifth switching signal, the The routing circuit selects the second original switching signal as the sixth switching signal, the routing circuit selects the third original switching signal as the seventh switching signal, and the routing circuit selects the fourth original switching signal as the eighth switching signal ; and when the decoding result is a third logic state, the routing circuit selects the fourth original switching signal as the fifth switching signal, the routing circuit selects the third original switching signal as the sixth switching signal, the routing The circuit selects the second original switching signal as the seventh switching signal, and the routing circuit selects the first original switching signal as the eighth switching signal.

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