TWI769017B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes: a substrate, a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composite blocking layer. The buffer layer is on the substrate. The channel layer is on the buffer layer. The barrier layer is on the channel layer. The doped compound semiconductor layer is on the barrier layer. The composite blocking layer is on the doped compound semiconductor layer, the composite blocking layer and the barrier layer include a same Group III element,and an atom percent of the same Group III element in the composite blocking layer increases with a distance from the doped compound semiconductor layer.

Description

semiconductor structure

Embodiments of the present invention relate to semiconductor structures, particularly semiconductor structures having composite barrier layers.

GaN-based semiconductor materials have many excellent material properties, such as high thermal resistance, wide band-gap, high electron saturation rate, and better heat dissipation. Gallium nitride based semiconductor materials are suitable for high frequency operation and high temperature environments. In recent years, GaN-based semiconductor materials have been used in fast charging equipment, wireless communication base station power supply modules, electric vehicle related components, or other high electron mobility transistors (HEMTs) with heterointerface structures. installation.

High electron mobility transistors, also known as heterostructure FETs (HFETs) or modulation-doped FETs (MODFETs), include semiconductors with different energy gaps material, a two-dimensional electron gas (2DEG) layer is generated at the interface of adjacent different semiconductor materials. High electron mobility transistors may be affected by processes (eg, doping or etching processes) during processing, resulting in poor electrical performance or uniformity. Therefore, developing a structure that can further improve the performance and reliability of the high electron mobility transistor device is still one of the current research topics in the industry.

An embodiment of the present invention provides a semiconductor structure, including: a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; a doped compound semiconductor layer on the barrier layer; and A composite barrier layer on the doped compound semiconductor layer, wherein the composite barrier layer and the barrier layer comprise the same Group III element, and the same atomic percentage of the same Group III element in the composite barrier layer increases with distance from doped Hetero compound semiconductor layer increases.

In some embodiments, the composite barrier layer includes a first barrier layer and a second barrier layer on the first barrier layer.

In some embodiments, the composite barrier layer further includes a third barrier layer located between the first barrier layer and the second barrier layer.

In some embodiments, the second barrier layer includes AlN or _{AlxGa ( 1-x )} N, where 0 < x < 1.

In some embodiments, the first barrier layer, the second barrier layer, and the third barrier layer are each p-type doped or undoped.

The following disclosure provides numerous embodiments, or examples, for implementing various elements of the provided subject matter. Specific examples of elements and their configurations are described below to simplify the description of embodiments of the invention. Of course, these are only examples, and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. Additionally, embodiments of the invention may use repeated reference numerals in various instances. This repetition is for the purpose of brevity and clarity and is not intended to represent the relationship between the different embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms related to joining and connecting, such as "connected", "interconnected", etc., unless otherwise defined, may mean that the two structures are in direct contact, or may also mean that the two structures are not in contact with each other. Direct contact, where there are other structures placed between the two structures. And the terms of joining and connecting can also include the case where both structures are movable, or both structures are fixed.

Furthermore, spatially relative terms such as "below", "below", "lower", "above", "higher" and the like may be used for ease of description The relationship between one component or feature(s) and another component(s) or feature(s) in a drawing. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is turned in a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

The terms "about", "approximately" and "approximately" as used herein generally mean within ±20%, preferably within ±10%, and more preferably within ±5% of a given value, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. For example, the term "about 5 nm" can encompass a size range from 4.5 nm to 5.5 nm. The numerical value given in the text is an approximate numerical value, that is, the given numerical value may still imply “about”, “approximately” and “approximately” without specifying “about”, “approximately” or “approximately”. ' meaning.

Some embodiments of the invention are described below, and additional steps may be provided before, during, and/or after the various stages described in these embodiments. Some of the stages described may be replaced or omitted in different embodiments. Additional components may be added to the semiconductor structures of embodiments of the present invention. Some of the components described may be replaced or omitted in different embodiments. Although some of the embodiments discussed are performed in a particular order of steps, the steps may be performed in another logical order.

Some embodiments of the present invention provide semiconductor structures with composite barrier layers, which can avoid adverse effects of doping, etching, or other processes on the semiconductor structures, and further improve electrical performance. In addition, in some embodiments, the semiconductor structure has a capping layer, and in addition to protecting other components, the configuration of the capping layer can also be adjusted according to different process or design requirements.

FIG. 1 is a cross-sectional view illustrating a semiconductor structure 10 according to some embodiments of the present invention. The semiconductor structure 10 includes a substrate 100 , a buffer layer 102 , a channel layer 104 , a barrier layer 106 , a doped compound semiconductor layer 108 , and a composite blocking layer 110 . The substrate 100 may include: elemental (single element) semiconductors such as silicon (Si) or germanium (Ge); compound semiconductors such as silicon carbide (silicon carbide), gallium arsenide (GaAs), gallium phosphide (GaP), phosphide Indium (InP), Indium Arsenide (InAs) and/or Indium Antimonide (InSb); alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum arsenide Gallium (AlGaAs), Gallium Indium Arsenide (GaInAs), Gallium Indium Phosphide (GaInP) and/or Gallium Indium Arsenide Phosphide (GaInAsP).

In some embodiments, the substrate 100 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al ₂ O ₃ ) substrate (or referred to as a sapphire substrate), a glass substrate , or other similar substrates. In some embodiments, the substrate 100 may include a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may include a ceramic material, and the ceramic material includes a metal inorganic material. For example, the ceramic substrate may comprise: silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina. In other embodiments, the substrate 100 may be a semiconductor on insulator substrate, such as silicon on insulator or silicon germanium on insulator (SGOI).

In semiconductor structures, the lattice structure, coefficient of thermal expansion, or other material properties of the substrate may be different from the upper components (eg, the channel layer 104 or other components), so strain may develop at or near the interface of the substrate and the upper components , resulting in defects such as cracks or warpage. In some embodiments, the buffer layer 102 is disposed on the substrate 100 to relieve strain in components formed over the buffer layer 102 (eg, the channel layer 104 ), thereby preventing defect formation. The material of the buffer layer 102 may include: AlN, GaN, AlxGa1 _{- xN} (wherein 0<x<1), a combination of the foregoing, or other similar materials. The buffer layer 102 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), combinations of the foregoing, or other methods.

In some embodiments, the channel layer 104 is disposed on the buffer layer 102 , and the material of the channel layer 104 includes one or more group III-V compound semiconductor materials, such as group III nitrides. For example, the material of the channel layer 104 may include: GaN, AlGaN, AlInN, InGaN, InAlGaN, other suitable materials, or a combination of the foregoing. In some embodiments, the channel layer 104 may be doped with n-type dopants or p-type dopants. by metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), atomic layer deposition (ALD), other suitable methods, or The combination of the foregoing forms the channel layer 104 .

In some embodiments using a GaN layer as the channel layer, the breakdown voltage of the high electron mobility transistor depends primarily on the thickness of the GaN layer. For example, increasing the thickness of the GaN layer can effectively increase the breakdown voltage of high electron mobility transistors. In such an embodiment, in order to deposit the GaN material on the substrate during the process of forming the GaN layer, a substrate with high thermal conductivity and high mechanical strength needs to be used, otherwise the substrate may be bent or even cracked. For example, compared with silicon (Si) substrates, AlN substrates have higher thermal conductivity and mechanical strength, so a thicker GaN layer can be formed on the AlN substrates to avoid bending or cracking of the substrates. It should be noted that the aforementioned use of the AlN substrate and the formation of the GaN layer thereon is only an example, and does not limit the material of the substrate or the channel layer used in the embodiments of the present invention. According to different process conditions and design requirements, the GaN layer or the channel layer including other materials can be formed on other substrates.

In some embodiments, the barrier layer 106 is disposed on the channel layer 104 , and the material of the barrier layer 106 includes a ternary III-V compound semiconductor, such as a III-nitride. For example, the material of the barrier layer 106 may be AlGaN, AlInN, or a combination thereof. In other embodiments, the material of the barrier layer 106 includes: GaN, AlN, GaAs, GaInP, AlGaAs, InP, InAlAs, InGaAs, other suitable III-V group materials, or a combination of the foregoing. In some embodiments, the barrier layer 106 may be doped, eg, doped with an n-type dopant or a p-type dopant. The barrier layer 106 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, combinations of the foregoing, or other methods.

According to some embodiments of the present invention, the materials of the channel layer 104 and the barrier layer 106 are different, and their interface is a heterojunction, so the lattice of the channel layer 104 and the barrier layer 106 do not match, which may cause stress and The piezoelectric polarization effect is caused, and the bonding of group III metals (eg, Al, Ga, or In) to nitrogen is more ionic, resulting in spontaneous polarization. Due to the difference in energy gap between the channel layer 104 and the barrier layer 106 and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) (not shown) is formed between the channel layer 104 and the barrier layer. on the hetero interface between layers 106 . In some embodiments, the semiconductor structure includes a high electron mobility transistor (HEMT) utilizing a two-dimensional electron gas (2DEG) as a conductive carrier.

Referring to FIG. 1 , in some embodiments, the semiconductor structure 10 includes a multi-layer stack formed by a doped compound semiconductor layer 108 disposed on the barrier layer 106 and a composite barrier layer 110 on the doped compound semiconductor layer 108 . stack) (or multi-layer mesa). In some embodiments, the doped compound semiconductor layer 108 includes a p-type doped III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or other III-V semiconductors. In other embodiments, the doped compound semiconductor layer 108 includes p-type doped II-VI semiconductors, such as CdS, CdTe, ZnS, or other II-VI semiconductors. The doped compound semiconductor layer 108 may be formed by metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, a combination of the foregoing, or other methods. In some embodiments, the doped compound semiconductor layer 108 may be doped, for example, the dopants include: magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be), strontium (Sr) , barium (Ba), radium (Ra), carbon (C), silver (Ag), gold (Au), lithium (Li) or sodium (Na), so that the doped compound semiconductor layer 108 is p-type doped. In some embodiments, the doping concentration of the doped compound semiconductor layer 108 is about 1E19 cm ⁻³ to about 4E19 cm ⁻³ , eg, about 2.8E19 cm ⁻³ .

In semiconductor structures, due to differences in potential energy between different components, voltages applied during operation, or other process/operating conditions, carriers in doped components may migrate to other adjacent components, causing adverse effects influences. For example, the carriers of the doped compound semiconductor layer may be affected by the aforementioned effects and move to the gate components formed subsequently, resulting in leakage and carrier trapping. In addition, dopants in doped components may diffuse to other adjacent components, causing adverse effects such as leakage and carrier trapping as previously described. During the gate switching process, the trapped carriers will cause the threshold voltage shift (V _T shift) to reduce the gate switching efficiency. This may increase the time required for the device to turn on causing a gate lag. Generally speaking, the doping concentration of the doped compound semiconductor layer is positively correlated with the carrier concentration that is influenced to move to other adjacent components and the doping concentration that diffuses to adjacent other components. However, the predetermined threshold voltage of the device mainly depends on the doping concentration of the doped compound semiconductor layer. If the doping concentration of the doped compound semiconductor layer is adjusted to avoid leakage and carrier trapping, the predetermined threshold voltage will be changed. This can cause the device to fail to achieve the desired performance for which it was designed. On the other hand, if the doping concentration of the doped compound semiconductor layer is relatively high, such as 2.8E19 cm ^-3 , although the required threshold voltage (Vt) can be achieved, it is also prone to high gate leakage current and gate delay. Therefore, a composite doped compound semiconductor layer is required to eliminate this side effect.

According to some embodiments of the present invention, disposing the composite barrier layer 110 on the doped compound semiconductor layer 108 can suppress the gate leakage caused by the doping of high-concentration dopants (eg, high-concentration magnesium or other p-type dopants). current. In some embodiments, composite barrier layer 110 and barrier layer 106 comprise the same group III element (or group III element), and the atomic percentage of the same group III element in composite barrier layer 110 increases with distance Doping the compound semiconductor layer 108 increases. In other words, the composite barrier layer 110 has an increasing group III element concentration gradient in a direction away from the doped compound semiconductor layer 108 . The composite barrier layer 110 may be formed by metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, atomic layer deposition, other suitable methods, or a combination of the foregoing. In one embodiment, the composite barrier layer 110 is grown in situ in a metal organic chemical vapor deposition process chamber for forming the doped compound semiconductor layer 108 . In some embodiments, the process of forming the doped compound semiconductor layer 108 and the composite barrier layer 110 includes: sequentially depositing the doped compound semiconductor material layer and the composite barrier material layer on the barrier layer 106 , and patterning the doped compound semiconductor material material layer and composite barrier material layer to expose barrier layer 106 to form a multi-layer stack or multi-layer platform of doped compound semiconductor layer 108 and composite barrier layer 110 . The patterning process includes (but is not limited to): a lithography process and an etching process. In some embodiments, the lithography process may include photoresist coating, soft baking, hard baking, mask aligning, exposure, Post-exposure baking, developing photoresist, rinsing, drying, or other suitable processes. In some embodiments, the etching process may include a dry etching process, a wet etching process, or a combination thereof. For example, the dry etching process may include a reactive ion etching (RIE) process or a plasma etching process. In some embodiments where the doped compound semiconductor layer 108 is doped with magnesium or other p-type dopants, the composite barrier layer 110 may interrupt the growth of magnesium or other p-type dopants (ie, provide a good barrier to dopant diffusion) ), blocking the memory effect of magnesium or other dopants, thereby effectively obtaining lower doping of magnesium or other p-type dopants than the doped compound semiconductor layer to improve electrical performance. In some embodiments, the doping concentration of the doped compound semiconductor layer 108 is about 1E19 cm ⁻³ to about 4E19 cm ⁻³ , eg, about 2.8E19 cm ⁻³ , and the doping concentration of the composite barrier layer 110 is about 5E17 cm ⁻³ . to about 5E18 cm ^-3 , for example about 2E18 cm ^-3 .

2-4 are cross-sectional views illustrating the composite barrier layer 110 according to some embodiments of the present invention. In these embodiments, the composite barrier layer 110 includes at least two layers, each including a Group III element. For example, the group III elements may include boron (B), aluminum (Al), gallium (Ga), or indium (In), or other group III elements. 2, in some embodiments, the composite barrier layer 110 includes a first barrier layer 110a and a second barrier layer 110b thereon. The first barrier layer 110a and the first barrier layer 110a can be sequentially formed by metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, atomic layer deposition, other suitable methods, or a combination of the foregoing. Two barrier layers 110b. In some embodiments, the atomic percentage of the Group III element of the second barrier layer 110b increases away from the doped compound semiconductor layer 108 . In some embodiments, the first barrier layer 110a may be an AlGaN layer and the second barrier layer 110b may be an AlN layer or an _{AlxGa ( 1-x )} N layer (0<x<1). In some embodiments, the x value representing the aluminum content in the _{AlxGa ( 1-x )} N layer may be variable, with the x value increasing in a direction away from the doped compound semiconductor layer 108 (the x value still ranges from 0 to 1, that is, 0 < x < 1). In other words, the _{AlxGa ( 1-x )} N layer has a concentration gradient of aluminum. In some embodiments, the composite barrier layer 110 with an aluminum (or other Group III element) concentration gradient can provide a stress buffer between the layers above and below it to mitigate or prevent damage caused by the material, At the same time, the polarization between the barrier layer and the doped compound semiconductor layer can be eliminated, avoiding the occurrence of additional carrier trapping. In some embodiments, the composite barrier layer 110 is p-type doped or undoped. For example, the first barrier layer 110a may be p-type doped or undoped and the second barrier layer 110b may be p-type doped or undoped. In the embodiment in which the composite barrier layer 110 is p-type doped, the doping concentration of the composite barrier layer 110 is much smaller than the doping concentration of the doped compound semiconductor layer 108 . For example, the doping concentration of the composite barrier layer 110 is higher than that of the doping The doping concentration of the hetero compound semiconductor layer 108 is 1 to 2 orders of magnitude smaller. In these embodiments, the doping concentration of the first barrier layer 110a is about 5E17 cm ^-3 to about 5E18 cm ^-3 , eg, about 2E18 cm ^-3 , and the doping concentration of the second barrier layer 110b is about 2E17 cm ^-3 To about 2E18 cm ^-3 (eg about 8E17 cm ^-3 ) or about 5E16 cm ^-3 to about 5E17 cm ^-3 (eg about 2E17 cm ^-3 ). It should be noted that, in some embodiments, the term "undoped feature" refers to the feature that is not doped using diffusion or ion implantation processes. However, during subsequent processing, dopants may inadvertently diffuse into the components with low or negligible dopant concentrations.

3, in some embodiments, the composite barrier layer 110 includes a first barrier layer 110a, a third barrier layer 110c on the first barrier layer 110a, and a second barrier layer 110b on the third barrier layer 110c. In such embodiments, the third barrier layer 110c is located between the first barrier layer 110a and the second barrier layer 110b. The first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 110a, the first barrier layer 100 Three barrier layers 110c and a second barrier layer 110b. In some embodiments, as a whole, the atomic percentage of one of the Group III elements of the composite barrier layer 110 of FIG. 3 increases as it moves away from the doped compound semiconductor layer 108, thereby providing a stress buffer between layers . For example, in some embodiments, the first barrier layer 110a is an AlGaN layer, the third barrier layer 110b is an _{AlxGa ( 1-x )} N layer (where 0 < x < 1), and the second barrier layer 110b is AlN layer in which the _x value of the AlxGa _{( 1-x )} N layer (0<x<1) increases in the direction away from the doped compound semiconductor layer 108, the Al concentration of the _{AlxGa ( 1-x )} N layer (percentage) higher than the AlGaN layer to provide a stress buffer. Furthermore, in some embodiments, the second barrier layer 110b (eg, an AlN layer or a layer with other group III elements) may more effectively interrupt the growth of magnesium or other p-type dopants, blocking the memory effect of magnesium or other dopants , in order to achieve better electrical performance. In some embodiments, the first barrier layer 110a, the second barrier layer 110b, and the third barrier layer 110c are each p-doped or undoped. In some embodiments, the doping concentration of the first barrier layer 110a may be about 5E17 cm ⁻³ to about 5E18 cm ⁻³ , eg, about 2E18 cm ⁻³ , and the doping concentration of the third barrier layer 110c may be about 5E16 cm ⁻³ The doping concentration of the second barrier layer 110b may be about 2E17 cm ⁻³ to about 2E18 cm ⁻³ , for example about 8E17 cm ⁻³ , from ³ to about 5E17 cm ⁻³ , for example, about 2E17 cm ⁻³ . In some embodiments, the atomic percentage of one of the Group III elements of the third barrier layer 110c is higher than the atomic percentage of this Group III element of the first barrier layer 110a.

4, in some embodiments, the composite barrier layer 110 includes a first barrier layer 110a and a third barrier layer 110c thereon. In some embodiments, metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, atomic layer deposition, other suitable methods, or a combination of the foregoing can be used to sequentially form A barrier layer 110a and a third barrier layer 110c. In some embodiments, the first barrier layer 110a may provide a stress buffer between the third barrier layer 110c and the doped compound semiconductor layer 108 . According to some embodiments, the first barrier layer 110a is an AlGaN layer and the third barrier layer 110c is an _{AlxGa ( 1-x )} N layer (where 0 < x < 1). In some embodiments, the composite barrier layer 110 is p-type doped or undoped. For example, the first barrier layer 110a may be p-type doped or undoped and the third barrier layer 110c may be p-type doped or undoped. In the embodiment in which the first barrier layer 110a is p-type doped, the doping concentration thereof is about 5E17 cm ⁻³ to about 5E18 cm ⁻³ , for example, about 2E18 cm ⁻³ . In the embodiment in which the third barrier layer 110c is p-doped, its doping concentration is about 5E16 cm ⁻³ to about 5E17 cm ⁻³ , for example, about 2E17 cm ⁻³ . The composite barrier layer of some embodiments of the present invention can better block the memory effect of the dopant and can better prevent the carrier from moving from the doped compound semiconductor layer to the adjacent layer compared to the barrier layer composed of a single layer or a single material components, resulting in leakage and carrier trapping.

FIG. 5 is a cross-sectional view of the semiconductor structure 20 according to another embodiment of the present invention. The semiconductor structure 20 is similar to the semiconductor structure 10 of FIG. 1 , and the semiconductor structure 20 further includes a capping layer 112 disposed on the composite barrier layer 110 . The capping layer 112 may include one or more layers of nitrides. In some embodiments, the capping layer 112 includes a p-type doped or undoped gallium nitride (GaN) layer, which can improve the surface morphology of the semiconductor structure 20 . For example, the GaN layer may be disposed on the top surface of the composite barrier layer 110 (eg, on the second barrier layer 110b or the third barrier layer 110c ), reducing the surface roughness of the semiconductor structure 20 to improve subsequent formation thereover layer stacking quality. In some embodiments, capping layer 112 includes a p-type doped or undoped silicon nitride (SiN) layer, which may be disposed on the top surface of composite barrier layer 110 (eg, second barrier layer 110b or on the third barrier layer 110 c ) to passivate the surface of the composite barrier layer 110 . According to some embodiments, the capping layer 112 includes a first nitride layer 112a and a second nitride layer 112b on the first nitride layer 112a. For example, the first nitride layer 112a includes GaN and the second nitride layer 112b includes SiN. In some embodiments, the cap layer 112 includes a p-type doped or undoped first nitride layer 112a and a p-type doped or undoped second nitride layer 112b on the first nitride layer 112a, such as shown in Figure 6. For example, the material of the first nitride layer 112a may include: GaN or other suitable materials; the material of the second nitride layer 112b may include: SiN or other suitable materials. In some embodiments, the thickness of the first nitride layer 112a is about 1 nm to 10 nm, and the thickness of the second nitride layer 112b is about 2 nm to 20 nm.

FIGS. 7-8 are cross-sectional views of the buffer layer 102 according to other embodiments of the present invention. In such embodiments, the buffer layer 102 includes at least one superlattice layer. 7, in some embodiments, the buffer layer 102 includes a first superlattice layer 102a and a second superlattice layer 102b, wherein the first superlattice layer 102a and the second superlattice layer 102b have different Period, the lattice difference between the substrate 100 and other film layers formed thereon can be further alleviated, so as to avoid defects such as bow or cracks due to lattice mismatch during the formation of these film layers. According to some embodiments, the buffer layer 102 includes a first superlattice layer 102a and a second superlattice layer 102b stacked in pairs, the first superlattice layer 102a having tensile stress and the second superlattice layer 102b having compressive stress stress. In some embodiments, the first superlattice layer 102 a and the second superlattice layer 102 b are stacked along a direction perpendicular to the main surface S of the substrate 100 . It should be noted that the number of superlattice layers shown in the figure is only an example, and the number of superlattice layers may be one or more than two depending on the material of the film layers above the substrate 100 and/or the process for forming these materials. . Referring to FIG. 8, in some embodiments, the buffer layer 102 further includes a resistance layer 102c disposed on the superlattice layer. In these embodiments, the resistance layer 102c acts as an electrical resistance layer, which can reduce leakage current. In some embodiments, the resistance layer 102c is a binary or ternary III-V compound. In some embodiments, the resistance layer 102c is a GaN layer doped with carbon or iron, and the doping concentration is about 6E18 cm ⁻³ to about 6E19 cm ⁻³ , eg, about 4E19 cm ⁻³ .

FIG. 9 is a cross-sectional view of the semiconductor structure 20 according to another embodiment of the present invention, wherein the substrate 100 includes a ceramic substrate 100 a and a pair of substrate barriers respectively disposed on the upper surface and the lower surface of the ceramic substrate 100 a Layer 100b. In some embodiments, the substrate barrier layer 100b on the upper and lower surfaces of the ceramic substrate 100a includes a single or multiple layers of insulating material and/or other suitable material layers, such as semiconductor layers. The insulating material layer may be oxide, nitride, oxynitride, or other suitable insulating material. The semiconductor layer may be polysilicon. The substrate barrier layer 100b may prevent diffusion between the ceramic substrate 100a and other components, and may also prevent the ceramic substrate 100a from interacting with other layers or process environments. In some embodiments, the substrate barrier layer 100b may also encapsulate the ceramic substrate 100a. In these embodiments, the base material barrier layer 100b not only covers the upper and lower surfaces of the 100a, but also covers the side surfaces of the 100a.

FIG. 10 is a cross-sectional view illustrating a semiconductor structure 30 according to other embodiments of the present invention. Semiconductor structure 30 includes: substrate 100 , nucleation layer 101 , buffer layer 102 , channel layer 104 , barrier layer 106 , doped compound semiconductor layer 108 , composite barrier layer 110 , gate features 118 and source/drain features 114 . The buffer layer 102 of the semiconductor structure 30 includes a first superlattice layer 102a, a second superlattice layer 102b and a resistance layer 102c. The composite barrier layer 110 of the semiconductor structure 30 includes a first barrier layer 110a and a third barrier layer 110c. It should be noted that, according to some embodiments of the present invention, the buffer layer 102 of the semiconductor structure 30 may also be two layers as shown in FIG. 7 or at least one layer described above; the composite barrier layer 110 of the semiconductor structure 30 may also be as The composite barrier layer shown in Figures 2 or 3. Gate features 118 are disposed on composite barrier layer 110 and source/drain features 114 are disposed on both sides of gate features 118 . The composite barrier layer 110 can achieve a growth interruption of the dopant of the doped compound semiconductor layer 108, prevent dopant diffusion into the gate feature 118 (eg, into the gate metal layer in the gate feature 118) or other features, To achieve zero or low dopant concentration surfaces in other components, it is beneficial to reduce leakage and carrier trapping, thereby avoiding gate delay and improving electrical performance. In some embodiments, source/drain features 114 extend through barrier layer 106 into channel layer 104 . In some embodiments, semiconductor structure 30 includes passivation layer 116 disposed on barrier layer 106 and source/drain features 114 . The material of the passivation layer 116 may include: SiO ₂ , SiON, Al ₂ O ₃ , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO) , other insulating materials, or a combination of the above. In some embodiments, the passivation layer 116 may be formed using metal organic vapor deposition, chemical vapor deposition, spin coating, other suitable methods, or a combination thereof. In some embodiments, the process of forming gate features 118 includes etching through passivation layer 116 to form openings over doped compound semiconductor layer 108 , filling the openings with layers of gate metal material and/or other materials , and remove excess material outside the opening. During the etching of the passivation layer 116, the composite barrier layer 110 can serve as an etch stop layer, and during the process of filling the material layer into the opening and other subsequent processes, the composite barrier layer 110 can protect the underlying doped compound semiconductor layer 108 and/or or barrier layer 106 .

In some embodiments, the nucleation layer 101 is disposed between the substrate 100 and the buffer layer 102 . The nucleation layer 101 can alleviate the lattice difference between the substrate 100 and the film layer grown above, so as to improve the crystal quality. The material of the nucleation layer may include: AlN, Al ₂ O ₃ , AlGaN, SiC, Al, a combination of the foregoing, or other materials. The nucleation layer 101 of single-layer or multi-layer structure can be formed by suitable processes, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, other processes, or a combination of the foregoing. In some embodiments, the material of the buffer layer 102 depends on the material of the nucleation layer 101 and the gas introduced in the epitaxial process.

The semiconductor structure provided by the embodiment of the present invention includes a composite barrier layer, which can prevent the memory effect of dopants in the doped compound semiconductor layer and prevent the carriers therein from moving to adjacent components, thereby avoiding leakage and carrier trapping. The composite barrier layer of the embodiment of the present invention can also be used as a protective layer and an etch stop layer. In some embodiments, the semiconductor structure further includes a capping layer disposed on the composite barrier layer, which can improve the stacking quality of the film layers above the capping layer.

The components of several embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present invention pertains can more easily understand the viewpoint of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should appreciate that they can, based on the embodiments of the present invention, design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can, without departing from the spirit and scope of the present invention, Make all kinds of changes, substitutions, and substitutions.

10, 20, 30: Semiconductor Structures 100: Substrate 100a: Ceramic substrate 100b: Substrate Barrier 101: Nucleation layer 102: Buffer layer 102a: Ceramic substrate 102b: Substrate Barrier 104: Channel Layer 106: Barrier layer 108: Doping compound semiconductor layer 110: Composite barrier 110a: first barrier layer 110b: Second barrier layer 110c: Third barrier layer 112: Cover layer 112a: first nitride layer 112b: second nitride layer 114: source/drain components 116: Passivation layer 118: Gate parts

Embodiments of the present invention are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily enlarged or reduced to clearly characterize the embodiments of the present invention. 1-4 are cross-sectional views illustrating semiconductor structures according to some embodiments of the present invention. 5-9 are cross-sectional views illustrating semiconductor structures according to other embodiments of the present invention. FIG. 10 is a cross-sectional view illustrating a semiconductor structure according to other embodiments of the present invention.

10: Semiconductor structure

100: Substrate

102: Buffer layer

104: Channel Layer

106: Barrier layer

108: Doping compound semiconductor layer

110: Composite barrier

Claims (10)

A semiconductor structure, comprising: a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; a doped compound semiconductor layer on the barrier and a composite barrier layer comprising a first barrier layer on the doped compound semiconductor layer and a second barrier layer on the first barrier layer, wherein the composite barrier layer and the barrier layer contain aluminum element , and the Al atomic percentage in the composite barrier layer increases with distance from the doped compound semiconductor layer. The semiconductor structure of claim 1, wherein the first barrier layer and the second barrier layer are p-type doped or undoped. The semiconductor structure of claim 1, wherein the composite barrier layer further comprises a third barrier layer located between the first barrier layer and the second barrier layer. The semiconductor structure of claim 1, wherein the first barrier layer comprises AlGaN, and the second barrier layer comprises AlN or _{AlxGa (1-x)} N, wherein 0<x<1. The semiconductor structure of claim 1, further comprising a cap layer on the composite barrier layer. The semiconductor structure of claim 5, wherein the cap layer includes a first nitride layer and a second nitride layer on the first nitride layer. The semiconductor structure of claim 6, wherein the first nitride layer comprises gallium nitride, and the second nitride layer comprises silicon nitride. The semiconductor structure of claim 6, wherein each of the first nitride layer or the second nitride layer is p-type doped or undoped. The semiconductor structure of claim 1, wherein the buffer layer comprises a first superlattice layer and a second superlattice layer stacked in pairs, the first superlattice layer has tensile stress and the second superlattice layer The lattice layer has compressive stress. The semiconductor structure of claim 1, further comprising: a gate part located on the composite barrier layer; and a source part and a drain part located on both sides of the gate part.

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