TWI768695B - Semiconductor apparatus - Google Patents

Abstract

The present disclosure relates to a storage unit in a semiconductor apparatus. The storage unit includes a stack structure, a block layer, a floating layer, a tunnel insulating layer, and a channel layer. The stack structure includes at least one control layer, at least one erase layer, and at least one insolated layer. The block layer is coplanar with the control layer. The floating layer is received in the block layer, and is insulated from the control layer by the block layer. The tunnel insulating layer covers sides of the block layer and the floating layer. The channel layer is disposed on a side of the tunnel insulating layer. The erase layer applies a specified layer for reducing resistance of the channel layer when the semiconductor apparatus executes an erase or written operation, and a conduction speed of the semiconductor apparatus is improved.

Description

semiconductor device

The present invention relates to a semiconductor device, in particular to a 3D flash memory device.

In the current semiconductor industry, three-dimensional (3D) flash memory can keep stored information for a long time without powering on, and has the advantages of high integration, fast storage speed, and easy erasing and rewriting. With the development of technology, it has become a trend that the size of 3D flash memory gradually becomes smaller. In the 3D flash memory structure, the cross-sectional area of the channel layer becomes smaller, and it is not easy to reduce the series resistance in the vertical direction by ion implantation, etc., thereby reducing the writing speed of the 3D flash memory during data writing operations. .

The main purpose of the present invention is to provide a semiconductor device, which aims to solve the problem of reduced read and write speeds in the prior art.

A semiconductor device includes a plurality of memory cells; each of the memory cells includes: a stacked structure including at least one control layer, at least two dielectric layers, and at least one erasing layer; a blocking layer, which is shared with the control layer The floating gate layer is arranged coplanar with the control layer and is insulated from the control layer by the barrier layer; a tunnel dielectric layer covers one side of the barrier layer and the floating gate layer ; a channel layer, located on one side of the tunnel dielectric layer; Wherein, the erasing layer applies a predetermined voltage when performing data reading and writing operations, so that the series resistance of the channel layer is reduced, so as to facilitate the rapid turn-on of the semiconductor device. When performing the data erasing operation, all A forward voltage is applied to the erasing layer, and electrons in the memory cells travel from the floating gate layer along the erasing path through the dielectric layer and all the dielectric layers in the overlapping portion of the erasing layer and the floating gate layer. The sidewall of the blocking layer flows into the erasing layer.

In the above-mentioned semiconductor device, when performing data read and write operations, a predetermined voltage is applied to the erase gate to reduce the series resistance of the channel layer, so as to facilitate the rapid turn-on of the semiconductor device and improve the semiconductor performance. The read and write speed of the device.

1: Semiconductor device

10: Storage unit

ST: Layered structure

11: Dielectric layer

12: Insulation layer

13: Control layer

112: Erase Layer

14: Barrier

15: Floating gate layer

16: Tunnel Dielectric Layer

17: Channel layer

18: Fill Layer

D1: first thickness layer

D2: first thickness layer

path-A: write path

path-B: Erase path

FIG. 1 is a schematic vertical cross-sectional view of the semiconductor device of the present invention along the X direction.

FIG. 2 is a schematic horizontal cross-sectional view of the semiconductor device of the present invention along the X direction.

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The terms "first", "second" and "third" in the description of the present invention and the above-mentioned drawings are used to distinguish different items, rather than to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or modules is not limited to the listed steps or modules, Rather, it optionally includes steps or modules not listed, or optionally includes other steps or modules inherent to the process, method, product, or device.

Specific embodiments of the semiconductor device of the present invention will be described below with reference to the accompanying drawings.

Please refer to FIG. 1 and FIG. 2 , the present invention provides a vertical cross-sectional schematic diagram of a semiconductor device 1 along the X direction and a horizontal cross-sectional schematic diagram along the X direction. The semiconductor device 1 is a stacked structure, which is composed of several memory cells 10 . FIG. 1 only shows a vertical cross-sectional schematic diagram of one memory cell 10 along the X direction. FIG. 2 is a horizontal cross-sectional schematic diagram of two adjacently disposed memory cells 10 along the X direction. In at least one embodiment of the present invention, the semiconductor device 1 may be a three-dimensional flash memory. Each of the storage units 10 can perform data writing operations and data erasing operations.

Each of the memory cells 10 includes a stacked structure ST, an insulating layer 12 , a floating gate layer 15 , a barrier layer 14 , a tunnel dielectric layer 16 , a channel layer 17 and a filling layer 18 .

The stacked structure ST includes at least one control layer 13 , at least one erase layer 112 and at least one dielectric layer 11 . In at least one embodiment of the present invention (as shown in FIG. 2 ), the stacked structure ST includes two control layers 13 , three erase layers 112 and one dielectric layer 11 . The control layer 13 is sandwiched between the adjacent dielectric layer 11 and the barrier layer 14 . The erase layer 112 and the control layer 13 are isolated by the dielectric layer 11 . The erase layer 112 and the floating gate layer 15 are isolated by the dielectric layer 11 and the blocking layer 14 . In at least one embodiment of the present invention, the dielectric layer 11 is made of an insulating material; the erasing layer 112 is made of a low-resistance conductive material, such as metal, silicide, and the like.

In at least one embodiment of the present invention, the barrier layer 14 , the tunnel dielectric layer 16 , the channel layer 17 and the filling layer 18 in the control layer 13 are substantially annular structures (as shown in FIG. 1 ) shown). The channel layer 17 is disposed outside the filling layer 18 , and the tunnel dielectric layer 16 is disposed outside the channel layer 17 .

The floating gate layer 15 is accommodated in the barrier layer 14 . In the second direction Y, the floating gate layer 15 and the control layer 13 are coplanar. The floating gate layer 15 has a semi-ring structure (as shown in FIG. 1 ). In the first direction X, the floating gate layer 15 and the erasing layer 112 are partially overlapped. In at least one embodiment of the present invention, the floating gate layer 15 is made of silicide or other materials with better electrical conductivity. The floating gate layer 15 is used for storing data.

In the second direction Y, the dielectric material between the erasing layer 112 and the channel layer 17 has a first thickness layer D1; in the first direction X, in the erasing layer The dielectric material between the layer 112 and the floating gate layer 15 has a second thickness layer D2; the breakdown voltage of the first thickness layer D1 is greater than that of the second thickness layer D2 (as shown in FIG. 2 ) ).

The insulating layer 12 insulates and isolates the adjacent barrier layers 14 in the second direction Y, and insulates the tunnel dielectric layer 16 from the adjacent memory cells 10 in the third direction Z. The tunnel dielectric layer 16 is insulated and isolated (as shown in FIG. 1 ). In at least one embodiment of the present invention, the insulating layer 12 is made of silicon oxide material.

The memory cell 10 applies a corresponding voltage on the control layer 13 when the data writing operation is performed, so that electrons enter through the channel layer 17 through the tunnel dielectric layer 16 along the writing path path-A. The floating gate layer 15 is formed, thereby realizing data storage (as shown in FIG. 2 ). At the same time, a predetermined voltage is applied on the erasing layer 112 to reduce the series resistance of the channel layer 17 , so as to facilitate the rapid turn-on of the semiconductor device 1 , thereby improving the data read and write speed. In at least one embodiment of the present invention, the predetermined voltage is in the range of 3-8 volts. In other embodiments, the predetermined voltage can also be adjusted according to the performance of the semiconductor device 1, and can be other voltage ranges and values.

When the memory cell 10 performs a data erasing operation, a forward voltage is applied to the erasing layer 112 , the floating gate layer 15 is floating, and a voltage smaller than the forward voltage is applied to the control layer 13 . voltage to prevent breakdown between the erase layer 112 and the control layer 13 . At the same time, in A ground voltage or a negative voltage is provided on the channel layer 17 , so that electrons pass from the floating gate layer 15 along the erasing path path-B through the dielectric at the overlapping portion of the erasing layer 112 and the floating gate layer 15 . The sidewalls of the electrical layer 11 and the barrier layer 14 flow into the erase layer 112 instead of the tunnel dielectric layer 16 (as shown in FIG. 2 ). In at least one embodiment of the present invention, the forward voltage is 10-15 volts. In other embodiments, the forward voltage may also be other values.

In the above-mentioned semiconductor device 1, when performing data reading and writing operations, a predetermined voltage is applied to the erase gate 112 to reduce the series resistance of the channel layer 17, so as to facilitate the rapid turn-on of the semiconductor device 1 , to improve the read and write speed of the semiconductor device 1 .

It should be noted that, for the sake of simple description, the foregoing method embodiments are all expressed as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence. As in accordance with the present invention, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

It should also be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements , but also other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: The technical solutions described in each embodiment are modified Modifications, or equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

To sum up, the present invention complies with the requirements of an invention patent, and a patent application can be filed in accordance with the law. However, the above descriptions are only the preferred embodiments of the present invention, and for those who are familiar with the techniques of this case, equivalent modifications or changes made in accordance with the creative spirit of this case should be included within the scope of the following patent application.

1: Semiconductor device

10: Storage unit

ST: Layered structure

11: Dielectric layer

13: Control layer

112: Erase Layer

14: Barrier

15: Floating gate layer

16: Tunnel Dielectric Layer

17: Channel layer

18: Fill Layer

D1: first thickness layer

D2: first thickness layer

path-A: write path

path-B: Erase path

Claims (2)

A semiconductor device includes a plurality of memory cells; each of the memory cells includes: a stacked structure including at least one control layer, at least one erase layer and at least one dielectric layer; and a barrier layer coplanar with the control layer a floating gate layer, accommodated in the barrier layer, and insulated from the control layer by the barrier layer; a tunnel dielectric layer, covering one side of the barrier layer and the floating gate layer; a channel layer, located on one side of the tunnel dielectric layer; wherein, the erasing layer applies a predetermined voltage when performing data read and write operations, so that the series resistance of the channel layer is reduced, which is beneficial to the semiconductor device The fast turn-on of the memory cell, when performing the data erasing operation, a forward voltage is applied to the erasing layer, and the electrons in the memory cell follow the erasing path from the floating gate layer through the erasing layer and the Sidewalls of the dielectric layer and the blocking layer at the overlapping portion of the floating gate layer flow into the erasing layer. The semiconductor device of claim 1, wherein, in a direction parallel to the surface of the stacked structure, the dielectric material between the erasing layer and the channel layer has a first thickness layer; In the vertical direction of the stacked structure, the dielectric material between the erasing layer and the floating gate layer has a second thickness layer; the breakdown voltage of the first thickness layer is greater than the breakdown voltage of the second thickness layer .

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