TWI768316B - Memory apparatus and memory management method for safe power-up - Google Patents

Abstract

A memory apparatus and a memory management method for safe power-up are provided. The memory management method includes: dividing a memory cell array into a first block and a second block ; storing a boot code in the first block and storing a backup boot code in the second block by backing up the boot code; in a power up sequence, setting a fail-safe flag , and reading the boot code from the first block to obtain a fist read-out boot code according to a reset command; judging whether the first read-out boot code is normal or not to generate a judging result, and setting a prequalify flag according to the judging result or the fail-safe flag, and determining whether to read the backup boot code to obtain a second read-out boot code or not.

Description

Memory device and memory management method for safe booting

The present invention relates to a memory device and a memory management method for safe booting, and more particularly, to a memory device that can improve the success rate of booting and a memory management method for safe booting.

In today's electronic devices, the host-side boot codes are often stored in non-volatile memory, such as flash memory. The boot code stored in the flash memory is often damaged due to various reasons. Once the content of the boot code is damaged, the host will boot correctly without the code and cannot operate normally. Moreover, in the prior art, when the host end fails to boot and crashes, the system can only be sent back to the supplier end for maintenance, which is extremely inconvenient in use.

The present invention provides a memory device and a memory management method for safe booting, which can improve the probability of successful booting of the host.

The memory management method for safe booting of the present invention includes: in the memory cell Distinguish the first block and the second block in the array; make the boot code stored in the first block, and back up the boot code to store the backup boot code in the second block; in the boot process, set the fail-safe flag mark, and read the boot code in the first block according to the command of the host-side programmable software to obtain the first read boot code; determine whether the first read boot code is correct to generate a judgment result, and, according to the judgment result or Fail-safe flag to set the pre-check flag, and according to the pre-check flag to decide whether to read the backup boot code as the second read boot code.

The memory device of the present invention includes a memory cell array and a control circuit. The memory cell array has a first block and a second block, and the first block and the second block store the boot code and the backup boot code respectively. The control circuit is coupled between the memory cell array and the host, and is used for executing the above-mentioned management method for safe booting.

Based on the above, the present invention stores the boot code and the backup boot code respectively through the first block and the second block in the memory cell array. In the boot process, the pre-check flag is set according to the fail-safe flag or the judgment result of whether the first read-out boot code is correct, and according to the pre-check flag, it is determined whether to read the backup boot code to execute the booting action on the host side . It can maintain the normal operation of the host.

S110~S150, S310~S3130, S410~S4120: Memory management steps

200: Memory Cell Array

501: Memory device

510: Memory Cell Array

520: Control circuit

521: address decoder

522: Logic Circuits

ADD1~ADD3: address

BA-DEF: Boot address setting value

BC1: boot code

BC2: Backup boot code

BC-DEF: Boot code setting value

FF1: Flip-flop

HLSB: low byte address

HMSB: Highest bit address

MMSAD: toggle address

PREQ: Prequalification Flag

PUT: Power-on trigger signal

XOR: Mutually exclusive OR gate

Z1: The first block

Z2: Second block

FIG. 1 is a flowchart of a memory management method for secure booting according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating a configuration of a memory cell array according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating a memory management method according to another embodiment of the present invention.

FIG. 4 is a flowchart illustrating a memory management method for secure booting according to another embodiment of the present invention.

5A and 5B are schematic diagrams of different implementations of a memory device according to an embodiment of the present invention, respectively.

Please refer to FIG. 1 . FIG. 1 is a flowchart illustrating a memory management method for secure booting according to an embodiment of the present invention. Wherein, in step S110, the memory cell array in the memory can distinguish the first block and the second block. The first block and the second block may be two different blocks with consecutive or non-consecutive addresses in the memory cell array. In the embodiment of the present invention, the first block may be disposed in the memory cell array with a relatively low address range, and the second block may be disposed in the memory cell array with a relatively high address range. In this embodiment, the memory may be a non-volatile memory, such as a flash memory.

Next, in step S120, the boot code is stored in the first block, and the boot code is backed up to store the backup boot code in the second block. The boot code is used to provide the host to read, and to provide the host to execute the booting action.

In step S130, the boot process is entered, and in the boot process, a fail-safe flag is set, and the boot code in the first block is read according to the reset command to obtain the first read boot code. Among them, a fail-safe flag can be set in the flash memory. And, in step S130, a fail-safe flag can be set as the first logic level (eg logic level 1). Then, the host side can execute a reset command through the host-side programmable software, and based on the trigger of the reset command, the host side can read the boot code of the first block in the memory cell array, and thereby read out First read the boot code.

Here, when the read operation of the boot code of the first block of the memory is performed, the access address can be set as the first start access address, and the first start access address of the memory cell array can be set A read action is performed to obtain the first read-out boot code.

Next, in step S140, it can be judged whether the first read-out boot code is correct, and a judgment result can be generated thereby. In this embodiment, the judgment result can be obtained by performing a cyclic redundancy check (CRC) on the first readout code. Or, in other embodiments of the present invention, after the host side performs the booting action according to the first read-out code, the judgment result can be obtained by performing a specific function check, and the first area in the memory cell array can be known by this. Check whether the boot code stored in the block is correct.

Incidentally, when the judgment result obtained in step S140 indicates that the first read boot code is correct, the fail-safe flag can be cleared to the second logic level (eg, logic level 0). If the judgment result obtained in step S140 indicates that the first read-out code is wrong, the fail-safe flag can be maintained at the first logic level (eg, logic level 1).

In step S150, a pre-trial flag may be set according to the judgment result or the fail-safe flag. The pre-qualification flag is a volatile memory flag configured in the memory. Also, during the boot process, when the fail-safe flag is set (etc. In the state of the first logic level), or under the condition that the judgment result of step S140 indicates that the first read boot code is wrong, the pre-trial flag may be set equal to the first logic level. In addition, when the pre-check flag is equal to the first logic level, the host can read the backup boot code of the second block in the memory cell array, and thereby obtain the second read boot code. The host can perform restarting according to the second read-out code.

On the other hand, in the above-mentioned step S150, when the read operation is to be performed on the backup boot code of the second block of the memory cell array, the host side can, according to the pre-check flag equal to the first logic level, Under the condition of changing the initial access address, a read operation is performed on the memory cell array to obtain a second read boot code.

It is not difficult to know from the above description that in the memory management method for safe booting according to the embodiment of the present invention, when the boot code stored in the memory cell array is wrong, the memory cell array can provide a backup copy stored in the second block The boot code is backed up, and the host side is successfully booted by backing up the boot code, which effectively increases the probability of the host side successfully booting.

Please refer to FIG. 2 , which is a schematic diagram illustrating a configuration of a memory cell array according to an embodiment of the present invention. In FIG. 2, the memory cell array 200 can be divided into a first block Z1 and a second block Z2. In this embodiment, the first block Z1 is disposed between the address ADD1 and the address ADD2, and the second block Z2 is disposed between the address ADD2 and the address ADD3. In addition, the boot code BC1 is stored in the first block Z1, and the backup boot code BC2 is stored in the second block Z2. When the boot code BC1 in the first block Z1 is to be read, the address ADD1 as the starting address can be set as the access address, and the boot code BC1 is read. On the contrary, when the pre-trial flag is enabled, it is necessary to read the backup code BC2 in the second block Z2. During operation, the host side maintains the original starting address address (ADD1) as the access address, and performs the read operation of the backup boot code BC2.

Here, the memory capacity of the first block Z1 and the second block Z2 is larger than the size of the boot code BC1 and the backup boot code BC2. In addition, the address configuration of the first block Z1 and the second block Z2 may be continuous, but may also be discontinuous, and there is no certain limitation.

Please refer to FIG. 3 , which is a flowchart illustrating a memory management method according to another embodiment of the present invention. In FIG. 3, step S310 starts the booting procedure. Step S320 judges whether the failure-safety flag has been set. In the state where the fail-safety flag has been set, step S3100 is executed. On the contrary, in the state when the failure-safety flag is not set Next, step S330 is executed. Here, step S320 may be determined according to the logic level of the fail-safe flag. For example, when the fail-safe flag is at the first logic level, the fail-safe flag can be viewed as a set state. On the contrary, when the fail-safety flag is at the second logic level, the fail-safety flag can be regarded as a non-set state. The first logic level and the second logic level are complementary.

It is worth noting that when it is determined in step S320 that the fail-safety flag has been set, it means that the condition for fail-safe booting exists, and the fail-safe booting mechanism needs to be activated. In this case, it means that the previous power-on (reading the power-on code BC1) failed, and the fail-safe flag was not cleared. Next, step S3100 is executed to set the pre-trial flag to enable.

Incidentally, the fail-safe flag can be set in non-volatile memory (such as flash memory), so through a reboot action on the host side, and Does not change the logical level of the fail-safe flag. Additionally, in an embodiment of the present invention, the fail-safe flag may be stored in the same flash memory as the boot code is stored. In other embodiments of the present invention, the fail-safe flag and the boot code may also be stored in different flash memories.

In step S330, the setting fails - the security flag is the first logic level, then in step S340, the host can send a reset memory command, and in step S350, the boot code of the first block in the memory cell array is downloaded . Next, in step S360, a function check or a CRC check is performed on the read out first readout code, so as to confirm whether the first readout code is correct. Wherein, when the check result of step S360 is passed, it means that the first read-out code is correct, and step S370 can be executed. On the contrary, when the check result of step S360 is not passed, it means that the first read-out code is wrong and step S390 is executed accordingly.

In step S370 , based on the correctness of the first read boot code, the fail-safe flag can be cleared to the second logic level to indicate that the execution fail-safe boot condition does not exist. And in step S380, the host can perform normal actions.

On the other hand, in step S390, the host side executes the reset command again or starts a hardware reset (Hardware Reset) action. Next, through step S3100, the pre-check flag is set as enabled in the memory. Here, the action of setting the pre-check flag to enable can be accomplished by setting the pre-check flag to a high logic level. Correspondingly, when the pre-check flag is at the second logic level, the pre-check flag can be viewed as disabled. .

In step S3110, download the backup boot code in the second block of the memory according to the pre-qualification flag set as enabled, and thereby obtain the second read boot code code. Next, step S3120 performs a function check or a CRC check for the second readout code. If the second read-out power-on check in step S3120 is passed, step S3130 is executed. On the contrary, if the second readout power-on check operation in step S3120 fails, an error reporting operation is performed (step S3140 ).

In step S3130, the host side can perform the clearing operation of the fail-safe flag (cleared to the second logic level), and can perform the repairing operation of the boot code of the first block in the memory. It is worth mentioning that, regarding the details of the recovery action of the boot code, the first block in the memory can be erased first. Then, it is completed by writing the backup boot code (ie, the second read boot code) in the second block back to the first block of the memory.

Note here that in this embodiment, the fail-safe flag is set in memory. Therefore, the memory management process of FIG. 3 can be accomplished through the memory and the corresponding control circuit.

Please refer to FIG. 4 below. FIG. 4 is a flowchart illustrating a memory management method for safe booting according to another embodiment of the present invention. Different from the previous embodiment, the embodiment of FIG. 4 sets the logic of the forced exchange flag (equivalent to the fail-safe flag in the previous embodiment) through the user (external electronic device) outside the memory and its controller. level.

In terms of action details, a boot procedure is started in step S410. Next, in step S430, the boot code can be downloaded from the first block of the memory, and the first read boot code is obtained.

In step S440, a CRC or function check is performed on the first read-out boot code, so as to judge whether the first read-out boot code is correct or not. If the decision in step S440 If the disconnection result indicates that the first read-out boot code is correct, in step S450, the forced exchange flag can be disabled in advance, and a normal action is performed (step S460). On the contrary, if the judgment result of step S440 indicates that the first read boot code is wrong, the system can set an external signal connected to the memory (forced switch pin) (step S445) to a high logic level, and A restarting action of a warm reboot is performed, and at the same time, the memory sets the pre-check flag as an action of enabling (step S470 ). After the waiting for the warm-up action in step S480 ends, the action of downloading the backup boot code of the second block in the memory is performed in step S490.

Please note that in this embodiment, the logic level of the forced exchange flag can be set by an external electronic device. Under the condition that the forced swap flag is enabled and the forced swap flag is at the first logic level, step S490 may execute the action of downloading the backup boot code of the second block in the memory, thereby obtaining the second Read the boot code.

Next, in step S4100, a function check or CRC check is performed on the second readout code, and step S4120 is performed when the check passes, or step S4110 is performed when the check fails to report an error.

In step S4120, a repair action of the boot code of the first block in the memory can be performed, and the forced swap flag can be cleared (cleared to a second logic level) after the boot code of the first block is repaired.

Please refer to FIGS. 5A and 5B below. FIGS. 5A and 5B are schematic diagrams of different implementations of the memory device according to the embodiment of the present invention, respectively. In FIG. 5A , the memory device 501 includes a memory cell array 510 and a control circuit 520 . memory The cell array 510 is divided into a first block and a second block, and stores the boot code BC1 and the backup boot code BC2 respectively.

The control circuit 520 can be used to execute the memory management process of the foregoing embodiments, so as to increase the probability of the host side successfully booting.

On the other hand, the control circuit 520 includes a flip-flop FF1 , a logic circuit 522 and an address decoder 521 . The data terminal of the flip-flop FF1 receives the boot address setting value BA-DEF, the clock terminal of the flip-flop FF1 receives the power-on trigger signal PUT, and the output terminal of the flip-flop FF1 is based on the power-on trigger signal PUT generated by the restart action. The boot address setting value BA-DEF is generated.

On the other hand, the logic circuit 522 can be used as a glue logic circuit between the host side and the memory cell array 510 . The logic circuit 522 receives the boot code setting value BC-DEF, the most significant bit address HMSB and the output of the flip-flop FF1, and performs a logic operation to generate the switching address MMSAD. In addition, the address decoder 521 receives the lower-order address HLSB and the switching address MMSAD, and performs an address decoding operation to generate an access address according to the lower-order address HLSB and the switching address MMSAD. And according to the access address, the boot code BC1 or the backup boot code BC2 in the memory cell array 510 is read.

In operation details, when the boot code setting value BC-DEF is disabled, the address decoder 521 can only provide an access address to read the boot code BC1 of the first block of the memory cell array 510 . When the boot code setting value BC-DEF is enabled, the logic circuit 522 can generate the switch address MMSAD according to the most significant bit address HMSB and the output of the flip-flop FF1.

To further illustrate, under this condition, when the output of the flip-flop FF1 is, for example, a logic level of 0, the logic circuit 522 can output the high-order bit address HMSB as the switching address MMSAD. The address decoder 521 generates the access address according to the switching address MMSAD and the low-order byte address HLSB. The switching address MMSAD can be a single bit, which can be accessed as the highest bit of the address and used for integration with the lower bit address HLSB. Under the condition that the low-order bit address HLSB is 0 and the switching address MMSAD is also 0, the address decoder 521 can generate an access address equal to 000000h (hexadecimal value) to read the boot code BC1.

When the output of the flip-flop FF1 is, for example, a logic level of 1, the logic circuit 522 can reverse the switching address MMSAD and make the switching address MMSAD a logic level of 1. The address decoder 521 can generate an access address equal to 800000h (hexadecimal value) to read the backup boot code BC2.

Please note here that the output of the flip-flop FF1 can be generated according to the boot address setting value BA-DEF, and when the boot address setting value BA-DEF is changed, the flip-flop FF1 needs to be restarted after the restart. The generated output can be changed according to the power-on trigger signal PUT.

Next, please refer to FIG. 5B , which is different from the embodiment of FIG. 5A , the control circuit 520 in the memory device 502 of FIG. 5B further includes an exclusive or gate XOR. The exclusive OR gate XOR is coupled between the output terminal of the flip-flop FF1 and the logic circuit 522 . The mutual exclusion or gate XOR receives the pre-trial flag PREQ and the output of the flip-flop FF1. When the pre-review flag PREQ is enabled, the output of the flip-flop FF1 can be reversed (or not) according to the pre-review flag PREQ, thereby changing the toggle bit generated by the logic circuit 522 address MMSAD, and choose to read the power-on code BC1 or backup the power-on code BC2.

Here, the pre-qualification flag PREQ may be provided by a random access memory. That is to say, the external electronic device can change the pre-qualification flag PREQ by writing data to the random access memory, and perform the switching action of reading the boot code BC1 or the backup boot code BC2 accordingly.

To sum up, the present invention stores the boot codes and backup boot codes respectively in different blocks in the memory cell array. And when the boot code is judged to be in an error state, it switches to read the backup boot code to execute the boot action. In this way, the host can be guaranteed to boot successfully and maintain the normal operation of the system.

S110~S150: Memory management steps

Claims (10)

A memory management method for safe booting, comprising: distinguishing a first block and a second block in a memory cell array; storing a boot code in the first block, and backing up the boot code for The second block stores a backup boot code; in a boot process, it is determined whether a fail-safe flag has been set to generate a first determination result; when the first determination result indicates that the fail-safe flag has been set After being set, set a pre-check flag; when the first judgment result indicates that the failure-safety flag is not set, set the fail-safety flag, and read the failure-safety flag according to a host-side programmable software command the boot code in the first block to obtain a first read boot code; determine whether the first read boot code is correct to generate a second judgment result; set the pre-check flag according to the second judgment result; and determining whether to read the backup boot code as a second read boot code according to the pre-trial flag. The memory management method of claim 1, wherein when the second judgment result indicates that the first read boot code is correct, the method further comprises clearing the fail-safe flag. The memory management method of claim 1, wherein when the second judgment result indicates that the first read boot code is wrong, the pre-check flag is set. The memory management method as described in item 3 of the claimed scope further comprises reading the backup boot code as the second read boot code according to the pre-examination flag. The memory management method of claim 1, wherein the step of judging whether the first read boot code is correct to generate the second judgment result comprises: performing a cyclic redundancy check on the first read boot code to obtain the second judgment result; or perform a power-on action on a host according to the first read-out code, and make the host perform a function check to obtain the second judgment result. The memory management method as described in item 1 of the scope of the application, further comprising: performing a cyclic redundancy check on the second boot code, or performing a boot action on a host according to the second read boot code, and making The host performs a function check to verify whether the second read-out code is correct; and clears the fail-safe flag when the second read-out code is verified to be correct. The memory management method as described in item 6 of the claimed scope further comprises: performing a repairing action on the boot code in the first block. The memory management method of claim 7, wherein the repairing action comprises: performing an erase action on the first block; and copying the second read-out boot code for writing to the first block . The memory management method of claim 1, wherein the first block and the second block correspond to a first starting access address and a second starting access address, respectively, wherein the read The step of obtaining the boot code in the first block to obtain the first read boot code includes: setting an access address as the first initial access address, and the memory cell according to the access address The array performs a read operation to obtain the first read-out boot code, wherein the step of determining whether to read the backup boot code as the second read-out boot code according to the pre-check flag includes: according to the pre-check flag and the starting the access address, and performing a read operation on the memory cell array to obtain the second read-out boot code. A memory device, comprising: a memory cell array with a first block and a second block, the first block and the second block respectively store a boot code and a backup boot code; a control circuit , which is coupled between the memory cell array and a host, and is used for executing: in a boot-up procedure, judging whether a failure-safety flag has been set to generate a first judgment result; when the first judgment result indicates After the fail-safe flag has been set, set a pre-trial flag; when the first judgment result indicates that the fail-safe flag is not set, set the fail-safe flag, and according to a host-side availability program software commands to read the boot code in the first block to obtain a first read boot code; Judging whether the first read-out boot code is correct to generate a second judgment result; setting the pre-qualification flag according to the second judgment result; and determining whether to read the backup power-up code as a second according to the pre-qualification flag Read the boot code.

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