TWI765642B - Inter-chip SPI communication method, circuit device and information processing device for cascaded chip circuits - Google Patents

Abstract

The invention mainly discloses a cross-chip SPI communication method for cascading chip circuits, which is used for a first SPI communication between a host computer chip and a subordinate computer main chip, or with a subordinate computer slave cascading the subordinate computer main chip. The chip performs a second SPI communication, which is called cross-chip SPI communication. According to the method of the present invention, after the upper computer chip transmits a cross-chip communication enable command to the lower computer main chip through a first SPI communication line, the lower computer main chip couples the first SPI communication line to a first SPI communication line. Two SPI communication lines enable the upper computer chip to perform write operation or read operation on the lower computer slave chip through SPI communication. In addition, the present invention improves the speed of the read operation by arranging the latch circuit in the main chip of the lower computer.

Description

Inter-chip SPI communication method, circuit device and information processing device for cascaded chip circuits

The present invention relates to the technical field of chip read/write control, and more particularly to a cross-chip SPI communication method for cascading chip circuits, which is used to enable a host chip to cross the host chip of a host computer to communicate with the host chip of the host computer at the level of the host chip of the host computer. The connected subordinate computer performs read/write operations from the wafer.

FIG. 1 shows a block diagram of a conventional upper computer chip and a lower computer chip. It should be known that the host computer chip 1a refers to a circuit chip that issues a control command, such as a CPU or an application processor (Application Processor, AP). On the contrary, the lower computer chip 2a is a circuit chip that performs a specific work according to the control command of the upper computer chip 1a, such as a display driving chip, a touch control chip, and the like. As shown in FIG. 1, the upper computer chip 1a has a first SPI unit 11a, and the lower computer chip 2a has a second SPI unit 21a, which is coupled to the first SPI unit 11a according to the SPI bus protocol, so as to receive An SPI signal transmitted from the first SPI unit 11a.

Practical experience shows that, in some applications, a single subordinate computer chip 2a cannot efficiently complete the specific work. For example, the lower computer chip 2a is a touch chip, and it is difficult for a single touch chip to efficiently complete the touch detection for a large-sized touch panel. In this case, a cascaded chip circuit including a master chip and a slave chip of a lower computer is designed to complete the touch detection work for a large-sized touch panel.

FIG. 2 shows a block diagram of a conventional upper computer chip, a lower computer master chip, and a lower computer slave chip. As shown in FIG. 2 , a first SPI unit 11b of a host computer chip 1b is coupled to a second SPI unit 21b of the host computer chip 2b, and the host computer chip 2b is coupled with a third SPI unit 22b of the host computer chip 2b A fourth SPI unit 31b of the slave chip 3b is coupled to it. The prior art usually adopts the following two steps to make the host computer chip 1b complete a write operation to the slave chip 3b of the slave computer: (1a) the host computer chip 1b transmits a first SPI signal to the slave computer according to the SPI communication protocol The main chip 2b makes the lower computer main chip 2b contain a MOSI signal contained in the first SPI signal The data stored in a storage unit 20b; and (2a) the lower host chip 2b reads the data stored in the storage unit 20b, and then uses the third SPI unit 22b to send the data to a second SPI signal The form is transmitted to the fourth SPI unit 31b of the slave chip 3b of the lower computer.

As mentioned above, in order to write data to the slave chip 3b of the lower computer, the chip 1b of the upper computer must first write the data to the master chip 2b of the lower computer, and then the master chip 2b of the lower computer writes the data to the lower computer from wafer 3b. Therefore, it can be easily learned that the conventional SPI communication method for enabling the upper computer chip 1b to complete the write operation to the lower computer slave chip 3b has two major drawbacks: time-consuming and troublesome operation. It must be known that the master chip 2b of the lower-level computer must have the relevant program code, so that it can write data to the slave chip 3b of the lower-level computer through SPI communication. In other words, the developer must complete the design of the dedicated program code, and write the designed dedicated program code into the lower-level computer master chip 2b, so that the lower-level computer master chip 2b can write data into the lower-level computer slave chip 3b through SPI communication .

To further illustrate, the conventional technology usually adopts the following four steps to make the upper computer chip 1b complete a read operation for the lower computer slave chip 3b: (1b) The upper computer chip 1b sends a first read request to the The master chip 2b of the lower computer; (2b) The master chip 2b of the lower computer transmits a second read request to the slave chip 3b of the lower computer; (3b) The master chip 2b of the lower computer transmits a first read operation according to the SPI communication protocol signal (including CS signal and CLK signal) to the slave chip 3b, so that the slave chip 3b uploads a first MISO signal to the slave chip 3b according to the SPI communication protocol; and (4b) on the slave chip 3b After the master chip 2b stores the data of the MISO signal in its storage unit 20b, the host chip 1b transmits a second read operation signal to the slave master chip 2b according to the SPI communication protocol, so that the slave master chip 2b Upload the second MISO signal to the host computer chip 1b according to the SPI communication protocol.

As mentioned above, in order to read data from the slave chip 3b from the lower computer, the upper computer chip 1b must first make the master chip 2b of the lower computer read data from the slave chip 3b from the lower computer, and then continue to read the data from the lower computer master chip 2b. The wafer 2b reads out data. Therefore, the prior art is used to make the host computer chip 1b complete the The SPI communication method of the read operation of the lower computer from the chip 3b also has two main defects, which are time-consuming and troublesome to operate.

It can be seen from the above description that there is an urgent need in the art for a novel cross-chip SPI communication method.

The main purpose of the present invention is to provide a cross-chip SPI communication method for cascading chip circuits, which is used for a first SPI communication between an upper computer chip and a lower computer main chip, or a second SPI communication method for cascading the lower computer main chip. The bit computer performs a second SPI communication from the chip, which is called cross-chip SPI communication. According to the method of the present invention, after the upper computer chip transmits a cross-chip communication enable command to the lower computer main chip through a first SPI communication line, the lower computer main chip couples the first SPI communication line to a first SPI communication line. Two SPI communication lines, so that the upper computer chip can perform a cross-chip SPI write operation or a cross-chip SPI read operation on the slave chip of the lower computer. In addition, the present invention also improves the speed of the cross-chip SPI read operation by arranging a latch circuit in the host chip of the lower computer.

In order to achieve the above object, the present invention proposes an embodiment of the cross-chip SPI communication method of the cascaded chip circuit, which includes the following steps: a host computer chip transmits a cross-chip communication enable command to a subordinate computer through a first SPI communication line a host chip; the lower host chip executes a first switching operation according to the inter-chip communication enabling command to electrically connect the first SPI communication line with a second SPI communication line, so that the host chip can pass through the first SPI communication line An SPI communication line connected by an SPI communication line and the second SPI communication line directly performs an SPI communication with the subordinate computer slave chip; and the upper computer chip performs one or more cross-chip SPI communication, thereby crossing the The master chip of the lower computer performs the SPI communication with the slave chip of the lower computer, so as to realize a write operation or a read operation for the slave chip of the lower computer.

In one embodiment, the cross-chip SPI communication method of the cascaded chip circuit of the present invention further includes the following step: the host computer chip transmits a cross-chip communication stop command to the lower-level computer main chip through the first SPI communication line ;as well as The slave host chip performs a second switching operation according to the inter-chip communication stop command to disconnect the first SPI communication line from the second SPI communication line.

In one embodiment, the upper computer chip has a first SPI unit, and the lower computer main chip has a second SPI unit that uses the first SPI communication line and the first SPI unit to perform an SPI communication.

In one embodiment, the slave chip of the slave computer further has a third SPI unit and a switching unit, and the slave chip of the slave computer has a fourth SPI communication line and the switching unit to perform the SPI communication. SPI unit.

In one embodiment, the switching unit performs the first switching operation or the second switching operation according to the control of a switching signal.

In an embodiment, the host chip of the lower computer has a latch circuit for latching the data sent by the slave chip of the lower computer to perform a latching process, so as to satisfy the requirements of the upper computer chip for the data transmission by a water pipe. The timing specification of the read operation of the slave chip by the slave.

In one embodiment, the host computer chip discards the data of the read first tuple when the read operation is performed.

In one embodiment, when the upper computer chip is performing the read operation, the lower computer slave chip will start to transmit data in advance within the corresponding period of the first tuple.

In a feasible embodiment, the host chip of the lower computer and the slave chip of the lower computer are both selected from the group consisting of a display driver chip, a touch control chip, a fingerprint recognition chip, an image processing chip, and a signal processing chip One of the integrated circuit chips.

In addition, the present invention also provides a circuit device, which includes the above-mentioned host computer chip, a cascaded chip circuit coupled to the host computer chip, and a functional unit coupled to the cascaded chip circuit, and the cascaded chip circuit The above-mentioned subordinate computer master chip and the subordinate computer slave chip are included, so that the above-mentioned inter-chip SPI communication method of cascading chip circuits can be performed.

In a feasible embodiment, the functional unit may be a display panel, a touch panel, a photo sensor array, an image sensor array, a pressure sensing unit, a temperature sensing unit, or a voltage sensing unit.

Further, the present invention also provides an information processing device, which has the above-mentioned circuit device.

In a feasible embodiment, the information processing device may be a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, a desktop computer, or an industrial computer.

1a: host computer chip

11a: First SPI unit

2a: Lower computer chip

21a: Second SPI unit

1b: host computer chip

11b: First SPI unit

2b: Lower computer main chip

20b: storage unit

21b: Second SPI unit

22b: Third SPI unit

3b: The slave chip of the lower computer

31b: Fourth SPI unit

1: host computer chip

11: Host computer chip

111: The first SPI unit

12: Lower computer main chip

120: Switch unit

121: Second SPI unit

122: The third SPI unit

13: The slave chip of the lower computer

131: Fourth SPI unit

w1: The first SPI communication line

w2: Second SPI communication line

S1: An upper computer chip transmits a cross-chip communication enable command to the lower computer main chip through a first SPI communication line

S2: The host chip of the lower computer performs a first switching operation according to the cross-chip communication enable command to electrically connect the first SPI communication line with a second SPI communication line, so that the host chip can pass through the first SPI One of the SPI communication lines connected by the communication line and the second SPI communication line directly conducts an SPI communication with the subordinate computer slave chip

S3: The upper computer chip performs one or more cross-chip SPI communications, so as to cross the lower computer master chip and carry out the SPI communication with the lower computer slave chip, so as to realize a write operation for the lower computer slave chip or a read operation

S4: The upper computer chip transmits a cross-chip communication stop command to the lower computer main chip through the first SPI communication line

S4: The slave host chip performs a second switching operation according to the inter-chip communication stop command to disconnect the first SPI communication line from the second SPI communication line

FIG. 1 is a block diagram of a conventional upper computer chip and a lower computer chip; FIG. 2 is a block diagram of a conventional upper computer chip, a lower computer master chip and a lower computer slave chip; FIG. 3 is an application of this A block diagram of a circuit device of a cross-chip SPI communication method of a cascaded chip circuit of the invention; FIG. 4 is a flow chart of a cross-chip SPI communication method of a cascaded chip circuit of the present invention; FIG. 5 is a host computer chip. The SPI signal sent out, the SPI signal received by the master chip of the lower computer, and the working timing diagram of the SPI signal received by the slave chip of the lower computer; The working timing diagram of the second read operation.

In order to enable your examiners to further understand the structure, features, objectives, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

FIG. 3 shows a block diagram of a circuit arrangement applying a cross-chip SPI communication method for cascading chip circuits according to the present invention. As shown in FIG. 3 , the circuit device 1 is included in an electronic device, and includes: a host computer chip 11 , a cascading chip circuit coupled to the host computer chip 11 , and a cascading chip circuit coupled to the cascading chip circuit functional unit. The cascaded chip circuit includes a master chip 12 of a lower-level computer and a slave chip 13 of a lower-level computer. It should be noted that the aforementioned electronic device may be a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, a desktop computer, or an industrial computer. Moreover, according to different application requirements, the functional unit may be a display panel, a touch panel, a photo sensor array, an image sensor array, a pressure sensing unit, a temperature sensing unit, or a voltage sensing unit. Correspondingly, the lower computer master chip 12 and the lower computer slave chip 13 are display driver chips, touch control chips, fingerprint recognition chips, image processing chips, or signal processing chips. piece.

FIG. 4 shows a flow chart of a cross-chip SPI communication method for cascading chip circuits according to the present invention. A cross-chip SPI communication method for cascading chip circuits of the present invention is used to enable the upper computer chip 11 to perform a first SPI communication with the lower computer master chip 12, or to communicate with the lower computer slave that cascades the lower computer master chip 12. The chip 13 performs a second SPI communication, which is called cross-chip SPI communication. As shown in FIG. 3 and FIG. 4 , the method flow first executes step S1 : a host computer chip 1 transmits a cross-chip communication enable command to the host computer chip 12 through a first SPI communication line w1 . Next, step S2 is performed: the host chip 12 of the lower computer performs a first switching operation according to the cross-chip communication enable command to electrically connect the first SPI communication line w1 with a second SPI communication line w2, so that the upper computer The chip 1 can directly perform an SPI communication with the subordinate computer slave chip 13 through an SPI communication line formed by connecting the first SPI communication line w1 and the second SPI communication line w2.

According to FIG. 3 , the host computer chip 11 has a first SPI unit 111 , and the lower computer host chip 12 has a first SPI communication circuit w1 and the first SPI unit 111 to perform the first SPI communication. The second SPI unit 21 . Meanwhile, FIG. 3 also shows that the host chip 12 of the lower computer further has a third SPI unit 122 and a switching unit 120 coupled to a switching signal, the first SPI communication line w1 and the third SPI unit 122, and the The slave chip 13 of the lower computer has a fourth SPI unit 131 that uses the second SPI communication line w2 and the switching unit 120 to perform SPI communication. According to this design, after receiving the cross-chip communication enable command, the switch unit 120 of the slave host chip 12 implements a first switch operation according to the control of a switch signal, so that the first SPI communication line w1 passes through The switching unit 120 is electrically connected to the second SPI unit 121 . In this case, the first SPI unit 111 of the host chip 11 performs SPI communication with the second SPI unit 121 of the host chip 12 through the first SPI communication line w1, and the The third SPI unit 122 performs SPI communication with the second SPI communication line w2 and the fourth SPI unit 131 of the slave chip 13 of the lower computer through the switching unit 120 .

In other words, the first SPI unit 111 of the upper computer chip 11 is electrically connected to the lower computer slave chip 13 via the first SPI communication circuit w1, the lower computer master chip 12 and the second SPI communication circuit w2 Fourth SPI unit 111 . In this case, the first An SPI unit 111 can perform a first SPI communication with the second SPI unit 121 of the slave chip 12 of the lower computer, and can also perform a second SPI communication with the fourth SPI unit 131 of the slave chip 13 of the lower computer, which is called as Cross-die SPI communication. Using the first SPI communication, the upper computer chip 11 can perform a first writing operation or a first reading operation on the lower computer main chip 12 . And, using the second SPI communication, the host computer chip 11 can perform a second write operation or a second read operation on the lower computer slave chip 13 .

As shown in FIG. 4 , the method flow then executes step S3: the host computer chip 11 performs one or more cross-chip SPI communications, so as to cross the lower computer master chip 12 and perform the SPI communication with the lower computer slave chip 13 , to implement a write operation or a read operation for the slave wafer 13 of the lower computer. FIG. 5 shows the working timing diagram of the SPI signal sent by the upper computer chip, the SPI signal received by the master chip of the lower computer, and the SPI signal received by the slave chip of the lower computer. When the second write operation is performed (that is, the upper computer chip 11 performs a read operation on the lower computer slave chip 13 across the wafer), as shown in FIG. 5 , the SPI signal sent by the upper computer chip 11 includes a CS signal, a CLK signal and a MOSI signal. It should be understood that through the first SPI communication, the SPI signal is received by the first SPI unit 121 of the host chip 12 of the lower-level computer. And, through the second SPI communication, the SPI signal is transmitted to the fourth SPI unit 131 of the slave chip 13 of the lower-level computer through the switching unit 120 and the second SPI communication line w2. It is worth noting that FIG. 5 shows that the SPI signal received by the host chip 12 of the slave computer has a signal transmission delay of a first time td1, and the SPI signal received by the slave computer from the chip 13 has a second time Signal propagation delay at time td2.

However, it is worth noting that even if the SPI signal received by the subordinate computer main chip 12 and the SPI signal received by the subordinate computer slave chip 13 have signal transmission delays of different lengths of time, the signal transmission delay of the SPI signal received by the subordinate computer main chip 12 cannot The SPI signal of the SPI signal has a signal transmission delay of the same time length, so it does not affect the correctness of the data (bit0~bit7) read out from the MOSI signal by the main chip 12 of the lower computer. Similarly, the SPI signal received by the lower computer from the chip 13 also has a signal transmission delay of the same time length, so it does not affect the correctness of the data (bit0~bit7) read by the lower computer from the MOSI signal from the chip 13.

FIG. 6 shows that the second reading from the wafer 13 for the lower machine is realized by the wafer 11 of the upper machine. A working sequence diagram of the first embodiment of the operation. As shown in FIG. 6 , for the upper computer chip 11 , CS and CLK refer to the chip selection signal and the clock signal transmitted by the upper computer chip 11 to the lower computer main chip 12 . In addition, for the lower computer main chip 12 , CS and CLK refer to the chip selection signal and the clock signal received from the upper computer chip 11 by the lower computer main chip 12 . Furthermore, for the slave chip 12 of the lower computer, CS and CLK refer to the chip selection signal and clock signal received by the slave chip 13 of the lower computer from the master chip 12 of the lower computer, that is, the upper computer chip 11 passes through the An SPI communication line w1 , the subordinate computer master chip 12 and the second SPI communication line w2 transmit the chip selection signal and the clock signal to the subordinate computer slave chip 13 .

Similarly, in FIG. 6, it can be seen that the clock signal CLK received by the subordinate computer main chip 12 has a signal transmission delay of the first time td1, and the clock signal CLK received by the subordinate computer from the chip 13 has a second time. Signal propagation delay at time td2.

When performing the second read operation (ie, the host computer chip 11 reads data from the slave chip 13 across the chip), the host computer chip 11 transmits a chip selection signal CS and a clock signal CLK to The subordinate computer master chip 12 transmits the chip selection signal CS and the clock signal CLK to the subordinate computer slave chip 13 across the wafers through the subordinate computer master chip 12 . Next, the slave chip 13 sends a MISO signal to the master chip 12 of the slave computer according to the clock signal CLK, so that the master chip 11 coupled to the master chip 12 of the slave computer 12 receives the MISO signal across the chip.

It can be found from FIG. 6 that the MISO signal received by the host chip 12 of the lower computer has a signal transmission delay of the third time td3, and the MISO signal received by the upper computer chip 11 has a signal transmission delay of the fourth time td4. . In other words, when performing the second read operation, the signal transmission delays of the first time td1, the second time td2, the third time td3, and the fourth time td4 must be taken into consideration to ensure that the host computer chip 11 reads the MISO The correctness of the data bits of the signal. Therefore, according to the design of the present invention, when the host chip 11 crosses over to the host chip 12 of the host computer and performs the read operation to the slave chip 13 of the host computer (ie, the aforementioned second read operation), it must require: (1) the host computer The slave chip 13 starts to transmit data in advance within the corresponding period of the first tuple; (2) the slave chip 12 latches the data sent from the slave chip 13 by the slave chip 13 , so as to transmit the data in a pipeline type (Pipeline) The data transfer method satisfies the timing specification of the upper computer chip 11 for a read operation of the lower computer slave chip 13; and (3) the upper computer The bit-machine chip 1 discards the data of the read first tuple when performing the read operation.

Taking the commonly used SPI mode 0 as an example, the slave chip 13 of the slave computer is triggered by the falling edge of the clock signal CLK and sends a MISO signal (MISO) to the master chip 12 of the slave computer, so that the host chip 11 can The MISO signal is received across the chip through the first SPI communication line w1 and the subordinate host chip 12 . As shown in FIG. 6 , when receiving the MISO signal, the first SPI unit 111 of the host computer chip 11 is triggered by the rising edge of the clock signal CLK to sample the MISO signal.

In an exemplary embodiment, as shown in FIG. 6 , the subordinate computer sends a MISO signal to the subordinate computer host in advance of the chip 13 by half a clock signal period (ie, within the corresponding period of the first tuple). wafer 12 . In the process of receiving the MISO signal, the host chip 12 of the lower computer performs a latching process on the MISO signal with its internal latch circuit (eg, a D flip-flop circuit), and then uses a pipeline (Pipeline) The data transfer method satisfies the timing specification of the read operation of the host chip 11 to one of the slave chips 13, so that the host chip 11 coupled to the host chip 12 of the host chip 12 crosses the chip in the next clock signal cycle receive the MISO signal. Taking the commonly used SPI mode 0 as an example, the slave chip 13 of the slave computer sends a MISO signal (MISO) to the master chip 12 of the slave computer with the rising edge of the clock signal CLK as a trigger. Then, as shown in FIG. 8 , the second SPI unit 121 of the host chip 12 of the lower computer performs latch processing on the MISO signal triggered by the rising edge of the clock signal CLK, so that the first SPI unit 111 of the host chip 11 receives the next clock signal cycle the MISO signal. When receiving the MISO signal, the first SPI unit 111 of the host computer chip 11 performs data sampling on the MISO signal with the rising edge of the clock signal CLK as a trigger.

For example, for the upper computer chip 11, the lower computer sends the MISO signal from the chip 13 in advance of 1.5 clock signal cycles (TCLK/2+ latch processing). Therefore, in order to ensure that the upper computer chip 11 can correctly read data from the MISO signal, the first byte of the MISO signal sent by the lower computer from the chip 13 must be a dummy byte. , or invalid bytes. Therefore, when performing the second read operation, it must be required that: (1) the slave chip 13 starts to transmit data in advance within the corresponding period of the first tuple. With this design, as shown in FIG. 8, the slave chip 13 of the slave computer will start to send a last valid byte of the first valid byte at the seventh CLK rising edge of the dummy byte. The most significant bit (ie, bit7) is followed by the remaining 7 bits of the first significant byte. When receiving the MISO signal, as shown in FIG. 8 , the host chip 12 of the lower-level computer uses the D flip-flop (ie, the latch circuit) to start latching the MISO signal at the 8th CLK rising edge of the first byte group processing, and then sending a MISO signal to the host computer chip 11 . Finally, when receiving the MISO signal, the host computer chip 11 starts to sample the most significant bit (ie, bit7) of the first valid byte at the first CLK rising edge of the second byte, and then samples the first The remaining 7 bits of a valid byte.

With this design, the second read operation can support high SPI communication rates. Further, as shown in FIG. 3 and FIG. 4 , the method flow further includes step S4 : the upper computer chip 1 transmits a cross-chip communication stop command to the lower computer main chip 12 through the first SPI communication line w1 . Finally, the method flow is to execute step S5 : the subordinate host chip 12 performs a second switching operation according to the inter-chip communication stop command to disconnect the first SPI communication line w1 from the second SPI communication line w2 .

In other words, step S1, step S2 and step S3 are used to make the upper computer chip 11 and the lower computer slave chip 13 cascaded with the lower computer master chip 12 to perform the second SPI communication, that is, cross-chip write operation or read operation. On the other hand, steps S4 and S5 stop the cross-chip read/write operation, and only make the upper computer chip 11 and the lower computer main chip 12 perform the first SPI communication to write to the lower computer main chip 12 operation or read operation. In more detail, through the cross-chip communication enable command to achieve a handshake switch between the upper computer chip 11 and one of the lower computer main chips 12, it can be determined when the upper computer chip 11 performs cross-chip communication, so as to avoid signal transmission/reception between chips. conflict.

Simulation data

In order to prove that the cross-chip SPI communication method of the cascaded chip circuit of the present invention has the advantages of being easy to implement and time-consuming to transmit data, etc., the SPI communication method of the prior art and the cross-chip SPI communication method of the cascaded chip circuit of the present invention are respectively used. A data read/write operation of 128k bytes (ie, 8 bits) is performed on the slave chip 13 of the lower computer at the SPI rate of 20MHz. The relevant data are organized in Tables (1) and (2) below.

In this way, the above has completely and clearly explained a cross-chip SPI communication method for cascading chip circuits of the present invention; and, from the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a cross-chip SPI communication method for cascading chip circuits, which is used for a first SPI communication between an upper computer chip and a lower computer main chip, or with a subordinate computer that cascades the lower computer main chip. The machine performs a second SPI communication from the chip, which is called cross-chip SPI communication. According to the method of the present invention, the host computer chip transmits a cross-chip communication enable command through a first SPI communication line. After being sent to the lower-level computer master chip, the lower-level computer master chip couples the first SPI communication line to a second SPI communication line, so that the upper-level computer chip can communicate with the lower-level computer slave chip through the lower-level computer master chip The cross-chip SPI communication enables the slave chip to perform a cross-chip SPI write operation or a cross-chip SPI read operation. In addition, the present invention also provides a water-pipe data buffer mechanism by arranging a latch circuit in the host chip of the lower computer, so that the speed of the cross-chip SPI reading operation can be compatible with the reading of the upper computer chip Take the operation timing.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is suitable for practical use, and indeed meets the patent requirements of the invention. Society is to pray for the best.

1: host computer chip

11: Host computer chip

111: The first SPI unit

12: Lower computer main chip

120: Switch unit

121: Second SPI unit

122: The third SPI unit

13: The slave chip of the lower computer

131: Fourth SPI unit

w1: The first SPI communication line

w2: Second SPI communication line

Claims (10)

A cross-chip SPI communication method for cascading chip circuits, comprising the following steps: a host computer chip transmits a cross-chip communication enabling command to a subordinate computer main chip through a first SPI communication line; the subordinate computer main chip is based on the cross chip. The communication enabling command executes a first switching operation to electrically connect the first SPI communication line with a second SPI communication line, so that the host computer chip can be connected through the first SPI communication line and the second SPI communication line One of the SPI communication lines formed directly conducts an SPI communication with the subordinate computer slave chip; and the host computer chip performs one or more cross-chip SPI communication, so as to cross the subordinate computer master chip and communicate with the subordinate computer slave chip. The SPI communication implements a write operation or a read operation for the slave chip of the lower computer. The cross-chip SPI communication method for cascading chip circuits as claimed in claim 1, further comprising the following steps: the upper computer chip transmits a cross-chip communication stop command to the lower computer main chip through the first SPI communication line; and The slave host chip performs a second switching operation according to the inter-chip communication stop command to disconnect the first SPI communication line from the second SPI communication line. The cross-chip SPI communication method for cascading chip circuits according to claim 1, wherein the upper computer chip has a first SPI unit, and the lower computer main chip has a communication line using the first SPI and the first SPI The unit performs a SPI communication with a second SPI unit. The cross-chip SPI communication method for cascading chip circuits as claimed in claim 3, wherein the subordinate computer master chip further has a third SPI unit and a switching unit, and the subordinate computer slave chip has communication using the second SPI A fourth SPI unit that performs the SPI communication with the switching unit. The cross-chip SPI communication method for cascaded chip circuits according to claim 4, wherein the switching unit performs the first switching operation or the second switching operation according to the control of a switching signal. The cross-chip SPI communication method of cascaded chip circuits as claimed in claim 4, wherein the subordinate computer master chip has a latch circuit for performing a latching process on the data sent by the subordinate computer slave chip, so as to use A water-pipe data transmission method satisfies the timing specification of the read operation of the slave chip of the host computer to the slave chip of the slave computer. The cross-chip SPI communication method for cascaded chip circuits as claimed in claim 6, wherein the host computer chip discards the data of the read first tuple when performing the read operation. The cross-chip SPI communication method for cascaded chip circuits according to claim 7, wherein when the upper computer chip is performing the read operation, the lower computer slave chip will be in the corresponding period of the first tuple Start sending data in advance. A circuit device, which includes a host computer chip as described in claim 1, a cascaded chip circuit coupled to the host computer chip, and a functional unit coupled to the cascaded chip circuit, and the cascaded chip circuit includes such as The master chip of the lower computer and the slave chip of the lower computer according to claim 1 can execute the cross-chip SPI communication method of cascaded chip circuits as described in any one of claim 1 to 8. An information processing device, which has the circuit device as claimed in claim 9, and the information processing device is selected from a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control An electronic device in the group consisting of devices, desktop computers, and industrial computers.

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