TWI764481B - Chassis management control device and chassis management control system - Google Patents

Abstract

A chassis management control device is used to connect to one or more baseboard management controllers through a multiplexer switch, and the multiplexer switch is connected to each baseboard management controller through plural connection interfaces. The chassis management control device includes a circuit board, a chassis management controller, a firmware memory, and a random access memory. The circuit board has a card edge connector extending on an edge of the circuit board, and the card edge connector includes a first pin group and at least one second pin group. The card edge connector is used to connect to the multiplexer switch. The chassis management controller is electrically connected to the first pin group. After startup, the chassis management controller loads the firmware from the firmware memory to perform an initialization operation; the chassis management controller sends out a management data packet and a designated address through the card edge connector, and the designated address corresponds to one of plural connection interfaces of the multiplexer switch.

Description

Chassis management control device and chassis management control system

The present invention relates to management and control of multiple baseboard management controllers, in particular to a chassis management control device and a chassis management control system.

The existing Chassis Management Controller (CMC) adopts a centralized architecture, and multiple baseboard management controllers use relay boards for auxiliary wiring, and are respectively connected to different pin groups of the CMC. The baseboard management controller can identify different baseboard management controllers through the different pin groups connected.

When the number of baseboard management controllers increases with the expansion of the system architecture, the relay boards and wiring will take up a lot of space. At the same time, when the number of baseboard management controllers is increased or decreased, no matter whether the chassis management controller needs to be repaired abnormally, the relay board must be powered off, so that the system cannot work for a period of time.

In addition, the number of pins of the chassis management controller is limited. When the number of baseboard management controllers gradually increases, the number of pins of the chassis management controller will be insufficient, which limits the expansion of the system architecture.

Based on the above technical issues, the present invention proposes a chassis management control device and a chassis management control system, which can change the connection structure between the chassis management control device and the baseboard management controller, so that the number of baseboard management controllers can be easily changed.

The present invention provides a chassis management control device for connecting to one or more baseboard management controllers through a multiplex switch, and the multiplex switch is respectively connected to each baseboard management controller through a plurality of connection interfaces. The chassis management control device includes a circuit board, a chassis management controller, a firmware storage and a temporary memory.

The circuit substrate has a card edge connector extending from one side edge of the circuit substrate, and the card edge connector includes a first pin set and at least a second pin set, and the card edge connector is used for connecting to the multiplex switch device. The chassis management controller is arranged on the circuit substrate and is electrically connected to the first pin group. The firmware storage is arranged on the circuit substrate and is electrically connected to the chassis management controller for storing a firmware of the chassis management controller. The temporary storage memory is arranged on the circuit substrate and is electrically connected to the chassis management controller for providing a working temporary storage space.

The chassis management controller loads the firmware from the firmware storage after being started to perform an initialization operation; the chassis management controller is used for sending a management data packet and a designated address through the card edge connector, and the designated address corresponds to One of the connection interfaces of the multiplexer.

In at least one embodiment, the chassis management controller receives a response data packet and a hardware address through the card edge connector, and the hardware address corresponds to one of the connection interfaces of the multiplexer switch.

In at least one embodiment, the card edge connector is a connector conforming to the OCP NIC 3.0 standard, and the at least one second pin group is a pin group conforming to the PCIe standard.

In at least one embodiment, the chassis management controller and the at least one second pin group are air-connected.

In at least one embodiment, the chassis management control device further includes a network chip and at least one network connector; the network chip is electrically connected to the chassis management controller, the network connector is electrically connected to the network chip, and the network chip is electrically connected to the network chip. The circuit connector is used to connect to a network switching device, so that the chassis management controller is connected to a network.

In at least one embodiment, the at least one first connection interface is connected to an expansion slot, and the expansion slot is used for inserting the card edge connector.

The present invention also provides a chassis management control system for connecting to a plurality of baseboard management controllers, including the aforementioned chassis management control device, a relay substrate and a multiplex switch. The relay substrate has at least one first connection interface and a plurality of second connection interfaces. The multiplex switch is disposed on the relay substrate, and at least one first connection interface and each of the second connection interfaces are electrically connected to the multiplex switch. The card edge connector of the chassis management control device is connected to the first connection interface, the baseboard management controllers are respectively connected to the second connection interfaces, and the second connection interfaces are respectively corresponding to a hardware address.

The multiplex switch receives the management data packet and the designated address sent by the chassis management control device through the first connection interface, and temporarily stores the management data packet; The second connection interface is sent out.

In at least one embodiment, the multiplexer receives a response data packet through one of the second connection interfaces, temporarily stores it, and obtains a corresponding hardware address; the multiplexer switches the response data packet and the hardware address. It is transmitted to the chassis management controller through at least one first connection interface.

In at least one embodiment, the card edge connector is a connector conforming to the OCP NIC 3.0 standard, and the at least one second pin group is a pin group conforming to the PCIe standard.

In at least one embodiment, the chassis management controller and the at least one second pin group are air-connected.

In at least one embodiment, the relay substrate has more than two first connection interfaces, and the chassis management control system has two chassis management control devices, which are connected to the multiplex switch through each of the first connection interfaces; the multiplex switch is used for Enable one of the chassis management controls and toggle the other chassis management control to idle.

In at least one embodiment, the multiplexer continuously monitors whether the active chassis management control device operates normally; when the active chassis management control device is abnormal, the multiplexer switches the chassis management control device to idle, and enables another chassis management control device Chassis management controls.

In at least one embodiment, each of the first connection interfaces respectively has at least one designated pin for connecting to each other through the relay substrate, and the active chassis management control device is used for sending an update command to the multiplexer, so that the multiplexer The switch switches another chassis management control device into firmware update mode; the active chassis management control device transmits a firmware image file to the other chassis management control device through the designated pin, so as to update the firmware of the other chassis management control device. write to the bulk storage.

In at least one embodiment, the active chassis management control device performs handshake communication through the designated pins to determine whether another chassis management control device is idle. If the other chassis management control device is idle, the active chassis The management control device sends an update command to the multiplexer.

In the present invention, through the relay of the multiplex switch, the management control packet is first temporarily stored in the multiplex switch, and then sent to the correct baseboard management controller through the corresponding second connection interface according to the specified address. Likewise, the response data packets are temporarily stored in the multiplex switch, and then sent to the chassis management control device according to the source attached hardware address. Therefore, the external connection of the chassis management control device can be connected to multiple baseboard management controllers as long as there is one first pin group, and the number of connections is not limited by the number of pins of the first pin group. At the same time, the number of baseboard management controllers is also easy to increase or decrease. It is only necessary to add or delete the corresponding code in the firmware of the chassis management control device, and it is related to the hardware address to increase or decrease the number of baseboard management controllers. The number of pins of the card edge connector does not need to be redefined, and the connection state of each pin of the card edge connector does not need to be changed.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 , which are a chassis management control device 10 disclosed in an embodiment of the present invention, which is suitable for a chassis management control system and is used for connecting to one or more substrates through a multiplex switch 20 The management controllers 31-34 are used to manage the operation of one or more motherboards.

As shown in FIG. 1 and FIG. 2 , the chassis management control device 10 is in the form of a board card, and includes a circuit board 110 , a baseboard management controller (BMC) 120 , a firmware storage 130 and a temporary storage memory 140.

As shown in FIG. 1 , the circuit substrate 110 has a card edge connector 112 extending from one edge of the circuit substrate 110 . The circuit substrate 110 is also configured with necessary circuits, such as printed circuits, for electrically connecting the card edge connector 112 , the Chassis Management Controller (CMC) 120 , the firmware storage 130 and the temporary memory 140 . The card edge connector 112 includes a first pin set 1121 and one or more second pin sets 1122 .

As shown in FIG. 1 , the chassis management controller 120 is disposed on the circuit substrate 110 and is electrically connected to the first pin group 1121 . The firmware storage 130 is disposed on the circuit substrate 110 and is electrically connected to the chassis management controller 120 for storing a firmware of the chassis management controller 120 . The chassis management controller 120 loads the firmware from the firmware storage 130 after startup to perform initialization and subsequent management and control operations. The temporary memory 140 is disposed on the circuit substrate 110 and is electrically connected to the chassis management controller 120 . The temporary storage memory 140 is used for providing a working temporary storage space for the chassis management controller 120 to temporarily store working data. Generally, the firmware storage 130 is a non-volatile memory, such as EEPROM or flash memory, to store firmware semi-permanently. The temporary memory 140 is a volatile memory with a fast data read and write rate, such as SRAM or SDRAM.

As shown in FIG. 3 , the chassis management controller 120 is used for connecting to a multiplexer switch 20 . Meanwhile, the baseboard management controllers 31 to 34 are also connected to the multiplexer switch 20 . A specific embodiment of the multiplexer 20 is a Complex Programmable Logic Device (CPLD) for implementing the required arithmetic and combinational logic. According to the electrical characteristics of the connection pins or the received device identification codes, the multiplex switch 20 determines whether the devices connected to different hardware addresses are the chassis management controller 120, the baseboard management controllers 31-34 or other devices, so as to The master-slave relationship between the chassis management controller 120 and the baseboard management controllers 31 to 34 is set. The multiplex switch 20 can also buffer and temporarily store the received data packets, and then correctly transmit them to the predetermined destination according to the identification information in the data packets.

As shown in FIGS. 3 and 4 , specifically, the card edge connector 112 is a connector compliant with the OCP NIC 3.0 standard (Open Compute Project Network Interface Card 3.0). The card edge connector 112 conforming to the OCP NIC 3.0 standard has 168 pins, and the second pin group 1122 is a pin group conforming to the PCIe standard. Based on the difference in electrical characteristics, the second pin group 1122 is configured as an empty connection, and is not electrically connected to the chassis management controller 120 , the firmware storage 130 and the temporary memory 140 to avoid errors. state occurs. In the embodiment of the present invention, a pin group that does not belong to the PCIe standard is used as the first pin group 1121 to be connected to the chassis management controller 120 , so that the chassis management controller 120 can be connected to the multiplex switch through the first pin group 1121 device 20.

FIG. 4 is a schematic diagram of pin assignment of the card edge connector 112 . The OCP NIC 3.0 compliant card edge connector 112 has four keys. In FIG. 4 , the four plug-in parts of the card edge connector 112 are separated by dashed lines. The markings in the solid rectangular lines are the pins of the OCP NIC 3.0, and the cables extending outside the rectangular shape are connected to the chassis management controller. The corresponding pins of 120 or the lines connected to the circuit substrate 110 . In the embodiment of the present invention, the first plug-in portion (pins OA1~OA14, OB1~OB14) is mainly used as the first pin group 1121 in combination with some other pins, and the other pins are left empty (not shown in FIG. 4 ). shown) as the second pin group 1122; some of the pins are used to meet the electrical requirements of the circuit substrate 110, such as grounding, and the working power supply of other components. The pin group that conforms to the PCIe standard is suitable for high-speed signal transmission, and the driving voltage level is different from that of the general CMC chip, so it is not used by empty connection. The first pin group 1121 can define a combination of CLK and SDA as an I2C interface for communication between the chassis management controller 120 and the multiplex switch 20 .

As shown in FIG. 3 , the multiplexer 20 is disposed on a relay substrate 20a, and the relay substrate 20a has at least a first connection interface 210 and a plurality of second connection interfaces 221-224, and the first connection interface 210 and All or part of the pins of the second connection interfaces 221 - 224 are electrically connected to the multiplex switch 20 . The card edge connector 112 of the chassis management control device 10 is electrically connected to the first connection interface 210 , so that the chassis management control device 10 is connected to the multiplex switch 20 through the card edge connector 112 and the first connection interface 210 . The baseboard management controllers 31-34 are respectively connected to the second connection interfaces 221-224, so that the baseboard management controllers 31-34 are connected to the multiplexer 20 through the second connection interfaces 221-224, and the second connection interfaces 221 to 224 respectively correspond to a hardware address. For example, the hardware addresses of the baseboard management controllers 31 to 34 may be 0x31 to 0x34, respectively.

Specifically, the first connection interface 210 of the relay substrate 20a is connected to an expansion slot 230 through a signal cable. The expansion slot 230 also conforms to the OCP NIC 3.0 specification for the card edge connector 112 to be inserted and connected to Chassis management controller 120 to multiplexer 20 . The expansion slot 230 can still maintain the standard OCP NIC 3.0 configuration for other devices compliant with the OCP NIC 3.0 specification to be connected to the multiplexer switch 20 . Since the chassis management controller 120 and the second pin group 1122 of the card edge connector 112 are in an empty connection configuration, the multiplex switch 20 can identify the chassis management control device 10 and other OCPs through the difference in the plug state. Differences between NIC 3.0 devices, for example, the multiplex switch 20 can change the voltage level of a specific pin to determine whether the expansion slot 230 is plugged into another device that complies with the OCP NIC 3.0 specification or the chassis management control device 10, and the switch is correct communication function. The baseboard management controllers 31-34 can be directly soldered to the corresponding contacts of the relay substrate 20a by means of cables, or can be connected through pluggable electrical connectors; similarly, the baseboard management controllers 31-34 are connected to the multiplexer The switches 20 can also be connected through I2C.

As shown in FIG. 3 and FIG. 5 , when the chassis management control device 10 manages and controls one of the multiple baseboard management controllers 31 to 34 , for example, the first baseboard management controller 31 is managed and controlled, and the chassis management The controller 120 sends the management data packet A and the designated address through the card edge connector 112; the designated address may be 0x31 as exemplified above. The multiplex switch 20 receives the management data packet A and the designated address 0x31 through the first connection interface 210 . Then, the multiplex switch 20 sends the management data packet A through the second connection interface 221 whose hardware address matches 0x31 according to the specified address 0x31, and the first baseboard management controller 31 can then transmit the management data packet A through the second connection interface 221. Receive management data packets and execute corresponding operations.

As shown in FIG. 5 , the chassis management control device 10 may continuously send out management data packets to manage and control different baseboard management controllers 31 to 34 . For example, the chassis management control device 10 sends out the management data packet A and the designated address 0x31, and continuously sends out the management data packet D and the designated address 0x34 for controlling the fourth baseboard management controller 34 . At this time, the multiplex switch 20 can temporarily store the management data packets A, D and the designated addresses 0x31, 0x34 according to the received time sequence, and sequentially pass through the second connection interfaces 221, 224 whose hardware addresses match 0x31, 0x34 The outgoing management data packets A, D.

As shown in FIG. 3 and FIG. 6 , on the contrary, the baseboard management controllers 31 to 34 will also periodically or after accepting the request, send out response data packets, so as to return the status of the motherboard or host of the controlled end to the chassis management Control device 10 . For example, the third baseboard management controller 33 sends the response data packet C through the second connection interface 223 . At this time, the multiplex switch 20 receives the response data packet C through the third second connection interface 223 and temporarily stores it, and the corresponding hardware address can be obtained as 0x33. Next, the multiplex switch 20 transmits the response data packet C and the hardware address 0x33 to the chassis management controller 120 of the chassis management control device 10 through the first connection interface 210 . According to the hardware address 0x33, the chassis management controller 120 can determine that the response data packet C is sent by the third baseboard management controller 33 .

As shown in FIG. 6, a plurality of baseboard management controllers 31-34 may continue to send response data packets. For example, after the third baseboard management controller 33 sends the response data packet C, the second baseboard management controller 32 also sends the response data packet B. The multiplex switch 20 receives the response data packets C and B from the third second connection interface 223 and the second second connection interface 222 in sequence, and temporarily stores the response data packets C and B according to the received time sequence and appends the response data packets C and B. Hardware addresses 0x33, 0x32. Then, according to the received time sequence, the multiplex switch 20 sends the response data packets C and B in sequence and attaches the corresponding hardware addresses 0x31 and 0x34, so that the chassis management control device 10 receives the response data packets C and B in sequence, and According to the hardware addresses 0x31 and 0x34, it is determined that the response data packets C and B are respectively sent by the third baseboard management controller 33 and the second baseboard management controller 32 . The aforementioned hardware addresses 0x31 to 0x34 are only examples, and are not used to limit the recording format of the hardware addresses.

As shown in FIG. 1 and FIG. 7 , the chassis management control device 10 according to the embodiment of the present invention further includes a network interface 150 . The network interface 150 includes a network chip 152 and one or more network connectors 154 . The network chip 152 is electrically connected to the chassis management controller 120 , and the network connector 154 is electrically connected to the network chip 152 . The network connector 154 is used to connect to a network switching device, so that the chassis management controller 120 is connected to a network through the network interface 150 . Each host is also connected to the network, so that the baseboard management controllers 31 to 34 can be connected to the network and have an IP Address. By recording the network protocol addresses corresponding to the baseboard management controllers 31-34, the chassis management controller 120 can establish a connection with the baseboard management controllers 31-34 through the network, respectively, to send out management data packets or receive response data packets . That is, the network interface 150 can be used as a backup device to provide a backup line when the multiplex switch 20 is abnormal or the newly added baseboard management controllers 31 to 34 are not connected to the multiplex switch 20 .

Referring to FIG. 8 , the multiplexer 20 may have two or more first connection interfaces 210 . Each of the first connection interfaces 210 is respectively connected to a chassis management control device 10 through an expansion slot 230 . As shown in FIG. 4 , the multiplexer 20 enables one of the chassis management control devices 10 as the active chassis management control device 10 , and switches the remaining chassis management control devices 10 to idle as the backup chassis management control device 10 '. The multiplexer 20 continuously monitors whether the enabled chassis management control device 10 is functioning normally. The monitoring method is that the multiplex switch 20 continues to communicate with the active chassis management control device 10 in handshake communication. If the active chassis management control device 10 does not respond to the communication for a preset time, the multiplex switch 20 Determines that the state of the chassis management and control device 10 being activated is abnormal, and the abnormal state includes the failure of the chassis management and control device 10 or the disconnection of the electrical connection line. When the active chassis management control device 10 is abnormal, the multiplex switch 20 switches the active chassis management control device to idle, and enables the redundant chassis management control device 10'.

Referring to FIG. 4 and FIG. 8, the two chassis management control devices 10, 10' can update the firmware of each other. Specifically, not all the pins of the first connection interface 210 are connected to the multiplex switch 20, and the designated pins of each first connection interface 210 are connected through the relay substrate 20a, so that the two chassis management control devices 10, A communication connection is established between 10' through the designated pin. The active chassis management control device 10 can first receive the updated firmware from the outside (such as the network), and conduct handshake communication through the designated pins between the two chassis management control devices 10, so that the active chassis management control device 10 The device 10 determines whether the redundant chassis management control device 10' is idle. If the redundant chassis management control device 10' is idle, the active chassis management control device 10 sends an update command to the multiplex switch 20, so that the multiplex switch 20 can update the chassis of the redundant chassis management control device 10' through the OA4 pin The CMC_FW_RECOVERY_MODE pin of the management controller 120 transmits an enable signal, so that the chassis management controller 120 of the redundant chassis management control device 10' enters the firmware update mode. Then, the active chassis management control device 10 transmits the firmware image file to the redundant chassis management control device 10' through the designated pins, such as CMC_CMC_SPI_MOSI, CMC_CMC_SPI_MISO, and performs the operation on the firmware storage 130 of the redundant chassis management control device 10'. Write to overwrite the original firmware with the firmware image file. After the update is completed, the multiplexer 20 can switch the activation and inactivity of the two chassis management control devices 10 , 10 ′, and update the firmware of the other chassis management control device 10 .

In the present invention, through the relay of the multiplex switch 20, the management control packet is first temporarily stored in the multiplex switch 20, and then sent to the correct baseboard management controller 31 through the corresponding second connection interfaces 221-224 according to the specified address. ~34. Likewise, the response data packet is temporarily stored in the multiplex switch 20 in advance, and then sent to the chassis management control device 10 according to the source attached hardware address. Therefore, the external connection of the chassis management control device 10 can be connected to multiple baseboard management controllers 31 to 34 only by having one set of the first pin group 1121 , and the number of connections is not limited to the pins of the first pin group 1121 . number. At the same time, the number of baseboard management controllers 31 to 34 is also easy to increase or decrease. It is only necessary to add or delete the corresponding code in the firmware of the chassis management control device 10, and it is related to the hardware address to increase or decrease the baseboard. The number of the controllers 31 to 34 is managed without redefining each pin of the card edge connector 112 or changing the connection state of each pin of the card edge connector 112 .

10: Chassis management control device 10’: Redundant chassis management control device 110: circuit substrate 112: Card edge connector 1121: The first pin group 1122: The second pin group 120: Chassis Management Controller 130:Firmware storage 140: Temporary memory 150: Web Interface 152: Network chip 154: Network Connector 20: Multiplexer 20a: Relay substrate 210: The first connection interface 221~224: The second connection interface 230: Expansion slot 31~34: Baseboard Management Controller

FIG. 1 is a top view of a chassis management control device in an embodiment of the present invention. FIG. 2 is a circuit block diagram of a chassis management control device according to an embodiment of the present invention. FIG. 3 is a schematic block diagram of a chassis management control device according to an embodiment of the present invention. FIG. 4 is a schematic diagram of the pin position of the card edge connector according to the embodiment of the present invention. FIG. 5 is a schematic diagram of a data management packet sent by a chassis management control device according to an embodiment of the present invention. FIG. 6 is a schematic diagram of a chassis management control device receiving a response data packet according to an embodiment of the present invention. FIG. 7 is a schematic diagram of a chassis management control device connected to a baseboard management controller through a network according to an embodiment of the present invention. FIG. 8 is a schematic diagram of a multiplex switch connected to two chassis management control devices in an embodiment of the present invention.

10: Chassis management control device

110: circuit substrate

112: Card edge connector

1121: The first pin group

1122: The second pin group

120: Chassis Management Controller

130:Firmware storage

140: Temporary memory

150: Web Interface

152: Network chip

154: Network Connector

Claims (14)

A chassis management control device is used to connect to one or more baseboard management controllers through a multiplex switch, and the multiplex switch is respectively connected to each of the baseboard management controllers through a plurality of connection interfaces; the chassis management control The device contains: A circuit substrate has a card edge connector extending from one side edge of the circuit substrate, and the card edge connector includes a first pin set and at least a second pin set, and the card edge connector is used for connected to the multiplexer; a chassis management controller disposed on the circuit substrate and electrically connected to the first pin group; a firmware storage disposed on the circuit substrate and electrically connected to the chassis management controller for storing a firmware of the chassis management controller; and a temporary storage memory disposed on the circuit substrate and electrically connected to the chassis management controller for providing a working temporary storage space; The chassis management controller loads the firmware from the firmware storage to perform an initialization operation after startup; the chassis management controller is used for sending a management data packet and a designated address through the card edge connector , and the designated address corresponds to one of the connection interfaces of the multiplexer. The chassis management control device of claim 1, wherein the chassis management controller receives a response data packet and a hardware address through the card edge connector, and the hardware address corresponds to the one of these connection interfaces. The chassis management control device of claim 1, wherein the card edge connector is a connector conforming to the OCP NIC 3.0 standard, and the at least one second pin group is a pin group conforming to the PCIe standard. The chassis management control device as claimed in claim 1, wherein the chassis management controller and the at least one second pin group are connected in air. The chassis management control device of claim 1, further comprising a network chip and at least one network connector; the network chip is electrically connected to the chassis management controller, and the network connector is electrically connected to the network connector A network chip, the network connector is used for connecting to a network switching device, so that the chassis management controller is connected to a network. The chassis management control device of claim 1, wherein the at least one first connection interface is connected to an expansion slot, and the expansion slot is used for the card edge connector to be inserted. A chassis management control system for connecting to multiple baseboard management controllers, comprising: The chassis management control device as described in the preceding claim 1; a relay substrate having at least one first connection interface and a plurality of second connection interfaces; and A multiplexer switch disposed on the relay substrate; wherein the at least one first connection interface and each of the second connection interfaces are electrically connected to the multiplexer switch; the card edge of the chassis management control device is connected The device is connected to the at least one first connection interface, each of the baseboard management controllers is connected to each of the second connection interfaces, and each of the second connection interfaces respectively corresponds to a hardware address; Wherein, the multiplex switch receives the management data packet and the designated address sent by the chassis management control device through the at least one first connection interface, and temporarily stores the management data packet; according to the designated address, the management data packet is The data packet is sent out through the second connection interface where each of the hardware addresses corresponds to the specified address. The chassis management control system of claim 7, wherein the multiplexer receives a response data packet through one of the second connection interfaces, temporarily stores it, and obtains the corresponding hardware address; The industrial switch transmits the response data packet and the hardware address to the chassis management controller through the at least one first connection interface. The chassis management control system of claim 7, wherein the card edge connector is a connector conforming to the OCP NIC 3.0 standard, and the at least one second pin group is a pin group conforming to the PCIe standard. The chassis management control system as claimed in claim 7, wherein the chassis management controller and the at least one second pin group are connected in air. The chassis management and control system of claim 7, wherein the relay substrate has two or more of the first connection interfaces, and the chassis management and control system has two of the chassis management and control devices, through each of the first connection interfaces is connected to the multiplex switch; the multiplex switch is used for enabling one of the chassis management control devices and switching the other chassis management control device to idle. The chassis management control system of claim 11, wherein the multiplexer continuously monitors whether the enabled chassis management control device operates normally; when the enabled chassis management control device is abnormal, the multiplexer switches The chassis management control is idle, and another of the chassis management control is enabled. The chassis management control system of claim 11, wherein each of the first connection interfaces respectively has at least one designated pin for connecting to each other through the relay substrate, and the chassis management control device in use is used for sending The update command is sent to the multiplex switch, so that the multiplex switch switches another of the chassis management control device to enter the firmware update mode; the enabled chassis management control device transmits a firmware image file through the designated pins to the the other chassis management control device for writing to the firmware storage of the other chassis management control device. The chassis management control system of claim 13, wherein the enabled chassis management control device performs handshake communication through the designated pins to determine whether the other chassis management control device is idle, if the other chassis management control device is idle The management control device is idle, and the active chassis management control device sends the update command to the multiplexer.

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