TWI764459B - Source driving circuit - Google Patents

Abstract

A source driving circuit coupled to a display panel and a gate driving circuit is disclosed. The source driving circuit includes an ESD detection unit, an output enabling unit and a data output unit. The ESD detection unit provides an ESD detection signal when an ESD interference event is detected. The output enabling unit, coupled to the ESD detection unit and the gate driving circuit, provides an output enabling signal to the gate driving circuit according to the ESD detection signal to make the gate driving circuit provide a low-level gate driving signal to the display panel. The data output unit, coupled to the ESD detection unit and the display panel, provides a HiZ data signal to the display panel according to the ESD detection signal, so that the screen displayed on the display panel can comply with a specific standard.

Description

source driver circuit

The present invention relates to a display device, in particular to a source driving circuit applied to a display panel.

Generally speaking, the external electrostatic discharge (ESD) interference usually causes the operation of the vehicle source driver IC to be abnormal in a short period of time, thus causing the display screen of the vehicle display panel to flicker for a short time. The screen or flashing line and other pictures abnormally occur, resulting in poor visual experience for those viewing the displayed picture.

Currently, the highest level (Class A) electrostatic discharge protection standard adopted in the industry is: under the interference of electrostatic discharge, the screen displayed on the vehicle display panel cannot appear abnormal screen such as splash screen and flashing line. Although there are conventional circuit countermeasures against electrostatic discharge interference in automotive source driver ICs, these circuit countermeasures may still fail due to factors such as the liquid crystal characteristics of the display panel and the misalignment of circuit signals, resulting in automotive display panels. The display screen of the device still has abnormal screen such as splash screen and flashing line, which needs to be further improved.

In addition, the conventional circuit countermeasures are not suitable for automotive source driving ICs including line buffers or frame buffers, so it is still necessary to further propose corresponding circuit countermeasures to improve the The above display screen is abnormal.

In view of this, the present invention proposes a source driving circuit applied to a display panel to effectively solve the above-mentioned problems encountered in the prior art.

A specific embodiment according to the present invention is a source driving circuit. In this embodiment, the source driving circuit is coupled to the display panel and the gate driving circuit. The source driving circuit includes an electrostatic discharge detection unit, an output enabling unit and a data output unit. The electrostatic discharge detection unit is used for providing an electrostatic discharge detection signal when an electrostatic discharge event is detected. The output enable unit is coupled to the electrostatic discharge detection unit and the gate drive circuit, and is used for providing an output enable signal to the gate drive circuit according to the electrostatic discharge detection signal, so that the gate drive circuit sends a gate drive signal to the display panel at low potential. The data output unit is coupled to the electrostatic discharge detection unit and the display panel, and is used for providing a data signal with high impedance to the display panel according to the electrostatic discharge detection signal, so that the image displayed by the display panel conforms to a specific specification.

In one embodiment, the display panel is a vehicle display panel and the source driving circuit is a vehicle source driving circuit.

In one embodiment, a specific specification is that when the electrostatic discharge event occurs, the screen displayed on the display panel cannot have the phenomenon of flashing screen or flashing line.

In one embodiment, the display panel includes a plurality of pixels and each pixel includes a transistor switch and a capacitor, the gate of the transistor switch is coupled to the gate driving signal at a low level (VGL), the The capacitor is coupled to one end of the transistor switch and the other end of the transistor switch is coupled to the data signal with high impedance (HiZ), so as to eliminate the leakage path of the charge stored in the capacitor and avoid the image displayed on the display panel A splash screen appears.

In one embodiment, the output enable (OE) signal can last until the end of the current frame or until the next frame or multiple frames, so that the display panel continues to display the picture of the previous frame.

In one embodiment, the source driver circuit includes a frame buffer. If the electrostatic discharge event occurs in the Nth frame, the output enable (OE) signal is only in the (N+1)th frame. Start with the gate drive signal low (VGL), where N is a positive integer.

Another specific embodiment according to the present invention is also a source driving circuit. In this embodiment, the source driving circuit is coupled to the display panel and the gate driving circuit. The source driving circuit includes a data output unit, an output enable unit and a timing control unit. The data output unit is coupled to the display panel for providing data signals to the display panel. The electrostatic discharge detection unit is used for providing an electrostatic discharge detection signal when an electrostatic discharge event is detected. The output enable unit is coupled to the electrostatic discharge detection unit and the gate drive circuit, and is used for providing an output enable signal to the gate drive circuit according to the electrostatic discharge detection signal, so that the gate drive circuit sends a gate drive signal to the display panel at low potential. The timing control unit is coupled to the electrostatic discharge detection unit and the gate driving circuit, and is used for switching the first clock signal originally provided to the gate driving circuit to the second clock signal when the electrostatic discharge detection signal is activated, and when the electrostatic discharge detection signal is activated When the discharge detection signal ends, it switches back to the first clock signal, so that the picture displayed on the display panel conforms to a specific specification.

Compared with the prior art, the source driver circuit of the present invention can output a high impedance (HiZ) data signal to the display panel or output an analog clock signal to the gate driver when an electrostatic discharge event is detected, so as to effectively Traditionally, it can avoid the abnormality of the display screen such as flickering screen and flickering line due to factors such as the liquid crystal characteristics of the display panel or the misalignment of circuit signals. In addition, the present invention also considers the case where the source driver circuit has a line buffer or a frame buffer and proposes corresponding circuit countermeasures, so it is also applicable.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements/components using the same or similar numbers in the drawings and the embodiments are intended to represent the same or similar parts.

According to an embodiment of the present invention, a source driving circuit of a display panel is provided. In this embodiment, the display panel may be a vehicle display panel and the source driving circuit may be a vehicle source driving circuit, but not limited thereto.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a display device including a display panel, a source driving circuit and a gate driving circuit.

As shown in FIG. 1 , the display device 1 includes a display panel DA, a source driver circuit SIC, and a gate driver circuit GIC. The gate driving circuit GIC provides the gate driving signal GP to the display panel DA. The source driving circuit SIC provides the source data signal SDA to the display panel DA. In addition, the source driver circuit SIC also provides an output enable signal OE and a pulse signal CKV to the gate driver circuit GIC.

Next, please refer to FIG. 2 , which is a functional block diagram of the source driver circuit in this embodiment.

As shown in FIG. 2 , the source driving circuit 2 is coupled to the display panel PL and the gate driving circuit GD. The source driving circuit 2 includes an electrostatic discharge detection unit 20 , an output enabling unit 22 and a data output unit 24 . The electrostatic discharge detection unit 20 is used for providing an electrostatic discharge detection signal ESDS when an electrostatic discharge event is detected. The output enable unit 22 is coupled to the electrostatic discharge detection unit 20 and the gate drive circuit GD, and is used for providing the output enable signal OE to the gate drive circuit GD according to the electrostatic discharge detection signal ESDS, so that the gate drive circuit GD provides the The gate driving signal GP of the display panel PL is at a low potential (VGL). The data output unit 24 is coupled to the electrostatic discharge detection unit 20 and the display panel PL, and is used for providing a data signal SDA with a high impedance (HiZ) to the display panel PL according to the electrostatic discharge detection signal ESDS, so that the image displayed by the display panel PL be able to meet specific specifications. In practical applications, the above-mentioned specific specification means that when an electrostatic discharge event occurs, the screen displayed on the display panel PL cannot exhibit abnormal phenomena such as screen splashes or flashing lines, but it is not limited thereto.

For example, as shown in FIG. 3 , during the Nth frame FN and the (N+1)th frame F(N+1), since no ESD event occurs, the ESD detection signal ESDS is not activated and maintained at a low level, and the source driver circuit SIC provides the gate driver circuit GIC with the output enable signal OE and the clock signal CKV, the source driver circuit SIC provides the data signal SDA to the display panel PL, and the gate driver circuit GD The gate driving signals GP supplied to the display panel PL are maintained normally.

After the time t5 enters the (N+2)th frame F(N+2), there is no ESD event yet, so everything remains normal. Until time t6, since the electrostatic discharge detection unit 20 detects the occurrence of an electrostatic discharge event, the electrostatic discharge detection signal ESDS will change from a low level to a high level to indicate the occurrence of the electrostatic discharge event.

At this time, the output enable unit 22 provides a high-level output enable signal OE to the gate driving circuit GD, so that the gate driving circuit GD provides a low-level (VGL) gate driving signal GP to the display panel PL. The data output unit 24 simultaneously provides a high impedance (HiZ) data signal SDA to the display panel PL. In this way, the leakage paths in the pixels of the display panel PL can be eliminated, so that abnormal phenomena such as screen flashes or flashing lines on the display screen of the display panel PL can be avoided when an electrostatic discharge event occurs.

It should be noted that the above operation can continue until the end of the (N+2)th frame F(N+2), or until the (N+3)th frame F(N+3), or even the (N+3)th frame F(N+3) according to actual needs. N+4) frames F(N+4) or more frames without specific limitation.

Next, please refer to FIG. 4 , the display panel 3 includes a plurality of pixels and each pixel includes a transistor switch and a capacitor respectively. Taking the upper left pixel as an example, the gate of the transistor switch M11 is coupled to the gate drive line GL1 for transmitting the gate drive signal at a low potential (VGL), and the capacitor CS is coupled to the gate of the transistor switch M11 One end and the other end of the transistor switch M11 are coupled to the data signal SDA with high impedance (HiZ), so as to eliminate the leakage path of the charge stored in the capacitor CS. As for other pixels, it can be deduced in the same way, which will not be repeated here. In this way, since possible leakage paths in all the pixels of the display panel PL have been eliminated, it is possible to effectively avoid the screen flicker phenomenon of the picture displayed on the display panel PL.

In another embodiment, the source driver circuit may further include a timing control unit for generating a clock signal CKV to the gate driver circuit. Please refer to FIG. 5 , which is a functional block diagram of the source driver circuit in this embodiment.

In the source driving circuit 4 , the timing control unit 42 is coupled to the interface unit 40 . The interface unit 40 provides the first clock signal CKVA to the timing control unit 42 . The timing control unit 42 includes a first clock supply unit 420 , a second clock supply unit 422 , an oscillator 424 and a multiplexed output unit 428 . The first clock supply unit 420 and the second clock supply unit 422 are both coupled to the multiplexing output unit 428 . The first clock supply unit 420 is also coupled to the interface unit 40 . The second clock supply unit 422 is also coupled to the oscillator 424 .

The first clock providing unit 420 is used for providing the first clock signal CKVA of the interface unit 40 to the multiplexing output unit 428 . The oscillator 424 is used for simulating the first clock signal CKVA to generate the second clock signal CKVB to the second clock supply unit 422 , and the second clock supply unit 422 provides the multiplex output unit 428 .

When the multiplexed output unit 428 receives the electrostatic discharge detection signal ESDS, the multiplexed output unit 428 selectively outputs the first clock signal CKVA or the second clock signal CKVB according to whether the electrostatic discharge detection signal ESDS is enabled. For example, when the electrostatic discharge detection signal ESDS is activated, it means that an electrostatic discharge event is detected. At this time, the multiplexed output unit 428 will switch from originally providing the first clock signal CKVA to providing the second clock signal CKVB. When the electrostatic discharge detection signal ESDS ends, it means that the electrostatic discharge event has ended. At this time, the multiplexed output unit 428 switches from providing the second clock signal CKVB to providing the first clock signal CKVA again.

It should be noted that, since the second clock signal CKVB is obtained by the oscillator 424 by simulating the first clock signal CKVA, the second clock signal CKVB should be the same as the first clock signal CKVA, but not the same as the first clock signal CKVA. limit.

As shown in FIG. 6A , conventionally, since the source driver circuit will stop transmitting the clock signal CKV to the gate driver circuit during the detection of the ESD event, it is easy to cause the circuit signal matching to be misaligned (for example, the output of the gate driver circuit). The gate output signals G(N+1)~G(N+3) correspond to wrong data signals respectively), which causes the display screen of the display panel to shake.

On the contrary, as shown in FIG. 6B , since the source driving circuit 4 of the present invention still outputs the analog second clock signal CKVB to the gate driving circuit during the detection of the ESD event, the circuit signal can be effectively avoided. When the misalignment occurs, the gate output signal output by the gate driving circuit can correspond to the correct data signal, so that the display screen of the display panel will not vibrate.

In addition, since the source driver circuit can also be provided with a line buffer or a frame buffer, the present invention proposes corresponding circuit countermeasures for the above situations as follows.

Referring to FIG. 7 , in one embodiment, it is assumed that the source driving circuit SIC includes a line buffer with 6 lines. Therefore, considering the line buffer, the shielding start point SP of the output enable signal OE will be more than The Nth line LN when the ESD event is detected is further delayed by 6 lines, that is, the shielding start point SP of the output enable signal OE in this embodiment will be the (N+6)th line L(N +6), but not limited to this.

Next, please refer to FIG. 8A and FIG. 8B , in another embodiment, it is assumed that the source driver circuit SIC includes a frame buffer. Therefore, when the frame buffer is considered, when ESD is detected in the Nth frame FN When the event occurs, the shading start point SP of the output enable signal OE in this embodiment will start from the next frame, that is, from the (N+1)th frame F(N+1), but not limited to this .

Compared with the prior art, the source driver circuit of the present invention can output a high impedance (HiZ) data signal to the display panel or output an analog clock signal to the gate driver when an electrostatic discharge event is detected, so as to effectively Traditionally, it can avoid the abnormality of the display screen such as flickering screen and flickering line due to factors such as the liquid crystal characteristics of the display panel or the misalignment of circuit signals. In addition, the present invention also considers the case where the source driver circuit has a line buffer or a frame buffer and proposes corresponding circuit countermeasures, so it is also applicable.

1: Display device DA: Display Panel SIC: source driver circuit GIC: Gate Driver Circuit SDA: source data signal GP: gate drive signal OE: output enable signal CKV: clock signal 2: source driver circuit 20: Electrostatic discharge detection unit 22: Output enable unit 24: Data output unit GD: gate drive circuit PL: Display Panel ESDS: Electrostatic Discharge Detection Signal t1~t19: time DIN: input data VS: field sync signal DE: Effective display data strobe signal BK: blank space FN~F(N+4): frame HiZ: High impedance GL1~GL2: gate drive line SL1~SL2: source drive line VCOM: common voltage VGL: low potential M11, M12, M21, M22: Transistor switches CS: Capacitor 4: Source driver circuit 40: Interface unit 42: Timing control unit 420: The first clock supply unit 422: Second clock supply unit 424: Oscillator 428: Multiplex output unit CKVA: the first clock signal CKVB: The second clock signal SDA1~SDA7: source data signal G(N)~G(N+3): Gate output signal 6: Display device LN: Nth line L(N+6): Line (N+6) SP: Mask start point

The accompanying drawings of the present invention are described as follows: FIG. 1 is a schematic diagram illustrating a display device including a display panel, a source driving circuit and a gate driving circuit. FIG. 2 is a functional block diagram of a source driver circuit according to a preferred embodiment of the present invention. 3 is a timing diagram of the source driver circuit outputting a high-impedance (HiZ) data signal and providing an output enable signal to enable the gate driver circuit to emit a low-level gate driver signal when an ESD event is detected. FIG. 4 is a schematic diagram of eliminating the leakage path in the display panel through a high impedance (HiZ) data signal and a low potential gate driving signal. FIG. 5 is a functional block diagram of a source driving circuit according to another preferred embodiment of the present invention. FIG. 6A is a conventional timing diagram of misalignment of circuit signals due to the absence of a clock signal during the detection of an ESD event. FIG. 6B is a timing diagram of the present invention when an analog clock signal exists even when an ESD event is detected, so as to effectively avoid misalignment of circuit signals. FIG. 7 is a schematic diagram illustrating that, in the case where the source driver circuit has a line buffer with 6 lines, the start of the masking of the output enable signal is 6 lines later than the detection of the ESD event. FIGS. 8A and 8B are schematic diagrams illustrating the start of the masking of the output enable signal in the next frame after an ESD event is detected when the source driver circuit has a frame buffer.

2: source driver circuit

20: Electrostatic discharge detection unit

22: Output enable unit

24: Data output unit

GD: gate drive circuit

PL: Display Panel

ESDS: Electrostatic Discharge Detection Signal

OE: output enable signal

SDA: source data signal

GP: gate drive signal

Claims (13)

A source drive circuit is coupled to a display panel and a gate drive circuit, the source drive circuit includes: an electrostatic discharge detection unit for providing an electrostatic discharge detection signal when an electrostatic discharge event is detected an output enable unit, coupled to the electrostatic discharge detection unit and the gate drive circuit, for providing an output enable signal to the gate drive circuit according to the electrostatic discharge detection signal, so that the gate drive circuit The gate drive signal sent to the display panel is at a low level; and a data output unit, coupled to the electrostatic discharge detection unit and the display panel, is used for providing a high impedance data signal to the display panel according to the electrostatic discharge detection signal The display panel causes the picture displayed by the display panel to conform to a specific specification. The source driving circuit of claim 1, wherein the display panel is a vehicle display panel and the source driving circuit is a vehicle source driving circuit. The source driving circuit as claimed in claim 1, wherein the specific specification is that when the electrostatic discharge event occurs, the screen displayed on the display panel cannot exhibit the phenomenon of screen flashing or flashing lines. The source driving circuit of claim 1, wherein the display panel includes a plurality of pixels and each pixel includes a transistor switch and a capacitor, and a gate of the transistor switch is coupled to the gate at a low potential driving signal, the capacitor is coupled to one end of the transistor switch and the other end of the transistor switch is coupled to the data signal with high impedance, so as to eliminate the leakage path of the charge stored in the capacitor and prevent the display panel from displaying A splash screen appears on the screen. The source driver circuit of claim 1, wherein the output enable signal can be Continue until the end of the current frame or continue to the next frame or multiple frames, so that the display panel continues to display the picture of the previous frame. The source driving circuit of claim 1, wherein the source driving circuit comprises a frame buffer, and if the electrostatic discharge event occurs in the Nth frame, the output enable signal is in the (Nth frame) +1) The frame starts with the gate drive signal at a low level, where N is a positive integer. A source drive circuit is coupled to a display panel and a gate drive circuit, the source drive circuit includes: a data output unit, coupled to the display panel, for providing data signals to the display panel; an electrostatic discharge detector a detection unit for providing an electrostatic discharge detection signal when an electrostatic discharge event is detected; an output enabling unit, coupled to the electrostatic discharge detection unit and the gate driving circuit, for detecting the electrostatic discharge according to the The detection signal provides an output enable signal to the gate drive circuit, so that the gate drive signal sent by the gate drive circuit to the display panel is at a low level; and a timing control unit is coupled to the electrostatic discharge detection unit and The gate driving circuit is used for switching a first clock signal originally provided to the gate driving circuit to a second clock signal when the electrostatic discharge detection signal is activated, and when the electrostatic discharge detection signal ends When switching back to the first clock signal, the picture displayed on the display panel conforms to a specific specification. The source drive circuit of claim 7, wherein the display panel is a vehicle display panel and the source drive circuit is a vehicle source drive circuit. The source driver circuit as claimed in claim 7, wherein the specific specification is that when the electrostatic discharge event occurs, the screen displayed on the display panel cannot appear flickering or flickering. elephant. The source driving circuit of claim 7, wherein when the electrostatic discharge detection signal is not activated, the gate driving circuit receives the first clock signal and when the electrostatic discharge detection signal is activated, the The gate driving circuit can still receive the second clock signal, so as to prevent the gate output signal output by the gate driving circuit from corresponding to the wrong data signal, which causes the picture displayed on the display panel to vibrate. The source driving circuit of claim 7, wherein the timing control unit comprises: a first clock supply unit for supplying the first clock signal; a second clock supply unit for supplying the first clock signal two clock signals; and a multiplex output unit, respectively coupled to the electrostatic discharge detection unit, the first clock supply unit and the second clock supply unit, for selectively according to the electrostatic discharge detection signal Output the first clock signal or the second clock signal. The source driving circuit of claim 11, wherein the timing control unit further comprises an oscillator coupled to the second clock supply unit for simulating the first clock signal to generate the second clock signal to The second clock supply unit. The source driver circuit of claim 7, wherein the source driver circuit comprises a line buffer of K lines, and if the electrostatic discharge event occurs on the Nth line of a display frame, the output The enable signal starts to make the gate driving signal at a low level after the (N+K)th line of the display frame, wherein N and K are positive integers.

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