TWI761297B - Package structure - Google Patents
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- TWI761297B TWI761297B TW110141035A TW110141035A TWI761297B TW I761297 B TWI761297 B TW I761297B TW 110141035 A TW110141035 A TW 110141035A TW 110141035 A TW110141035 A TW 110141035A TW I761297 B TWI761297 B TW I761297B
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Abstract
Description
本揭露是有關一種封裝結構。The present disclosure relates to a package structure.
隨著積體電路(IC)製造技術日益進步,帶動封裝製程需求提高,目前應用於晶片封裝領域的技術繁多,例如扇出型面板級封裝(Fan-out Panel level Package;FOPLP)、晶片尺寸構裝(Chip Scale Package;CSP)、晶片直接貼附封裝(Direct Chip Attached;DCA)或多晶片模組封裝(Multi-Chip Module;MCM)等覆晶型態的封裝模組,或將晶片立體堆疊整合為三維積體電路(3D IC)的晶片堆疊技術等。With the continuous advancement of integrated circuit (IC) manufacturing technology, the demand for packaging processes has increased. Currently, there are many technologies applied in the field of chip packaging, such as Fan-out Panel level Package (FOPLP), chip size structure Flip-chip packaging modules such as Chip Scale Package (CSP), Direct Chip Attached (DCA) or Multi-Chip Module (MCM), or three-dimensional stacking of chips Chip stacking technology integrated into three-dimensional integrated circuits (3D IC), etc.
然而,因用於晶片接合的絕緣板體的材料特性,在封裝製程的熱處理期間(Thermal cycle)容易因熱脹冷縮現象而造成絕緣板體變形,致使其內的線路層移位。雖然可於絕緣板體的一側黏貼支撐板,但仍可能在移除支撐板後發生絕緣板體翹曲(Warpage)變形,進而導致後續焊錫凸塊無法有效或精確接合於線路層上。However, due to the material properties of the insulating plate body used for die bonding, the insulating plate body is easily deformed due to thermal expansion and contraction during the thermal cycle of the packaging process, resulting in displacement of the circuit layers in the insulating plate body. Although the support board can be pasted on one side of the insulating board, warpage deformation of the insulating board may still occur after the support board is removed, so that subsequent solder bumps cannot be effectively or accurately bonded to the circuit layer.
本揭露之一技術態樣為一種封裝結構。One technical aspect of the present disclosure is a package structure.
根據本揭露之一些實施方式,一種封裝結構包括載體及至少一互連結構。載體具有至少一第一通孔與複數個第二通孔。第一通孔靠近載體的中央區,第二通孔靠近載體的周圍區,且第一通孔的截面積小於第二通孔的總截面積。互連結構位於載體上,且覆蓋第一通孔與第二通孔。According to some embodiments of the present disclosure, a package structure includes a carrier and at least one interconnect structure. The carrier has at least one first through hole and a plurality of second through holes. The first through hole is close to the central area of the carrier, the second through hole is close to the peripheral area of the carrier, and the cross-sectional area of the first through hole is smaller than the total cross-sectional area of the second through hole. The interconnect structure is located on the carrier and covers the first through hole and the second through hole.
在一些實施方式中,上述第一通孔的直徑與每一第二通孔的直徑相同,且第一通孔的密度小於第二通孔的密度。In some embodiments, the diameter of the first through holes is the same as the diameter of each second through hole, and the density of the first through holes is smaller than the density of the second through holes.
在一些實施方式中,上述第一通孔的直徑大於每一第二通孔的直徑,且第一通孔的數量小於第二通孔的數量。In some embodiments, the diameter of the first through holes is larger than the diameter of each of the second through holes, and the number of the first through holes is smaller than the number of the second through holes.
在一些實施方式中,上述第一通孔的直徑小於每一第二通孔的直徑,且第一通孔的數量小於第二通孔的數量。In some embodiments, the diameter of the first through holes is smaller than the diameter of each second through hole, and the number of the first through holes is smaller than the number of the second through holes.
在一些實施方式中,上述載體具有複數個第一通孔,且第一通孔的總截面積小於第二通孔的總截面積。In some embodiments, the carrier has a plurality of first through holes, and the total cross-sectional area of the first through holes is smaller than the total cross-sectional area of the second through holes.
在一些實施方式中,上述每一第一通孔的直徑小於每一第二通孔的直徑,且第一通孔的數量大於第二通孔的數量。In some embodiments, the diameter of each of the first through holes is smaller than the diameter of each of the second through holes, and the number of the first through holes is greater than the number of the second through holes.
在一些實施方式中,上述封裝結構更包括複數個金屬填充材。金屬填充材分別位於第一通孔的第一部分與第二通孔的第一部分中,其中第一通孔的第二部分與第二通孔的第二部分中無金屬填充材。In some embodiments, the above-mentioned package structure further includes a plurality of metal fillers. The metal filling material is respectively located in the first part of the first through hole and the first part of the second through hole, wherein there is no metal filling material in the second part of the first through hole and the second part of the second through hole.
在一些實施方式中,上述第一通孔的第二部分的總截面積小於第二通孔的第二部分的總截面積。In some embodiments, the total cross-sectional area of the second portion of the first through hole is smaller than the total cross-sectional area of the second portion of the second through hole.
在一些實施方式中,上述封裝結構包括兩個互連結構,且載體位於兩互連結構之間。兩互連結構各包括介電層與位在介電層中的導線。兩互連結構的兩導線分別電性連接金屬填充材其中一者的兩端。In some embodiments, the package structure described above includes two interconnect structures, and the carrier is located between the two interconnect structures. Each of the two interconnect structures includes a dielectric layer and conductive lines located in the dielectric layer. The two wires of the two interconnecting structures are respectively electrically connected to two ends of one of the metal fillers.
在一些實施方式中,上述金屬填充材的熱膨脹係數與載體不同。In some embodiments, the thermal expansion coefficient of the metal filler material is different from that of the carrier.
在一些實施方式中,上述金屬填充材的熱膨脹係數大於載體的熱膨脹係數。In some embodiments, the thermal expansion coefficient of the metal filler is greater than the thermal expansion coefficient of the carrier.
在一些實施方式中,上述封裝結構更包括複數個金屬填充材。金屬填充材分別位於第一通孔與第二通孔的第一部分中,其中第二通孔的第二部分中無金屬填充材。In some embodiments, the above-mentioned package structure further includes a plurality of metal fillers. The metal filling material is respectively located in the first through hole and the first part of the second through hole, wherein there is no metal filling material in the second part of the second through hole.
在一些實施方式中,上述封裝結構更包括複數個金屬填充材。金屬填充材分別位於第一通孔與第二通孔中,其中在第一通孔中的金屬填充材的直徑小於在第二通孔中的金屬填充材的直徑。In some embodiments, the above-mentioned package structure further includes a plurality of metal fillers. The metal filling material is respectively located in the first through hole and the second through hole, wherein the diameter of the metal filling material in the first through hole is smaller than the diameter of the metal filling material in the second through hole.
在一些實施方式中,上述互連結構包括介電層與位在介電層中的導線。第二通孔其中一者與導線在垂直方向上重疊。In some embodiments, the interconnect structure described above includes a dielectric layer and wires located in the dielectric layer. One of the second through holes overlaps the wire in the vertical direction.
在一些實施方式中,上述第一通孔與第二通孔彼此平行。In some embodiments, the first through hole and the second through hole are parallel to each other.
在本揭露上述實施方式中,由於載體具有靠近載體中央區的至少一第一通孔與靠近載體周圍區的複數個第二通孔,且第一通孔的截面積小於第二通孔的總截面積,因此當載體與其上的不同材料層(例如互連結構)的熱膨脹係數不同而發生翹曲(Warpage)時,第一通孔與第二通孔的設計可改變載體的翹曲量,使載體的周圍區有較多的空間縮進而減少載體的翹曲量。如此一來,可避免互連結構在形成期間、接合(Bonding)晶片期間、模製(Molding)晶片期間因熱處理而導致其內的導線移位,使焊錫凸塊可精確接合於互連結構的導線上。In the above-mentioned embodiments of the present disclosure, since the carrier has at least one first through hole near the central area of the carrier and a plurality of second through holes near the peripheral area of the carrier, and the cross-sectional area of the first through hole is smaller than the total of the second through holes Therefore, when the thermal expansion coefficient of the carrier and the different material layers (such as interconnect structures) on the carrier are different and warpage occurs, the design of the first through hole and the second through hole can change the warpage of the carrier, The amount of warpage of the carrier is reduced by allowing more space for the surrounding area of the carrier to shrink. In this way, the displacement of the wires in the interconnect structure due to heat treatment during the formation, bonding of the wafer, and the molding of the wafer can be avoided, so that the solder bumps can be accurately bonded to the interconnect structure. on the wire.
以下揭示之實施方式內容提供了用於實施所提供的標的之不同特徵的許多不同實施方式,或實例。下文描述了元件和佈置之特定實例以簡化本案。當然,該等實例僅為實例且並不意欲作為限制。此外,本案可在各個實例中重複元件符號及/或字母。此重複係用於簡便和清晰的目的,且其本身不指定所論述的各個實施方式及/或配置之間的關係。The embodiments disclosed below provide many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present case. Of course, these examples are merely examples and are not intended to be limiting. In addition, reference numerals and/or letters may be repeated in various instances herein. This repetition is for brevity and clarity, and does not in itself specify the relationship between the various embodiments and/or configurations discussed.
諸如「在……下方」、「在……之下」、「下部」、「在……之上」、「上部」等等空間相對術語可在本文中為了便於描述之目的而使用,以描述如附圖中所示之一個元件或特徵與另一元件或特徵之關係。空間相對術語意欲涵蓋除了附圖中所示的定向之外的在使用或操作中的裝置的不同定向。裝置可經其他方式定向(旋轉90度或以其他定向)並且本文所使用的空間相對描述詞可同樣相應地解釋。Spatially relative terms such as "below," "below," "lower," "above," "above," and the like may be used herein for convenience of description to describe The relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
第1圖至第3圖繪示根據本揭露一實施方式之形成封裝結構100的各步驟的剖面圖。同時參閱第1圖與第2圖,載體110具有相對的頂面112與底面114。載體110的材料可為玻璃,但並不以此為限。載體110具有中央區C與圍繞中央區C的周圍區P。載體110可經鑽孔製程而形成至少一第一通孔O1與複數個第二通孔O2,使載體110的物理結構改變以改善翹曲。第一通孔O1與第二通孔O2貫穿載體110的頂面112與底面114,且第一通孔O1與第二通孔O2可彼此平行。此外,第一通孔O1靠近載體110的中央區C,第二通孔O2靠近載體110的周圍區P,且第一通孔O1的截面積小於第二通孔O2的總截面積。第一通孔O1與第二通孔O2的位置與數量可根據不同的抗翹曲需求而改變,第2圖僅為示例。1 to 3 are cross-sectional views illustrating various steps of forming the
參閱第3圖,在第一通孔O1與第二通孔O2形成後,可於載體110的頂面112上形成覆蓋第一通孔O1與第二通孔O2的互連結構120,便可得到封裝結構100。互連結構120可包括介電層122與位在介電層122中的導線124。在本實施方式中,導線124可以為重佈線(Redistribution line;RDL),其材料可以為銅或其他適合的金屬,用以傳遞電訊號;介電層122的材料可以為環氧樹脂(Epoxy)或聚醯亞胺(Polyimide;PI),但並不用以限制本揭露。第二通孔O2可與第二個導線124在垂直方向上重疊,或與介電層122與在垂直方向上重疊,並不用以限制本揭露。Referring to FIG. 3 , after the first through holes O1 and the second through holes O2 are formed, an
具體而言,由於載體110具有靠近載體110之中央區C的至少一第一通孔O1與靠近載體110之周圍區P的複數個第二通孔O2,且第一通孔O1的截面積小於第二通孔O2的總截面積,因此當載體110與其上的不同材料層(例如互連結構120)的熱膨脹係數不同而發生翹曲(Warpage)時,第一通孔O1與第二通孔O2的設計可改變載體110的翹曲量,使載體110的周圍區P有較多的空間縮進而減少載體110的翹曲量。如此一來,可避免互連結構120在形成期間、接合(Bonding)晶片期間、模製(Molding)晶片期間因熱處理而導致其內的導線124移位,使焊錫凸塊可精確接合於互連結構120的導線124上。Specifically, since the
在本實施方式中,第一通孔O1的直徑d1與每一第二通孔O2的直徑d2可以是相同的,也就是第一通孔O1與第二通孔O2的大小相同。此外,第一通孔O1的密度小於第二通孔O2的密度。這樣的設計,第一通孔O1的截面積可小於第二通孔O2的總截面積。In this embodiment, the diameter d1 of the first through hole O1 and the diameter d2 of each second through hole O2 may be the same, that is, the first through hole O1 and the second through hole O2 have the same size. In addition, the density of the first through holes O1 is smaller than that of the second through holes O2. In this design, the cross-sectional area of the first through hole O1 may be smaller than the total cross-sectional area of the second through hole O2.
應瞭解到,已敘述過的元件連接關係、材料與功效將不再重複贅述,合先敘明。在以下敘述中,將說明其他形式的封裝結構。It should be understood that the connection relationships, materials and functions of the components already described will not be repeated, but will be described first. In the following description, other forms of packaging structures will be described.
第4圖至第10圖繪示根據本揭露多個實施方式之封裝結構100a~100g的剖面圖。參閱第4圖,其與3圖實施方式不同的地方在於封裝結構100a除了具有互連結構120外,還包括互連結構120a。互連結構120、120a分別位於載體110的頂面112與底面114。也就是說,載體110位於兩互連結構120、120a之間。FIGS. 4 to 10 are cross-sectional views of
參閱第5圖,封裝結構100b包括載體110與互連結構120,其與3圖實施方式不同的地方在於封裝結構100b的載體110的第一通孔O1的直徑d1大於每一第二通孔O2的直徑d2,且第一通孔O1的數量小於第二通孔O2的數量。在本實施方式中,第一通孔O1的數量為1,第二通孔O2的數量為5,但並不用以限制本揭露。這樣的設計,第一通孔O1的截面積可小於第二通孔O2的總截面積,使封裝結構100b的載體110的周圍區P有較多的空間縮進而減少載體110的翹曲量。Referring to FIG. 5, the
參閱第6圖,其與5圖實施方式不同的地方在於封裝結構100c除了具有互連結構120外,還包括互連結構120a。互連結構120、120a分別位於載體110的頂面112與底面114。也就是說,封裝結構100c的載體110位於兩互連結構120、120a之間。Referring to FIG. 6 , the difference from the embodiment shown in FIG. 5 is that the
參閱第7圖,封裝結構100d包括載體110與互連結構120。封裝結構100d的載體110具有複數個第一通孔O1,且第一通孔O1的總截面積小於第二通孔O2的總截面積。此外,每一第一通孔O1的直徑d1小於每一第二通孔O2的直徑d2,且第一通孔O1的數量大於第二通孔O2的數量。在本實施方式中,第一通孔O1的數量為4,第二通孔O2的數量為3,但並不用以限制本揭露。這樣的設計,第一通孔O1的總截面積可小於第二通孔O2的總截面積,使封裝結構100d的載體110的周圍區P有較多的空間縮進而減少載體110的翹曲量。Referring to FIG. 7 , the
參閱第8圖,其與7圖實施方式不同的地方在於第8圖的封裝結構100e除了具有互連結構120外,還包括互連結構120a。互連結構120、120a分別位於載體110的頂面112與底面114。也就是說,封裝結構100e的載體110位於兩互連結構120、120a之間。此外,在本實施方式中,第一通孔O1的數量為6,第二通孔O2的數量為5,且第一通孔O1的總截面積小於第二通孔O2的總截面積。Referring to FIG. 8 , the difference from the embodiment in FIG. 7 is that the
參閱第9圖,封裝結構100f包括載體110與互連結構120。互連結構120位於載體110的頂面112。封裝結構100f的載體110具有至少一第一通孔O1與複數個第二通孔O2,且第一通孔O1的總截面積小於第二通孔O2的總截面積。此外,第一通孔O1的直徑d1小於每一第二通孔O2的直徑d2,且第一通孔O1的數量小於第二通孔O2的數量。在本實施方式中,第一通孔O1的數量為1,第二通孔O2的數量為3,但並不用以限制本揭露。這樣的設計,第一通孔O1的截面積可小於第二通孔O2的總截面積,使封裝結構100f的載體110的周圍區P有較多的空間縮進而減少載體110的翹曲量。Referring to FIG. 9 , the
參閱第10圖,其與9圖實施方式不同的地方在於封裝結構100g除了具有互連結構120外,還包括互連結構120a。互連結構120、120a分別位於載體110的頂面112與底面114。也就是說,封裝結構100g的載體110位於兩互連結構120、120a之間。此外,在本實施方式中,第二通孔O2的數量為5,且第一通孔O1的截面積小於第二通孔O2的總截面積。Referring to FIG. 10 , the difference from the embodiment shown in FIG. 9 is that the
第11圖至第13圖繪示根據本揭露另一實施方式之形成封裝結構100h的各步驟的剖面圖。同時參閱第11圖與第12圖,載體110可經鑽孔製程而形成第一通孔O11與複數個第二通孔O21、O22。第一通孔O11靠近載體110的中央區C,第二通孔O21、O22靠近載體110的周圍區P。第一通孔O11與第二通孔O21、O22的位置與數量可根據不同的抗翹曲需求而改變,第11圖僅為示例。FIGS. 11 to 13 are cross-sectional views illustrating steps of forming a
在一實施方式中,載體110具有單一第一通孔O11與不同直徑的第二通孔O21、O22。第二通孔O21的直徑d4大於第二通孔O22的直徑d3,第一通孔O11的直徑d1與第二通孔O22的直徑d3大致相同。在後續製程中,可填充複數個金屬填充材130於第一通孔O11與第二通孔O21中,使金屬填充材130位於第一通孔O11與第二通孔O21中(即第二通孔的第一部分中),且第二通孔O22中(即第二通孔的第二部分中)無金屬填充材。這樣的設計,可讓第一通孔O11無金屬填充材130的截面積(例如0)小於第二通孔O21、O22無金屬填充材130的總截面積(例如第二通孔O22的總截面積),使載體110的熱膨脹係數(Coefficient of thermal expansion;CTE)改變以改善翹曲。In one embodiment, the
在本實施方式中,金屬填充材130的材料可以為銅、鋁或其他適當的金屬,且金屬填充材130的熱膨脹係數與載體110不同,例如金屬填充材130的熱膨脹係數大於載體110的熱膨脹係數。In this embodiment, the material of the
在另一實施方式中,載體110還具有第一通孔O12(如虛線所示)。第一通孔O12具有直徑d1且靠近載體110的中央區C。金屬填充材130位於第一通孔O11與第二通孔O21中(即第一通孔的第一部分與第二通孔的第一部分中),且第一通孔O12與第二通孔O22中(即第一通孔的第二部分與第二通孔的第二部分中)無金屬填充材130。這樣的設計,可讓第一通孔O11、O12無金屬填充材130的總截面積(例如第一通孔O12的截面積)小於第二通孔O21、O22無金屬填充材130的總截面積(例如第二通孔O22的總截面積),使載體110的熱膨脹係數改變以改善翹曲。In another embodiment, the
參閱第13圖,在第12圖的結構形成後,可於載體110的頂面112上形成覆蓋第一通孔O11、O12、第二通孔O21、O22與金屬填充材130的互連結構120,便可得到封裝結構100h。在本實施方式中,互連結構120的導線124可與金屬填充材130在垂直方向重疊且電性連接,但並不用以限制本揭露。Referring to FIG. 13 , after the structure of FIG. 12 is formed, an
第14圖至第16圖繪示根據本揭露多個實施方式之封裝結構100i~100k的剖面圖。參閱第14圖,其與13圖實施方式不同的地方在於封裝結構100i除了具有互連結構120外,還包括互連結構120a。互連結構120、120a分別位於載體110的頂面112與底面114。也就是說,封裝結構100i的載體110位於兩互連結構120、120a之間。此外,在本實施方式中,第一通孔O11與右側第二通孔O21中無金屬填充材130,且右側第二通孔O22中填充金屬填充材130。這樣的設計,可讓無金屬填充材130之第一通孔O11的截面積小於無金屬填充材130之第二通孔O21、O22的總截面積,使載體110的熱膨脹係數改變以改善翹曲。在本實施方式中,兩互連結構120、120a的兩導線124可分別電性連接金屬填充材130的兩端而導通。FIGS. 14 to 16 are cross-sectional views of
參閱第15圖,封裝結構100j包括載體110、複數個金屬填充材130與互連結構120。載體110具有至少一第一通孔O1與複數個第二通孔O2。金屬填充材130分別位於第一通孔O1與第二通孔O2中,也就是說,所有第一通孔O1與第二通孔O2皆填入金屬填充材130。在本實施方式中,第一通孔O1與其內的金屬填充材130具有直徑d1,第二通孔O2與其內的金屬填充材130具有直徑d2,且在第一通孔O1中的金屬填充材130的直徑d1小於在第二通孔O2中的金屬填充材130的直徑d2。這樣的設計,第一通孔O1中的金屬填充材130的截面積可小於第二通孔O2中的金屬填充材130的總截面積,進而減少載體110的翹曲量。互連結構120位於載體110的頂面112上,互連結構120的導線124可與第二通孔O2在垂直方向重疊。Referring to FIG. 15 , the
參閱第16圖,其與15圖實施方式不同的地方在於封裝結構100k還包括互連結構120a,且第二通孔O2與金屬填充材130的數量較多。互連結構120、120a分別位於載體110的頂面112與底面114。也就是說,封裝結構100k的載體110位於兩互連結構120、120a之間。這樣的設計,第一通孔O1中的金屬填充材130的截面積可小於第二通孔O2中的金屬填充材130的總截面積,進而減少載體110的翹曲量。Referring to FIG. 16, the difference from the embodiment shown in FIG. 15 is that the
前述概述了幾個實施方式的特徵,使得本領域技術人員可以更好地理解本揭露的態樣。本領域技術人員應當理解,他們可以容易地將本揭露用作設計或修改其他過程和結構的基礎,以實現與本文介紹的實施方式相同的目的和/或實現相同的優點。本領域技術人員還應該認識到,這樣的等效構造不脫離本揭露的精神和範圍,並且在不脫離本揭露的精神和範圍的情況下,它們可以在這裡進行各種改變,替換和變更。The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
100,100a~100k:封裝結構
110:載體
112:頂面
114:底面
120,120a:互連結構
122:介電層
124:導線
130:金屬填充材
C:中央區
d1,d2,d3,d4:直徑
O1:第一通孔
O11:第一通孔
O12:第一通孔
O2:第二通孔
O21:第二通孔
O22:第二通孔
P:周圍區100,100a~100k: Package structure
110: Carrier
112: top surface
114:
當與隨附圖示一起閱讀時,可由後文實施方式最佳地理解本揭露內容的態樣。注意到根據此行業中之標準實務,各種特徵並未按比例繪製。實際上,為論述的清楚性,可任意增加或減少各種特徵的尺寸。 第1圖至第3圖繪示根據本揭露一實施方式之形成封裝結構的各步驟的剖面圖。 第4圖至第10圖繪示根據本揭露多個實施方式之封裝結構的剖面圖。 第11圖至第13圖繪示根據本揭露另一實施方式之形成封裝結構的各步驟的剖面圖。 第14圖至第16圖繪示根據本揭露多個實施方式之封裝結構的剖面圖。 Aspects of the present disclosure are best understood from the following description when read in conjunction with the accompanying drawings. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIGS. 1 to 3 are cross-sectional views illustrating various steps of forming a package structure according to an embodiment of the present disclosure. 4 to 10 are cross-sectional views illustrating a package structure according to various embodiments of the present disclosure. FIGS. 11 to 13 are cross-sectional views illustrating steps of forming a package structure according to another embodiment of the present disclosure. 14 to 16 are cross-sectional views illustrating a package structure according to various embodiments of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none
100:封裝結構 100: Package structure
110:載體 110: Carrier
112:頂面 112: top surface
114:底面 114: Underside
120:互連結構 120: Interconnect structure
122:介電層 122: Dielectric layer
124:導線 124: Wire
C:中央區 C: Central District
d1,d2:直徑 d1,d2: diameter
O1:第一通孔 O1: first through hole
O2:第二通孔 O2: second through hole
P:周圍區 P: Surrounding area
Claims (15)
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| TW110141035A TWI761297B (en) | 2021-11-03 | 2021-11-03 | Package structure |
| CN202210532501.9A CN114843243B (en) | 2021-11-03 | 2022-05-10 | Packaging structure |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012009473A (en) * | 2010-06-22 | 2012-01-12 | Panasonic Corp | Semiconductor device and manufacturing method of the same |
| JP5609617B2 (en) * | 2010-12-17 | 2014-10-22 | 富士通株式会社 | Electronic component, method for manufacturing the electronic component, electronic device, and method for manufacturing the electronic device |
| US20160255728A1 (en) * | 2015-02-27 | 2016-09-01 | Fujitsu Limited | Semiconductor package, electronic device, and solder mounting method |
| TW201635432A (en) * | 2015-03-23 | 2016-10-01 | 華亞科技股份有限公司 | Semiconductor structure and preparation method thereof |
| TW201707168A (en) * | 2015-03-17 | 2017-02-16 | 東芝股份有限公司 | Semiconductor device and method of manufacturing same |
| CN111354768A (en) * | 2018-12-20 | 2020-06-30 | 乐金显示有限公司 | Display device and equipment for manufacturing the same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433321C (en) * | 2005-07-29 | 2008-11-12 | 三洋电机株式会社 | Circuit board and circuit device using the same |
| US20080217748A1 (en) * | 2007-03-08 | 2008-09-11 | International Business Machines Corporation | Low cost and low coefficient of thermal expansion packaging structures and processes |
| KR100965341B1 (en) * | 2007-12-20 | 2010-06-22 | 삼성전기주식회사 | Manufacturing method of printed circuit board |
| CN105514071B (en) * | 2016-01-22 | 2019-01-25 | 中芯长电半导体(江阴)有限公司 | A fan-out chip packaging method and packaging structure |
| US10515899B2 (en) * | 2016-10-03 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure with bump |
| US10573572B2 (en) * | 2018-07-19 | 2020-02-25 | Advanced Semiconductor Engineering, Inc. | Electronic device and method for manufacturing a semiconductor package structure |
| US11069630B2 (en) * | 2018-09-21 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structures and methods for reducing thermal expansion mismatch during integrated circuit packaging |
-
2021
- 2021-11-03 TW TW110141035A patent/TWI761297B/en active
-
2022
- 2022-05-10 CN CN202210532501.9A patent/CN114843243B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012009473A (en) * | 2010-06-22 | 2012-01-12 | Panasonic Corp | Semiconductor device and manufacturing method of the same |
| JP5609617B2 (en) * | 2010-12-17 | 2014-10-22 | 富士通株式会社 | Electronic component, method for manufacturing the electronic component, electronic device, and method for manufacturing the electronic device |
| US20160255728A1 (en) * | 2015-02-27 | 2016-09-01 | Fujitsu Limited | Semiconductor package, electronic device, and solder mounting method |
| TW201707168A (en) * | 2015-03-17 | 2017-02-16 | 東芝股份有限公司 | Semiconductor device and method of manufacturing same |
| TW201635432A (en) * | 2015-03-23 | 2016-10-01 | 華亞科技股份有限公司 | Semiconductor structure and preparation method thereof |
| CN111354768A (en) * | 2018-12-20 | 2020-06-30 | 乐金显示有限公司 | Display device and equipment for manufacturing the same |
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| CN114843243B (en) | 2025-08-15 |
| TW202320274A (en) | 2023-05-16 |
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