TWI759253B - Semiconductor patterning process method and inspection pattern for monitoring semiconductor patterning process - Google Patents

Abstract

The present invention provides a detection pattern for monitoring a semiconductor patterning process, comprising an inner pattern unit with a plurality of process patterns distributed at intervals, an outer pattern unit located outside the inner pattern unit and generally forming a square, and the outer pattern unit is opposite to The first circuit pattern and the second circuit pattern each have the same circuit density, and the line center line of the two first line patterns and the line center line of the two second line patterns intersect at right angles; the at least one line The auxiliary pattern unit is located on at least one side of the outer pattern unit, and has a plurality of auxiliary patterns spaced along the at least one side of the outer pattern unit, and the auxiliary patterns are adjacent to or away from at least one of the bottom sides of the outer pattern unit The lines are not in the same straight line. In addition, the present invention also provides a method for monitoring and adjusting the semiconductor patterning process by the detection pattern.

Description

Semiconductor patterning process method and inspection pattern for monitoring semiconductor patterning process

The present invention relates to a semiconductor manufacturing method and a detection pattern unit for monitoring the semiconductor manufacturing process, in particular to a semiconductor patterning process and a detection pattern unit for monitoring the semiconductor patterning process.

Due to the rapid development of semiconductor process technology, the requirements for key dimensions such as pitch and trench are getting higher and higher. Therefore, in the lamination process, if there is an error in the formed lamination pattern, the characteristics of the fabricated element will not meet expectations. The goal, especially now that the integrated circuit processing technology has progressed to the nanoscale, how to control the precision of the nanoscale structure is even more important. Among them, the critical dimension (Critical Dimension, CD) is used to evaluate the patterning precision of semiconductor patterning processes, such as lithography and etching processes. Therefore, how to monitor and detect the critical dimensions of the build-up patterns generated in the patterning process, so as to monitor each patterning process, and adjust the patterning process based on the monitoring results to improve the process stability, is extremely important in the semiconductor process. Target.

Therefore, one objective of the present invention is to provide a detection pattern for monitoring a semiconductor patterning process.

Therefore, the detection pattern of the present invention includes: an inner pattern unit, an outer pattern unit, and at least one auxiliary pattern unit.

The inner pattern unit has a plurality of process patterns distributed at intervals.

The outer pattern unit is located on the outer side of the inner pattern unit and is generally square, and has two first circuit patterns and two second circuit patterns opposite to each other, the two first circuit patterns and the two second circuit patterns have the same line density, and the line density of the adjacent first line pattern and the second line pattern can be the same or different, and the line center connection of the two first line patterns and the two second lines The line center lines of the pattern intersect at right angles.

The at least one auxiliary pattern unit is located on at least one side of the outer pattern unit, and has a plurality of auxiliary patterns spaced along the at least one side of the outer pattern unit, and the auxiliary patterns are adjacent to or away from at least one of the outer pattern units. The lines connecting the bottom edges are not in the same straight line.

In addition, another object of the present invention is to provide a semiconductor patterning process method for optimizing the semiconductor patterning process.

Therefore, the semiconductor patterning process method of the present invention includes a selection step and a first comparison step.

The selecting step is to obtain an image of a detection pattern formed on a substrate after at least one patterning process, wherein the detection pattern is the pattern as described above.

The first comparison step is to compare the image of the detection pattern with a preset data to obtain a plurality of difference information between the image of the detection pattern and the preset pattern, wherein the preset data is a A preset pattern corresponding to the detection pattern, or a preset value related to the detection pattern.

In addition, another object of the present invention is to provide a semiconductor patterning process method for optimizing the semiconductor patterning process.

Therefore, the semiconductor patterning process method of the present invention includes a selection step, a first comparison step, and an adjustment parameter selection step.

The selecting step is to obtain an electron microscope image of a detection pattern formed on a substrate after at least one patterning process.

The first comparison step is to compare the electron microscope image of the detection pattern with a preset data to obtain a plurality of difference information between the image of the detection pattern and the preset data, wherein the preset data includes an electron microscope preset pattern corresponding to the electron microscope image of the detection pattern, the first comparison step is to generate a pair of bits from at least one corresponding position of the electron microscope image of the detection pattern and the electron microscope preset pattern, respectively Connecting line segments, aligning the alignment line segments and adjusting at least one of the electron microscope image of the detection pattern and the electron microscope preset pattern equally, until the alignment line segments are coincident with each other A comparison is made to obtain such difference information.

The adjustment parameter selection step is to select a process parameter corresponding to the difference information from a database storing a plurality of process parameters according to the difference information, and obtain at least one corresponding process adjustment parameter accordingly.

The effect of the present invention is: through the design of the detection pattern and using the difference information between the image of the detection pattern obtained after the measurement patterning process and the corresponding preset data. By using the detection pattern with the auxiliary pattern units as the detection of the patterning process, the captured pattern range can be more clearly distinguished. After that, the corresponding process adjustment parameters can be obtained through other steps and fed back to the next patterning process or re-engineering process, so that the overall process result can be optimized.

The semiconductor patterning process method of the present invention can be used to monitor or optimize the patterning process. It mainly obtains the image of the detection pattern after the patterning process and has a specific design pattern, and the image of the detection pattern with the specific design pattern can be used to make it easier for relevant personnel to view the image of the detection pattern after the process and a preset. Difference information between data. The preset data can be a preset pattern corresponding to the detection pattern, or a preset value related to the detection pattern, and the preset value can be a preset key dimension, radian, area, edge of the detection pattern Position Error (Edge Placement Error, EPE). The difference information may be the critical dimension difference, radian difference, area difference, edge position error difference between the critical dimension of the inspection pattern image during and/or after the process and the default value, or the difference between the inspection pattern and the default value. Critical dimension difference, alignment difference, edge position error (EPE), etc. between the preset patterns. Afterwards, the difference information can be compared with a default value. When the comparison result exceeds the default value, a database corresponding to the difference information can be further selected from a database storing a plurality of adjustment parameters. After adjusting the parameters, the adjustment parameters corresponding to the difference information can be fed back to the patterning process, so as to be used as the process parameter adjustment of the next patterning process or re-engineering process, and the patterning process result can be more optimized. Alternatively, the results obtained after the comparison can be alerted to remind the relevant process personnel, and the patterning process can also be monitored.

The following embodiments are used to illustrate the semiconductor patterning process method of the present invention.

An embodiment of the semiconductor patterning process method of the present invention is performed by a computer system (not shown), the computer system has a central processing unit capable of receiving relevant image data and used for processing calculations, and a display capable of displaying Display unit.

By measuring the detection patterns formed on the same or a different substrate after a patterning process or a re-engineering process. Then, the detection pattern is compared with the corresponding preset data to obtain the position where the process result is greatly different, and then the corresponding at least one process adjustment parameter is obtained through the process parameter data corresponding to the same difference pre-stored in the database , and fed back to the patterning process to adjust the process parameters of the next patterning process, so as to optimize the patterning process.

Referring to FIG. 1 , in the aforementioned embodiment of the semiconductor patterning process method of the present invention, the detection pattern 60 for monitoring the patterning process is generated by a standard preset pattern through the patterning process, wherein the The standard preset pattern can be obtained from the image data system format GDSII, the OASIS (Open Artwork System Interchange Standard) image data format, the MEBES format image data, or the mask pattern.

In addition, for this embodiment of the present invention, as the preset pattern 600 to be compared with the detection pattern 60, its structure is also corresponding to the detection patterns 60, and the preset pattern 600 may be obtained from the image data system format GDSII, OASIS, MEBES image data formats, mask patterns, or patterns formed on another semiconductor substrate after the same or different patterning processes, or patterns formed on the semiconductor substrate during the patterning process. In addition, the preset pattern 600 used for comparison and the standard preset pattern used to generate the detection pattern 60 may be from the same or different sources, but have the same pattern.

It should be noted that, due to the influence of various parameters of the patterning process, the detection pattern 60 actually formed on the substrate is compared with the standard preset pattern used for generating the detection pattern 60 and the comparison There may be deviations in various sizes or shapes among the preset patterns 600. Therefore, in order to facilitate the description of the structure and measurement method of the detection pattern 60, the present case is used to illustrate the detection pattern 60 of this embodiment in the drawings. , is a description of the structure of the standard preset pattern used to generate the detection pattern 60 . The object to be measured by the semiconductor patterning process method of the present application is the image of the detection pattern 60 actually formed on the substrate (eg, wafer or mask) after the patterning process.

Specifically, the detection pattern 60 used in the embodiment of the semiconductor patterning process method of the present invention includes an inner pattern unit 2 , an outer pattern unit 3 , and a plurality of auxiliary pattern units 4 .

The inner pattern unit 2 has a plurality of process inspection patterns 21 distributed at intervals. Wherein, the process inspection patterns 21 are process inspection circuit patterns used for inspection.

The outer pattern unit 3 is located at the outer side of the inner pattern unit 2 , and generally surrounds the inner pattern unit 2 in a square shape. There are two first line patterns 31 and two second line patterns 32 opposite to each other, and each first line pattern 31 has a plurality of first lines 311 arranged at equal intervals along an X direction, and each second line The pattern 32 has a plurality of second lines 321 arranged at equal intervals along a Y direction.

In FIG. 1, the connection lines of the first lines 311 and the second lines 321 adjacent to and away from the bottom edge of the inner pattern unit 2 are respectively located on a straight line L11, L12, and L21, L22, and are adjacent to each other. The two straight lines L11, L12, and L21, L22 on both sides intersect at right angles, and the line density of the first lines 311 and the second lines 321 are different, and the line centers of any two opposite first lines 311 are connected. It is illustrated that the line C31 intersects with the line center connecting line C32 of any two of the second lines 321 at right angles. However, in actual implementation, only the connecting lines of the first lines 311 and the second lines 321 adjacent to the bottom edge of the inner pattern unit 2 may be located on a straight line L11, L21, away from the inner pattern unit 2. The connection lines of the other bottom side of the 2 do not need to be in the same straight line; and the circuit density of the first circuit patterns 31 and the second circuit patterns 32 can also be the same, which is not limited to the pattern shown in FIG. 1 .

The auxiliary pattern units 4 are respectively located on four sides of the outer pattern unit 3 . Each auxiliary pattern unit 4 has a plurality of auxiliary patterns 41 arranged at equal intervals along the corresponding side edge, and the connection lines of the auxiliary patterns 41 adjacent to and away from at least one bottom edge of the outer pattern unit 3 are not the same in a straight line.

In FIG. 1 , the connecting lines of the auxiliary patterns 41 adjacent to and away from the bottom edge of the outer pattern unit 3 are not in the same straight line, but are arranged in a staggered manner. However, referring to FIG. 2 , the auxiliary patterns 41 can also be connected only in a straight line away from the bottom edge of the outer pattern unit 3 and in the same straight line as the connection lines adjacent to the bottom edge of the outer pattern unit 3 , And has the structure shown in Figure 2. That is, as long as the connecting lines of the auxiliary patterns 41 away from the bottom edge of the outer pattern unit 3 are not in the same straight line.

In some embodiments, the auxiliary pattern units 4 may also be arranged in non-equidistant patterns and irregularly arranged patterns, and the auxiliary pattern units 4 may also be formed only on one side of the outer pattern unit 3, or It is located on the opposite two sides or three sides, but not limited to as shown in FIG.

Utilizing the auxiliary pattern units 4 can improve the circuit density uniformity of semiconductor processes (eg, etching, yellow light, thin film, diffusion, CMP, etc.), and can improve the loading effect or proximity effect of the process. In addition, by making the boundary of the auxiliary pattern units 4 non-linear at the boundary far from the outer pattern unit 3, a clear detection pattern boundary can be generated, so as to assist the process of capturing the image of the detection pattern 60 at a time, and further The range of the captured detection pattern 60 is clearly distinguished.

In this embodiment of the semiconductor patterning process method described above, the image of the inspection pattern 60 generated during the patterning process and/or after the patterning process is completed is obtained, and then the image of the inspection pattern 60 is measured to monitor the pattern. The patterning process is adjusted, and the parameters of the next patterning process are adjusted according to the measurement results, so as to optimize the overall process result. The embodiment of the semiconductor patterning process method is specifically described as follows.

Referring to FIG. 3 , the embodiment of the semiconductor patterning process method of the present invention is executed through the computer system, and includes a selection step 51 , a first comparison step 52 , a second comparison step 53 , and an adjustment parameter selection step 54, and a feedback adjustment step 55.

The selecting step 51 is to obtain an image of the detection pattern 60 formed on a substrate after a predetermined pattern according to a standard and a patterning process.

Wherein, the substrate can be a semiconductor wafer, a photomask, a glass substrate, or a substrate with a micron or nanometer size structure, and the patterning process can be a process such as lithography or etching (dry etching, wet etching).

The image of the detection pattern 60 can be a top-view image (as shown in FIG. 1 ) obtained by an image capturing tool such as an optical microscope, an electron microscope (eg, SEM, TEM), or a cross-sectional image obtained after slicing ( 4), and when the imaging tool is a high-resolution electron microscope (eg, HRTEM), the atomic arrangement of the image of the detection pattern 60 can also be observed.

The selecting step 51 is to select an image of the detection pattern 60 formed on the substrate through the same type or different types of patterning processes. Among them, it should be noted that the aforementioned patterning processes of the same type or different types refer to the same type of process, but the process parameters used may be the same or different, for example, both are lithography processes, but the photoresist or Conditions such as reticle can be the same or different.

In this embodiment, the selecting step 51 is to select images of the detection pattern 60 formed on a substrate through two different types of patterning processes. Specifically, the detection pattern 60 is formed by first forming a photoresist pattern on a semiconductor substrate through a yellow light process, and then etching the photoresist pattern to form the detection pattern 60 on the semiconductor substrate.

In addition, in some embodiments, the images of the detection pattern 60 may also be obtained from images generated on the same substrate through different types of patterning processes. For example, an image of a first detection pattern 61 formed on a semiconductor substrate through lithography can be obtained first, and then an image of a first detection pattern 61 formed on a semiconductor substrate can be obtained, and then the first detection pattern 61 can be used to perform etching, and an etched pattern can be formed on the semiconductor substrate. The image of the second detection pattern 62 obtained by the manufacturing process.

Alternatively, the images of the detection pattern 60 can also be images formed on different semiconductor substrates through the same type of patterning process (eg, a lithography process) but with the same or different process parameters. For example, in other embodiments, the detection pattern 60 may also be two photoresist patterns (ADI) or two etching patterns (AEI) formed by using the same photoresist and different masks to form different substrates; Or two photoresist patterns (ADI) or two etching patterns (AEI) are formed on different substrates using different photoresists and the same mask.

That is to say, whether the detection pattern 60 , the first detection pattern 61 and/or the second detection pattern 62 ) formed by the same type or different types of patterning processes, it is ultimately desirable to obtain the same pattern as the subsequent pattern. The preset pattern 600 used for comparison is substantially the same pattern.

Next, the first comparison step 52 is performed, and the detection pattern 60 is compared with a predetermined data to obtain a plurality of difference information between the detection pattern 60 and the predetermined data. Wherein, the preset data is a preset pattern corresponding to the image of the detection pattern 60 , or a preset value related to the detection pattern 60 , and the preset value may be a preset key size of the detection pattern 60 , at least one of area, radian, and edge position error. The difference information includes at least one of critical dimension difference, alignment error difference, and edge position error between the image of the detection pattern 60 and the preset pattern, or the image of the detection pattern 60 and the preset value at least one of the critical dimension difference, area, radian, and edge position error.

Referring to FIG. 5 , in this embodiment, the image of the detection pattern 60 obtained in the selection step 51 is obtained through lithography and etching processes and formed on a semiconductor substrate, and has the pattern shown in FIG. 1 . and the preset data is a preset pattern 600 corresponding to the detection pattern 60 as an example. Therefore, the first comparison step 52 is to obtain the detection pattern after the patterning process. The pattern 60 is compared with the preset pattern 600 to obtain a plurality of difference information between the detection pattern 60 and the preset data as an example.

Continuing to refer to FIG. 5 , when the first comparison step 52 is performed, the image of the detection pattern 60 and the outer pattern unit 3 of the preset pattern 600 can be used as the alignment basis, respectively, from the image of the detection pattern 60 and the outer pattern unit 3 of the detection pattern 60 . At least one corresponding position of the outer pattern unit 3 of the preset pattern 600 generates alignment line segments along at least one direction (X direction or Y direction). In this embodiment, alignment lines are generated along the X direction and the Y direction respectively. Take the bit connection line segment as an example, then, adjust at least one of the image of the detection pattern 60 and the preset pattern 600 to make the alignment line segments coincide with each other, and then measure and compare the inner patterns The contour difference of the unit 2 is obtained to obtain the difference information of the image of the detection pattern 60 and the process detection patterns 21 of the preset pattern 600 at different positions. The difference information may include a critical dimension error, an alignment error, and an edge position error between the image of the detection pattern 60 and the predetermined pattern 600 .

In addition, the first comparison step 52 can also display the superimposed contour images of the detection pattern 60 and the preset pattern 600 which are compared with each other through the display unit (not shown) of the computer, for the user to use View.

It should be noted that, whether it is the detection pattern 60 formed after the actual patterning process is completed, or the detection pattern (represented by the first detection pattern 61 and the second detection pattern 62 ) formed during the patterning process, or The preset patterns 600 that are preset for comparison have substantially the same pattern. Therefore, in actual implementation, the first detection pattern 61 , the second detection pattern 62 , and the detection pattern 60 obtained respectively during or after the patterning process can also be selected, and one of them can be selected as the default The image 600 for comparison; or the detection pattern 60 , or the first detection pattern 61 and the second detection pattern 62 are respectively compared with the preset pattern 600 , and the desired pattern can also be obtained. Compare results.

In some embodiments, the first comparison step 52 can be used to form photoresist patterns (ADI) of different substrates (such as the first detection pattern 61 ) by using the same mask and different photoresists (such as the first detection pattern 61 ), or The etching pattern (AEI) (such as the second inspection pattern 62) can also be used to evaluate the photoresist used in the patterning process; and the same photoresist, different masks/or different optical advanced correction modes ( OPC model) and photoresist patterns (ADI) or etching patterns (AEI) formed on different substrates, the photomask and optical compensation correction mode used can be further evaluated, and the related materials, components, Optical compensation corrections provide additional evaluation information.

In other implementations, the first comparison step 52 may also be to use two photoresist patterns (ADI) respectively formed under different lithography process parameters, and use one of the photoresist patterns as the default. Patterns 600 are compared, and evaluation information related to lithography process conditions can also be obtained.

In addition, in some embodiments, the first comparison step 52 may also include two etching patterns (AEIs) respectively formed under different etching process parameters, and one of the etching patterns is used as the predetermined pattern 600 for comparison, the evaluation information related to the etching deviation can be obtained.

In other embodiments, the first comparison step 52 may also be to compare the photoresist pattern (ADI) formed during the patterning process and the etching pattern (AEI) formed after etching, and compare one of the The pattern is compared as the predetermined pattern 600, and by comparing the difference information obtained between the photoresist pattern and the etching pattern, evaluation information about the optimization of the etching process can be obtained.

In addition, it should be noted that, in this embodiment, the preset data is a preset pattern 600 that is preset with the same pattern as the detection pattern 60 as an example for comparison. However, in actual implementation, the preset data It is assumed that the data can also be a preset value related to the detection pattern 60 , and the preset value can be, for example, the preset critical dimension, area, radian of the process detection patterns 21 of the inner pattern unit 2 of the detection pattern 60 . , and at least one of edge position errors.

Then, a second comparison step 53 can be performed, and the difference information is compared with a preset value to obtain a plurality of comparison results.

In addition, it should be noted that when the first comparison step 52 uses different images to be compared, the first comparison step 52 can directly measure the difference between the images by overlapping the different images in addition to the above-mentioned In addition, the pixel number PXn (Pixel number) of different images (such as the image of the first detection pattern 61, the image of the second detection pattern 62, and/or the preset pattern 600) can also be measured separately, or It is to measure at least one pitch P ( Pitch, line+space) to get the corresponding pitch size measurement value. After that, the pitch size measurement value obtained by measuring the image of the first detection pattern 61 and the image of the second detection pattern 62 can be used, or the pixel value or the pitch size of the preset pattern 600 can be used The first detection can also be obtained by performing a ratio operation between the preset value and the pitch size measurement value or the number of pixels measured from the image of the first detection pattern 61 and/or the image 62 of the second detection pattern 62 The critical dimension difference between the image of the pattern 61 and the image of the second detection pattern 62 , or the difference between the image of the first detection pattern 61 and/or the image of the second detection pattern 62 and the predetermined pattern 600 Critical dimension differences.

Then, the second comparison step 53 is performed, and the difference information is compared with a preset value to obtain a plurality of comparison results. The preset value may be a process allowable value or a standard value set by the user.

Since the results actually obtained in the patterning process will be affected by different process parameters, there are some differences. Therefore, through the first comparison step 52, the detection pattern 60 and the pre-production pattern actually generated after the patterning process are obtained. After setting the difference information of the corresponding process detection patterns 21 between the patterns 600 at different positions, the second comparison step 53 can be further performed to compare the difference information with the corresponding preset values respectively, Alternatively, after adjusting the difference information by an equal amount, the adjusted value is compared with the default value. When the difference information between the process detection patterns 21 , or the adjusted value after the difference information is adjusted by the same amount exceeds the preset value, it means that the current patterning process parameters need to be adjusted, and the process can be carried out. The adjustment parameter selects step 54 .

In the adjustment parameter selection step 54, when the comparison result between any difference signal and the preset value exceeds the preset value in the second comparison step 53, a plurality of process parameters (such as the process temperature) are stored in a , time and other parameters) database, select the process parameter data corresponding to the difference information, and obtain corresponding at least one process adjustment parameter accordingly. Wherein, the database can be internal keyed in the computer system, or stored in the cloud, and read through the computer system.

For example, with the process parameters stored in the database as shown in Table 1 below, the preset pattern (represented by IF in Table 1) that is preset before the process corresponds to different patterning processes (Table 1). In Table 1, Step1~Step3 represents the three different patterning processes of lithography, dry etching and wet etching) of multiple parameters (such as temperature, time, etc., in Table 1, P-A1~P-A3, P-B1~ P-B3, P-C1~P-C3 represent the temperature parameters of each patterning process), and the detection patterns generated by different patterning temperature conditions (IF-1~IF-3 represent the temperature parameters obtained after different process parameters) detection pattern). Table 1 only takes three sets of parameters and the patterning process results corresponding to the three processes as an example. However, in actual implementation, the process parameters stored in these databases have more sets and more diverse processes and processes depending on requirements. Relevant process parameter combination.

Table 1 Step1 Step2 Step3 Detection pattern IF P-A1 P-A2 P-A3 IF-1 P-B1 P-B2 P-B3 IF-2 P-C1 P-C2 P-C3 IF-3

That is to say, when any comparison result in the second comparison step 53 exceeds the preset value, for example, when the image of the detection pattern 60 obtained through the wet etching process is compared with the preset pattern 600 If the critical dimension is larger than the preset pattern 600, the adjustment parameter selection step 54 can select the wet etching process temperature corresponding to the reduced critical dimension from the database as the temperature adjustment parameter of the critical dimension of the wet etching process; or The temperature adjustment parameter suitable for the deviation of the critical dimension is obtained through calculation (eg, interpolation) by using the change result of the wet etching process temperature relative to the critical dimension in the selected database.

Finally, through the feedback adjustment step 55 , the process adjustment parameters corresponding to the difference information can be fed back to the patterning process, so as to adjust the process parameters of the next patterning process or re-engineering process, so as to monitor and compare the process parameters. The pattern 60 is detected, and the patterning process parameters are adjusted accordingly to optimize the overall patterning process.

Wherein, after the above-mentioned steps are compared, the target used for process adjustment may be a pattern or a value, such as the key dimension (line), line spacing (space), and hole (via, hole) ( CD), angle, thickness, or rounding.

In addition, in some embodiments, it is not necessary to perform the second comparison step 53, but directly select the corresponding data obtained through the first comparison step 52 from the database after the first comparison step 52. Process parameters of the difference information, and obtain corresponding process adjustment parameters accordingly.

Alternatively, in some embodiments, the second comparison step 53 can also be implemented after the adjustment parameter selection step 54 . That is, after the first comparison step 52, the adjustment parameter selection step 54 is performed first, and the process parameters corresponding to the equivalent difference information are directly selected from the database, and the corresponding process adjustment parameters are obtained accordingly, and then, The second comparing step 53 is then performed to compare the process adjustment parameters obtained through the difference information with a preset value. The preset value may be a process allowable value or a standard value set by the user. When any one of the process adjustment parameters exceeds the preset value, indicating that the process has a large deviation, the feedback adjustment step 55 can be performed, and the process adjustment parameter obtained from the difference information is fed back to the patterning process for the next pattern. The process parameters of the chemical process or the re-engineering process are adjusted; when the comparison result of any of the process adjustment parameters and the preset value is within a range of the preset value, it means that the process deviation is extremely small, and it is not necessary to adjust the process parameters. Feedback the process adjustment parameters.

Referring to FIG. 6 , in some embodiments, the semiconductor patterning process method may further include a warning step 56 .

The warning step 56 is to issue a warning signal when the equidistant information obtained by the second comparing step 53 exceeds the preset value, wherein the warning signal can be a sound or an image signal.

In addition, when the first comparison step 52 is performed by comparing the image of the detection pattern 60 with the superimposed outline image of the preset pattern 600 , the display unit can be used to display the image of the detection pattern 60 and the image of the preset pattern 600 , when the iso-difference information obtained by the second comparison step 53 exceeds the preset value, the warning step 56 can issue a warning signal and/or mark the detection pattern 60 The position where the difference between the superimposed contour image and the superimposed contour image after the alignment of the preset pattern 600 exceeds the preset value is used to remind the user and allow the user to check.

In other embodiments, the semiconductor patterning process method may only perform the selecting step 51 , the first comparing step 52 , the second comparing step 53 , and the warning step 56 . By comparing the difference between the detection pattern 60 and the preset pattern 600 generated during the patterning process, and when the difference exceeds the preset value, the relevant personnel are reminded to correct the process conditions in real time, so that the pattern can be more stable and optimized. chemical process.

Or, referring to FIG. 4, in some embodiments, when the image of the detection pattern 60 obtained in the selecting step 51 is an electron microscope image obtained after a patterning process is formed on the substrate and sliced ( For example, a TEM image), the first comparison step 52 may be to generate a pair of bit-connected line segments from the electron microscope image of the detection pattern 60 and the corresponding position of the electron microscope preset pattern 600, and then use X, Y Adjusting at least one of the electron microscope image of the detection pattern 60 and the electron microscope preset pattern by an equal amount in the direction, until the alignment line segments overlap each other, and then compare them to obtain the difference information . Wherein, the alignment line segment may be a length of a pitch dimension P or an integer multiple of the length of the pitch dimension P.

That is to say, when the images used for mutual comparison each have image patterns arranged along the X direction or the Y direction (as shown in FIG. 2 , the detection pattern 60 for comparison has both along the X direction and The first and second line patterns 31, 32) distributed in the Y direction, and the alignment line segments extending along the X direction and the Y direction can be generated through the image pattern respectively, then the first During the comparison step 52, the same or different scale adjustments can be performed on the X direction and the Y direction respectively, so that the alignment line segments in the X direction and the Y direction respectively overlap; and when used for comparison The image has only a pattern in a single direction (for example, when the image used for comparison is an electron microscope image with only a line pattern along the X direction as shown in Figure 4, or when the image used for comparison has only a pattern of lines along the X direction As shown in FIG. 2, when the first circuit patterns 31 or the second circuit patterns 32 are opposite to each other), and only the alignment line segments extending in a single direction can be generated by these patterns, then the When the first comparison step 52 is performed, the X direction and the Y direction are adjusted by equal amounts at the same time, so that the alignment line segments overlap each other.

In addition, the preset data can also be a preset value related to the TEM image of the detection pattern 60, and the preset value can be a key size value, a pitch size P, a thickness, a radian, a line width, and a unit pixel value at least one of them. The difference information can also be obtained by using the electron microscope image of the detection pattern 60 and this.

Then, at least one of the aforementioned second comparison step 53 , the adjustment parameter selection step 54 , the feedback adjustment step 55 , and the warning step 56 can be selectively executed again, by obtaining the correlation through the TEM image. The difference information is obtained accordingly at least one process adjustment parameter, which is used as a process parameter adjustment basis for the subsequent patterning process or rework.

In addition, when the atomic arrangement can be observed in the TEM image, the size of the atom is also used as the basis for measurement and calculation, and the relevant deviation information results are obtained.

To sum up, through the design of the detection pattern 60, the present invention utilizes the difference between the detection pattern 60 (the first detection pattern 61 and the second detection pattern 62) after the measurement patterning process and a preset data, Then, error information between the detection pattern 60 and the preset data is obtained. When the error information exceeds the preset value after comparison, the process adjustment parameters that can correspondingly improve the process differences can be obtained by calculating or selecting from the preset database for the next patterning process. Or rework the process parameter adjustment to optimize the overall process result, so the object of the present invention can indeed be achieved.

However, the above are only examples of the present invention, and should not limit the scope of the present invention. Any simple equivalent changes and modifications made according to the scope of the application for patent of the present invention and the content of the patent specification are still within the scope of the present invention. within the scope of the invention patent.

60: Detection pattern 61: The first detection pattern 62: Second detection pattern 2: Inner pattern unit 21: Process inspection pattern 3: Outer pattern unit 31: The first line pattern 311: First Line 32: Second circuit pattern 321: Second line L11, L12, L21, L22: Straight line C31, C32: line center connection 4: Auxiliary pattern unit 41: Auxiliary pattern 600: Preset Pattern 51: Selection steps 52: The first comparison step 53: Second alignment step 54: Adjust parameter selection steps 55: Feedback adjustment steps 56: Warning steps PXn: draw prime numbers P: pitch X, Y: direction

Other features and effects of the present invention will be clearly presented in the embodiments with reference to the drawings, wherein:

FIG. 1 is a schematic diagram illustrating a detection pattern unit used in this embodiment;

FIG. 2 is a schematic diagram illustrating another structural aspect for the auxiliary patterns 41;

3 is a text flow diagram illustrating the embodiment of the semiconductor patterning process method of the present invention;

4 is a schematic cross-sectional view illustrating the cross-sectional structure image of the detection pattern 60 obtained in the selection step 51;

FIG. 5 is a schematic diagram illustrating the first comparison step 52 of this embodiment; and

FIG. 6 is a text flow diagram illustrating another implementation aspect of the embodiment.

51: Selection steps

52: The first comparison step

53: Second alignment step

54: Adjust parameter selection steps

55: Feedback adjustment steps

Claims (19)

An inspection pattern for monitoring a patterning process, comprising: an inner pattern unit with a plurality of process inspection patterns distributed at intervals; An outer pattern unit, located on the outer side of the inner pattern unit and generally in a square shape, has two first circuit patterns and two second circuit patterns opposite to each other, the two first circuit patterns and the two second circuit patterns The patterns have the same line density, and the line densities of the adjacent first line patterns and the second line patterns can be the same or different, and the line centers of the two first line patterns are connected to the two second line patterns. The lines connecting the centers of the lines of the line pattern intersect at right angles; and At least one auxiliary pattern unit, located on at least one side of the outer pattern unit, has a plurality of auxiliary patterns spaced along the at least one side of the outer pattern unit, and the auxiliary patterns are adjacent to or away from at least one of the outer pattern units. The lines connecting the bottom edges are not in the same straight line. The detection pattern of claim 1, wherein the connection lines of the first circuit patterns and the second circuit patterns adjacent to and away from at least one bottom edge of the inner pattern unit are located on a straight line, and are adjacent to each other. The connecting lines of the bottom edges of the first circuit pattern and the second circuit pattern intersect at right angles. The detection pattern according to claim 1, wherein the detection pattern has a plurality of auxiliary pattern units corresponding to a plurality of sides of the outer pattern unit. The detection pattern of claim 1, wherein the connecting lines of the auxiliary patterns away from the bottom edge of the outer pattern unit are not in the same straight line. A semiconductor patterning process method for optimizing the semiconductor patterning process, comprising: a selecting step of obtaining an image of a detection pattern formed on a substrate after at least one patterning process, wherein the detection pattern is as described in claim 1; and a first comparison step, comparing the image of the detection pattern with a preset data to obtain a plurality of difference information between the image of the detection pattern and the preset data, wherein the preset data is a A preset pattern corresponding to the detection pattern, or a preset value related to the detection pattern. The semiconductor patterning process method according to claim 5, further comprising a second comparison step of comparing the difference information with a predetermined value, wherein the predetermined value is a process allowable value or a user's own a set standard value. The semiconductor patterning process method of claim 6, further comprising a warning step implemented after the second comparison step, when the difference information exceeds a predetermined value, a warning signal is issued. The semiconductor patterning process method according to claim 6, wherein the first comparison step further displays a superimposed contour image of the image of the detection pattern and the predetermined pattern after alignment, and the semiconductor patterning process method, Also includes a warning step implemented after the second comparison step, the warning step is when the difference information exceeds a predetermined value, then mark the superimposed contour image difference after alignment exceeds the predetermined value. Location. The semiconductor patterning process method according to any one of claims 5 to 8, further comprising an adjustment parameter selection step performed after the first comparison step, the adjustment parameter selection step is based on the difference information, in A process parameter corresponding to the equivalent difference information is selected from a database storing a plurality of process parameters, and corresponding at least one process adjustment parameter is obtained accordingly. The semiconductor patterning process method of claim 9, further comprising a feedback adjustment step performed after the adjustment parameter selection step, the feedback adjustment step is to feed back the at least one process adjustment parameter to the patterning process, so as to perform the following steps: Process parameter adjustment for a patterning process. The semiconductor patterning process method according to claim 5, wherein the selecting step is to obtain images of a plurality of detection patterns formed on the same or different substrates through two patterning processes of the same type or different types, respectively. , and use one of the detection patterns as the preset pattern. The semiconductor patterning process method as claimed in claim 10, wherein the selecting step is to obtain images of the detection patterns formed on different substrates through two patterning processes of the same type. The semiconductor patterning process method of claim 10, wherein the selecting step is to obtain images of a first detection pattern and a second detection pattern formed on the same substrate through two different types of patterning processes , and the second detection pattern is obtained after the first detection pattern is generated through a first patterning process, and then the first detection pattern is passed through a second patterning process. The semiconductor patterning process method of claim 5, wherein the predetermined value is at least one of a critical dimension, area, radian, and edge position error of the inspection pattern, and the difference information includes an image of the inspection pattern At least one of the critical dimension difference, the alignment error difference, and the edge position error between the preset pattern, or the critical dimension difference, area, radian, and edge position between the image of the detection pattern and the preset value at least one of the errors. The semiconductor patterning process method of claim 5, wherein the preset data is a preset pattern corresponding to the detection pattern, and the first comparison step is obtained from images of the detection pattern and the preset pattern, respectively. At least one corresponding position of the outer pattern unit generates a pair of connected line segments, aligns the paired line segments and adjusts at least one of the image of the detection pattern and the preset pattern to make the paired connection lines The line segments are overlapped with each other, and the difference information is obtained by comparing the contour difference between the image of the detection pattern and the preset pattern. The semiconductor patterning process method according to claim 5, wherein the preset pattern is obtained from image data system GDSII, OASIS, MEBES format image data, mask pattern, or according to the image data system GDS, OASIS , The image of the MEBES format image data forms a pattern of another semiconductor substrate, or an image image during the patterning process, and the image of the detection pattern can be a top-view pattern or a cross-sectional pattern. The semiconductor patterning process method as claimed in claim 9, wherein the adjustment parameter selection step is to select the corresponding process parameters from the database, or select the corresponding process parameters from the database and perform operations, and then The corresponding adjustment parameters of the process are obtained. A semiconductor patterning process method for optimizing the semiconductor patterning process, comprising: a selecting step of obtaining an electron microscope image of a detection pattern formed on a substrate after at least one patterning process; a first comparison step, comparing the electron microscope image of the detection pattern with a preset data to obtain a plurality of difference information between the image of the detection pattern and the preset data, wherein the preset data includes an electron microscope preset pattern corresponding to the electron microscope image of the detection pattern, the first comparison step is to generate a pair of bits from the electron microscope image of the detection pattern and the electron microscope preset pattern at least one corresponding position Connecting line segments, aligning the alignment line segments and adjusting at least one of the electron microscope image of the detection pattern and the electron microscope preset pattern equally, until the alignment line segments are coincident with each other make comparisons to obtain such discrepancies; and In an adjustment parameter selection step, a process parameter corresponding to the difference information is selected from a database storing a plurality of process parameters according to the difference information, and corresponding at least one process adjustment parameter is obtained accordingly. The semiconductor patterning process method as claimed in claim 18, further comprising a second comparison step of comparing the difference information with a preset value, wherein the preset value is a process allowable value or a user's own A set standard value, when any difference information exceeds the corresponding preset value, at least one of the corresponding position is marked and a warning signal is issued.

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