TWI758901B - Display device - Google Patents

Abstract

A display device includes a substrate, a scan line, a first signal line, a first insulating layer, a second signal line, a transistor and a pixel electrode. The scan line is disposed on the substrate. The first signal line is disposed on the substrate. The first insulating layer is disposed on the first signal line and has an opening. The second signal line is disposed on the first insulating layer. The second signal line is electrically connected to the first signal line through the opening. The transistor is electrically connected to the scan line and the first signal line. The pixel electrode is electrically connected to the transistor and has a first side adjacent to the scan line and a second side opposite to the first side. The opening is adjacent to the second side and away from the first side.

Description

display device

The present disclosure relates to an electronic device, and more particularly, to a display device capable of reducing the resistance of signal lines.

With the vigorous development of electronic products, the display technology applied to electronic products is also constantly improving. Electronic devices for display continue to improve towards larger and higher resolution displays.

The present disclosure provides a display device which can reduce the resistance value of the signal line or increase the driving capability of the panel.

The display device of the present disclosure includes a substrate, a scan line, a first signal line, a first insulating layer, a second signal line, a transistor, and a pixel electrode. The scan lines are arranged on the substrate. The first signal line is arranged on the substrate. The first insulating layer is disposed on the first signal line and has an opening. The second signal line is disposed on the first insulating layer. The second signal line is electrically connected to the first signal line through the opening. The transistor is electrically connected to the scan line and the first signal line. The pixel electrode is electrically connected to the transistor and has a first side adjacent to the scan line and a second side opposite to the first side. The opening is adjacent to the second side and away from the first side.

Based on the above, in the display device of the embodiment of the present disclosure, since the second signal line is disposed on the first signal line, and the second signal line can be electrically connected to the first signal line through the opening of the first insulating layer, the present invention The display device of the embodiment can utilize double-layered signal lines (ie, the first signal line and the second signal line) for signal transmission. Therefore, in the display device of the present embodiment, the resistance of the signal lines can be reduced by the arrangement of the double-layered signal lines (ie, the first signal line and the second signal line), so as to increase the panel driving capability and facilitate high frequency (eg greater than 90Hz) drive.

In order to make the above-mentioned features and advantages of the present disclosure more obvious and easy to understand, the following embodiments are given and described in detail in conjunction with the accompanying drawings as follows.

The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in order to facilitate readers' understanding and to simplify the drawings, the drawings in the present disclosure only depict a part of an electronic device. And specific elements in the drawings are not drawn according to actual scale. In addition, the number and size of each element in the figures are for illustration only, and are not intended to limit the scope of the present disclosure.

In the following description and claims, the words "comprising" and "including" are open-ended words, so they should be interpreted as meaning "including but not limited to...".

It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or directly connected to the other element or layer Hereto another element or layer, or there is an intervening element or layer in between (indirect case). In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present.

Although the terms first, second, third . . . may be used to describe various constituent elements, the constituent elements are not limited by the terms. This term is only used to distinguish a single constituent element from other constituent elements in the specification. The same terms may not be used in the claims, but replaced by first, second, third, . . . in the order in which the elements are recited in the claims. Therefore, in the following description, the first constituent element may be the second constituent element in the claims.

In some embodiments of the present disclosure, terms related to bonding and connection, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, There are other structures located between these two structures. And the terms of joining and connecting can also include the case where both structures are movable, or both structures are fixed. Furthermore, the term "coupled" includes any direct and indirect means of electrical connection.

In the present disclosure, the measurement method of length and width can be measured by using an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, any two values or directions used for comparison may have certain errors.

The electronic device of the present disclosure may include, but is not limited to, a display device, an antenna device, a sensing device, a touch display, a curved display, or a free shape display . The electronic device may be a bendable or flexible electronic device. The electronic device may include, for example, light emitting diode (LED), liquid crystal, fluorescence, phosphor, other suitable display medium, or a combination of the foregoing, but not limited to limit. The light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), sub-millimeter light-emitting diodes (mini LEDs), micro-LEDs Polar body (micro LED) or quantum dot (quantum dot, QD) light emitting diode (QLED, QDLED), or other suitable materials or any combination of the above, but not limited thereto. The display device may include, for example, but not limited to, a tiled display device. The antenna device may be, for example, a liquid crystal antenna, but not limited thereto. The antenna device may include, for example, but not limited to, an antenna splicing device. It should be noted that, the electronic device can be any arrangement and combination of the foregoing, but not limited to this. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device or a splicing device. Hereinafter, the present disclosure will be described with a display device, but the present disclosure is not limited thereto.

It should be noted that, in the following embodiments, features in several different embodiments may be replaced, recombined, and mixed to complete other embodiments without departing from the spirit of the present disclosure. As long as the features of the various embodiments do not violate the spirit of the invention or conflict with each other, they can be mixed and matched arbitrarily.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

FIG. 1A is a schematic top view of a display device according to an embodiment of the disclosure. FIG. 1B is a schematic cross-sectional view of the display device of FIG. 1A along the section line A-A'. FIG. 1C is a schematic cross-sectional view of the display device of FIG. 1A along the section line B-B'. For the sake of clarity and convenience of description of the drawings, FIG. 1A omits to illustrate some elements in the display device, for example, the opening GIa, the opening GIb, the opening 172a and the opening 172b are omitted, but not limited thereto.

1A , 1B and 1C at the same time, the display device 100 of this embodiment includes a substrate 110 , a scan line 120 , a first signal line 130 , a first insulating layer 140 , a second signal line 131 , a transistor 150 and pixels electrode 160. In this embodiment, the substrate 110 can be, for example, a flexible substrate, a rigid substrate, or a combination thereof. For example, the material of the substrate 110 may include glass, quartz, sapphire (sapphire), ceramics, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (polyethylene terephthalate) terephthalate, PET), other suitable substrate materials, or a combination of the foregoing, but not limited thereto.

The transistor 150 is disposed on the substrate 110, and the transistor 150 includes a gate GE, an insulating layer 173, a part of the gate insulating layer GI, a semiconductor layer SE, a source SD1 and a drain SD2, but not limited thereto. In this embodiment, the gate insulating layer GI has openings GIa and GIb to expose a part of the semiconductor layer SE. In some embodiments, the material of the source electrode SD1 and/or the drain electrode SD2 may include a transparent conductive material or a non-transparent conductive material, such as indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, tin oxide, metal materials (eg, aluminum, molybdenum, copper, silver, etc.), other suitable materials, or combinations thereof, but not limited thereto. In some embodiments, the material of the semiconductor layer SE may include amorphous silicon, low temperature polysilicon (LTPS), metal oxide (eg, indium gallium zinc oxide IGZO), other suitable materials, or a combination of the above, but Not limited to this. In this embodiment, although the gate GE of the transistor 150 is a top gate structure, the present disclosure is not limited to this, that is, in other embodiments, the gate of the transistor may also be a bottom gate structure.

The scan lines 120 are disposed on the substrate 110 , the first signal lines 130 are disposed on the substrate 110 , and the scan lines 120 and the first signal lines 130 intersect each other. Since the scan line 120 can be electrically connected to the gate electrode GE of the transistor 150, and the first signal line 130 can be electrically connected to the source electrode SD1 of the transistor 150, the transistor 150 can pass through the gate electrode GE and the source electrode respectively. SD1 is electrically connected to the scan line 120 and the first signal line 130 . In some embodiments, the materials of the scan lines 120 and the first signal lines 130 may include, for example, molybdenum (Molybdenum, Mo), titanium (titanium, Ti), tantalum (tantalum, Ta), niobium (niobium, Nb), hafnium ( hafnium, Hf), nickel (nickel, Ni), chromium (chromium, Cr), cobalt (cobalt, Co), zirconium (zirconium, Zr), tungsten (tungsten, W), aluminum (aluminum, Al), copper ( copper, Cu), silver (argentum, Ag), other suitable metals, or alloys or combinations of the above materials, but not limited thereto.

In this embodiment, the display device 100 further includes a buffer layer 170 , a shielding layer 171 and a dielectric layer 172 . The buffer layer 170 and the shielding layer 171 are disposed between the transistor 150 and the substrate 110 , and the shielding layer 171 is disposed corresponding to the gate GE. The dielectric layer 172 is disposed between the source electrode SD1 (or the drain electrode SD2 ) and the gate insulating layer GI to cover the gate electrode GE and the gate insulating layer GI. The dielectric layer 172 has openings 172a and 172b, wherein the opening 172a communicates with the opening GIa to expose a part of the semiconductor layer SE, and the opening 172b communicates with the opening GIb to expose a part of the semiconductor layer SE. In some embodiments, the buffer layer 170 , the dielectric layer 172 and the gate insulating layer GI may also be a single layer or other multi-layer structures, and may include organic materials, inorganic materials or combinations thereof, but not limited thereto . The shielding layer 171 may be, for example, a metal material or other light shielding material, and in some embodiments, the display device 100 may not be provided with the shielding layer 171 .

In this embodiment, the source electrode SD1 and the drain electrode SD2 are respectively disposed on the dielectric layer 172 . Part of the source electrode SD1 can also be filled in the opening 172a of the dielectric layer 172 and the opening GIa of the gate insulating layer GI, so that the source electrode SD1 can be electrically connected to the semiconductor layer SE. Part of the drain SD2 can also be filled in the opening 172b of the dielectric layer 172 and the opening GIb of the gate insulating layer GI, so that the drain SD2 can be electrically connected to the semiconductor layer SE.

The first insulating layer 140 is disposed on the first signal line 130 and covers the source SD1 , the drain SD2 and the dielectric layer 172 of the transistor 150 . The first insulating layer 140 and the substrate 110 are respectively disposed on opposite sides of the transistor 150 . The first insulating layer 140 has an opening 141 and an opening 142, wherein the opening 141 exposes a part of the first signal line 130, and the opening 142 exposes a part of the drain electrode SD2. The first insulating layer 140 may also be a single layer or other multi-layer structures, and may include, for example, organic materials, inorganic materials or a combination of the foregoing, but not limited thereto.

The second signal line 131 is disposed on the first insulating layer 140 . Part of the second signal line 131 can also be disposed in the opening 141 of the first insulating layer 140 , so that the second signal line 131 can be electrically connected to the first signal line 130 through the opening 141 . The second signal line 131 and the first signal line 130 are respectively located on opposite sides of the first insulating layer 140 . In this embodiment, the material of the second signal line 131 may be the same as or similar to that of the first signal line 130 , and details are not described herein again. In some embodiments, the first signal line 130 and the second signal line 131 may be made of the same or different materials, but not limited thereto.

In addition, in this embodiment, the second signal line 131 is disposed corresponding to the first signal line 130 . The orthographic projection of the second signal line 131 on the substrate 110 at least partially overlaps the orthographic projection of the first signal line 130 on the substrate 110 . In one embodiment, a portion of the first signal line 130 may not overlap with the second signal line 131 . In the top view of the display device 100 (as shown in FIG. 1A ), the maximum width of the first signal line 130 is W1 , the maximum width of the second signal line 131 is W2 , and the maximum width W1 of the first signal line 130 is different from The maximum width W2 of the second signal line 131 . In this embodiment, the maximum width W2 of the second signal line 131 is, for example, greater than or equal to the maximum width W1 of the first signal line 130 , but not limited thereto. In some embodiments, the ratio of the maximum width W2 of the second signal line 131 to the maximum width W1 of the first signal line 130 is, for example, greater than or equal to 0.5 and less than or equal to 2, but not limited thereto. When the ratio of the maximum width W2 of the second signal line 131 to the maximum width W1 of the first signal line 130 is less than 0.5, the resistance of the signal line cannot be significantly reduced. When the ratio of the maximum width W2 of the second signal line 131 to the maximum width W1 of the first signal line 130 is greater than 2, the aperture ratio of the pixels will be significantly reduced. In this embodiment, the maximum width W1 of the first signal line 130 and the maximum width W2 of the second signal line 131 are, for example, measured along the extending direction of the scan line 120 (ie, the direction X).

In this embodiment, the display device 100 further includes a second insulating layer 180 and a third insulating layer 182 . The second insulating layer 180 is disposed on the second signal line 131 to cover the second signal line 131 and the first insulating layer 140 . The second insulating layer 180 and the transistor 150 are respectively disposed on opposite sides of the first insulating layer 140 . The second insulating layer 180 has an opening 181, and the opening 181 communicates with the opening 142 of the first insulating layer 140 to expose a part of the drain electrode SD2. The third insulating layer 182 is disposed on the second insulating layer 180 , so that the third insulating layer 182 and the first insulating layer 140 are respectively disposed on opposite sides of the second insulating layer 180 . The third insulating layer 182 has an opening 183, and the opening 183 communicates with the opening 181 of the second insulating layer 180 and the opening 142 of the first insulating layer 140 to expose part of the drain electrode SD2. In this embodiment, although the second insulating layer 180 is disposed on the second signal line 131, the present disclosure is not limited to this, that is, in other embodiments, the second insulating layer 180 may also be omitted. The third insulating layer 182 is directly disposed on the second signal line 131 . In addition, in the top view of the display device 100 , the outlines of the openings 183 , 181 , 142 and 141 refer to the outlines of the bottoms of the openings 183 , 181 , 142 and 141 , such as rectangles, but not limited thereto. In some embodiments, the contours of the bottoms of the openings 183 , 181 , 142 , 141 can also be circular, oval, trapezoidal, square, etc., and the above contours may include slight edge deformation and rounded corners at the apex. It should be known that the openings of other embodiments may also have the above-mentioned outlines in the top view, but are not limited thereto.

The pixel electrode 160 is disposed on the third insulating layer 182 and between the fourth insulating layer 184 and the third insulating layer 182 . Part of the pixel electrode 160 can also be disposed in the opening 183 , the opening 181 and the opening 142 , so that the pixel electrode 160 can be electrically connected to the transistor 150 through the opening 183 , the opening 181 and the opening 142 and the drain SD2 . In some embodiments, in the top view of the display device 100, the pixel electrodes 160 and 160' may partially overlap with the second signal line 131, but not limited thereto. The second insulating layer 180 and the third insulating layer 182 may also be a single layer or other multi-layer structures, and may include organic materials, inorganic materials or combinations thereof, but not limited thereto. The material of the pixel electrode 160 may include, for example, a transparent conductive material, but is not limited thereto.

In this embodiment, in the top view of the display device 100 , the direction perpendicular to the extending direction of the scan lines 120 is defined as the direction Y (ie, perpendicular to the direction X). Next, as shown in FIG. 1A , in the top view of the display device 100 , the pixel electrodes 160 correspond to the scan lines 120 (for example, the scan lines 120 can provide a voltage, so that the first signal lines 130 and/or the second signal lines 131 are The voltage determines whether to charge the pixel electrode 160 or not), and the pixel electrode 160' corresponds to the scan line 120' (for example, the scan line 120' can provide a voltage, so that the first signal line 130 and/or the second signal line 131 can be based on the voltage determine whether to charge the pixel electrode 160 ′), and the pixel electrode 160 is adjacent to the pixel electrode 160 ′ in the direction Y; the pixel electrode 160 has a first side 161 adjacent to the scan line 120 and a first side 161 opposite to the first side 161 The second side 162, and the pixel electrode 160' has a first side 161' adjacent to the scan line 120' and a second side 162' opposite to the first side 161'. In other embodiments, the first sides 161 , 161 ′ and the second sides 162 , 162 ′ of the pixel electrodes 160 , 160 ′ may be non-linear edges (eg, have arc or concave edges). The two sides 162 are two separated sides, and the first side 161 is adjacent to the scan line 120 relative to the second side 162 , and the second side 162 is far away from the scan line 120 relative to the first side 161 ; the first side 161 ′ and the second side 161 The side 162' is two separated sides, and the first side 161' is adjacent to the scan line 120' relative to the second side 162', and the second side 162' is far from the scan line 120' relative to the first side 161'. Then, in the direction Y, the distance between the scan line 120 and the first side 161 of the pixel electrode 160 may be smaller than the distance between the scan line 120 and the second side 162 of the pixel electrode 160 . In the top view of the display device 100, the first side 161 of the pixel electrode 160 and the first side 161' of the pixel electrode 160' adjacent along the direction Y face each other, and the second side 162 of the pixel electrode 160 and The second sides 162' of adjacent pixel electrodes 160' along the direction Y face away from each other. For example, the distance between the first side 161 of the pixel electrode 160 and the first side 161' of the pixel electrode 160' along the direction Y is smaller than the distance between the second side 162 of the pixel electrode 160 and the second side 162' of the pixel electrode 160' along the direction Y Y distance. That is, the pixel electrode 160 and the pixel electrode 160' are arranged in a back-to-back manner.

In addition, in the top view of the display device 100 , the opening 141 of the first insulating layer 140 may be adjacent to the second side 162 of the pixel electrode 160 and away from the first side 161 of the pixel electrode 160 . That is, in the direction Y, the distance between the opening 141 of the first insulating layer 140 and the second side 162 of the pixel electrode 160 may be smaller than the distance between the opening 141 of the first insulating layer 140 and the first side 161 of the pixel electrode 160 distance. Therefore, by arranging the pixel electrode 160 and the pixel electrode 160 ′ in a back-to-back manner, and disposing the opening 141 of the first insulating layer 140 adjacent to the second side 162 of the pixel electrode 160 , it is possible to The contact holes of the first signal line 130 and the second signal line 131 (ie, the opening 141 of the first insulating layer 140 ) are arranged away from the area of the transistor 150 . Therefore, the manufacturing process of the contact holes of the first signal line 130 and the second signal line 131 can be simplified, the process yield can be improved, and the reduction of the aperture ratio of the region of the transistor 150 can be avoided.

In this embodiment, the display device 100 may optionally further include a fourth insulating layer 184 , a common electrode 185 and a fifth insulating layer 186 . The fourth insulating layer 184 is disposed on the pixel electrode 160 and/or in the opening 183 of the third insulating layer 182 . The common electrode 185 is disposed on the fourth insulating layer 184 and/or in the opening 183 of the third insulating layer 182 , so that the fourth insulating layer 184 is located between the common electrode 185 and the pixel electrode 160 . The fifth insulating layer 186 is disposed between the pixel electrode 160 and the third insulating layer 182 . In this embodiment, the second insulating layer 180 and the fifth insulating layer 186 can reduce the damage probability of the third insulating layer 182 and/or the drain electrode SD2 during the manufacturing process of the display device 100 . However, in some embodiments, the fifth insulating layer 186 can also be omitted, and the pixel electrode 160 is directly disposed on the third insulating layer 182, as shown in FIG. 3B and FIG. 5B . The fourth insulating layer 184 and the fifth insulating layer 186 may also be a single layer or other multi-layer structures, and may include organic materials, inorganic materials or combinations thereof, but not limited thereto. The material of the common electrode 185 may include, for example, a transparent conductive material, but is not limited thereto.

In other embodiments, the common electrode 185 may be disposed between the pixel electrode 160 and the transistor 150 , and the common electrode 185 may include an opening (not shown), and the pixel electrode 160 may be electrically connected through the opening of the common electrode 185 The transistor 150, but the disclosure is not limited thereto.

In short, in the display device 100 of the present embodiment, since the second signal line 131 is disposed on the first signal line 130 , and the second signal line 131 can be electrically connected to the first signal line 131 through the opening 141 of the first insulating layer 140 The signal line 130 thus enables the display device 100 of the present embodiment to use double-layered signal lines (ie, the first signal line 130 and the second signal line 131 ) for signal transmission. Therefore, compared with the conventional high-pixel display device, which has a problem of high resistance due to only a single layer of signal lines, the display device 100 of the present embodiment can use a double layer of signal lines (ie, the first The setting of the signal line 130 and the second signal line 131) reduces the resistance of the signal line to increase the panel driving capability and facilitate high frequency (eg, greater than 90 Hz, but not limited to) driving.

Other examples are listed below for illustration. It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

FIG. 2A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 2B is a schematic cross-sectional view of the display device of FIG. 2A along the section line C-C'. Please refer to FIG. 1B for a schematic cross-sectional view of the display device of FIG. 2A along the section line A-A'. 1A , 1C and FIGS. 2A-2B at the same time, the display device 100 a of this embodiment is substantially similar to the display device 100 of FIGS. 1A and 1C , so the same and similar components in the two embodiments will not be repeated here. The display device 100a of the present embodiment is different from the display device 100 mainly in that the opening 141a of the first insulating layer (not shown) in the present embodiment is a trench, and the long axis or length of the trench (ie, the opening 141a) The edges extend in a direction parallel to the scan line 120 (ie, direction X).

Specifically, please refer to FIG. 1C and FIGS. 2A-2B at the same time. In the display device 100a of the present embodiment, the first insulating layer in the portion between the second signal line 131 and the first signal line 130 in FIG. 1C is divided into 140 is removed to form trenches (ie, openings 141 a ) extending in a direction parallel to the scan line 120 (ie, direction X), as shown in FIG. 2A . Next, as shown in FIG. 2B , since the first insulating layer between the second signal line 131a and the first signal line 130 has been removed, the second signal line 131a can be located in the opening of the first insulating layer The 141 a is disposed on the first signal line 130 in a direct contact manner, thereby increasing the contact area between the second signal line 131 a and the first signal line 130 .

FIG. 3A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 3B is a schematic cross-sectional view of the display device of FIG. 3A along the section line D-D'. Please refer to FIG. 2B for a schematic cross-sectional view of the display device of FIG. 3A along the section line C-C'. 1A-1B and FIGS. 2A-2B at the same time, the display device 100b of this embodiment is substantially similar to the display device 100 of FIGS. 1A-1B , so the same and similar components in the two embodiments will not be repeated here. The main difference between the display device 100 b of this embodiment and the display device 100 is that the display device 100 b of this embodiment further includes a transition pad 190 .

3A and 3B, in this embodiment, the first insulating layer 140b has an opening 142b, the second insulating layer 180b has an opening 181b, and the third insulating layer 182b has an opening 183b. The opening 142b of the first insulating layer 140b exposes a portion of the drain electrode SD2. The opening 181b of the second insulating layer 180b communicates with the opening 142b of the first insulating layer 140b and also exposes part of the drain electrode SD2. The opening 183b of the third insulating layer 182b exposes part of the transfer pad 190 .

In this embodiment, the transfer pad 190 is disposed on the first insulating layer 140b, the second signal line 131 and the second insulating layer 180b. The second insulating layer 180b is disposed between the second signal line 131 and the transfer pad 190 . The transfer pad 190 is disposed between the third insulating layer 182b and the second insulating layer 180b. The transfer pad 190 can also be disposed in the opening 181b of the second insulating layer 180b and the opening 142b of the first insulating layer 140b, so that the transfer pad 190 can pass through the opening 181b of the second insulating layer 180b and the opening 142b of the first insulating layer 140b. The opening 142b is electrically connected to the drain electrode SD2. Next, in addition to being disposed on the third insulating layer 182b, the pixel electrode 160b can also be disposed in the opening 183b, so that the pixel electrode 160b can be electrically connected to the transfer pad 190 through the opening 183b. That is, the drain electrode SD2 can be electrically connected to the pixel electrode 160b through the pad 190 . In addition, since the transfer pad 190 and the second signal line 131 are respectively disposed at different layers, it can avoid the electrical connection between the transfer pad 190 and the second signal line 131, so as to ensure that there is no connection between the source SD1 and the drain SD2. There is a short circuit problem, and the transfer pad 190 can have a larger area than the drain SD2 to be in contact with the pixel electrode 160b.

In this embodiment, the transfer pad 190 is disposed corresponding to the drain electrode SD2. The orthographic projection of the transfer pad 190 on the substrate 110 at least partially overlaps with the orthographic projection of the drain SD2 on the substrate 110 , and the orthographic projection of the transfer pad 190 on the substrate 110 is greater than the orthographic projection of the drain SD2 on the substrate 110 . In the top view of the display device 100b (as shown in FIG. 3A ), along the direction Y, the maximum width W3 of the transfer pad 190 is greater than the maximum width W4 of the drain electrode SD2 . In this embodiment, the material of the transfer pad 190 may include a transparent conductive material or a non-transparent conductive material, such as indium tin oxide, indium zinc oxide, indium oxide, zinc oxide, tin oxide, metal material, other suitable materials or The above combination, but not limited thereto. In some embodiments, the aforementioned metal material may include molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co) ,, zirconium (Zr), tungsten (W), aluminum (Al), copper (Cu), silver (Ag), other suitable metals, or alloys or combinations of the above materials, but not limited thereto.

In this embodiment, since the area of the orthographic projection of the transfer pad 190 on the substrate 110 is larger than the area of the orthographic projection of the drain electrode SD2 on the substrate 110, and in the top view of the display device 100b (as shown in FIG. 3A ) , the maximum width W3 of the transfer pad 190 is greater than the maximum width W4 of the drain electrode SD2 . Therefore, compared with the drain electrode SD2 , the transfer pad 190 can have a larger area in contact with the pixel electrode 160 b . Therefore, in the display device 100b of the present embodiment, the contact area between the pixel electrode 160b and the contact pad 190 with a larger area can be increased, so as to reduce the resistance value between the pixel electrode 160b and the drain electrode SD2.

In addition, in some embodiments, an insulating layer (not shown) may be disposed between the pixel electrode 160b and the third insulating layer 182b, so as to reduce the damage probability of the third insulating layer 182b during the manufacturing process of the display device 100b . In some embodiments, an insulating layer (not shown) may also be disposed between the third insulating layer 182b and the transfer pad 190 to reduce the damage probability of the transfer pad 190 during the manufacturing process of the display device 100b. Although the opening 141a of the first insulating layer 140b in this embodiment is a trench, it is not limited to this. In some embodiments, the opening 141a of the first insulating layer 140b can also be a hole, as shown in the opening 141 of FIG. 1A . Show.

FIG. 4A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 4B is a schematic cross-sectional view of the display device of FIG. 4A along the section line E-E'. 1A-1B and FIGS. 4A-4B at the same time, the display device 100b of this embodiment is substantially similar to the display device 100 of FIGS. 1A-1B , so the same and similar components in the two embodiments will not be repeated here. The display device 100c of the present embodiment is different from the display device 100 mainly in that, in the top view of the display device 100c of the present embodiment (as shown in FIG. 4A ), the second side 162c of the pixel electrode 160c is in phase with the direction Y The first sides 161c' of adjacent pixel electrodes 160c' face each other.

4A, in the top view of the display device 100c, the pixel electrode 160c corresponds to the scan line 120c (for example, the scan line 120c can provide a voltage, so that the first signal line 130 and/or the second signal line 131c It is determined whether the pixel electrode 160c is charged or not according to the voltage), and the pixel electrode 160c' corresponds to the scan line 120c' (for example, the scan line 120c' can provide a voltage, so that the first signal line 130 and/or the second signal line 131c can be charged according to the voltage. The voltage determines whether the pixel electrode 160c' is charged or not), and the pixel electrode 160c is adjacent to the pixel electrode 160c' in the direction Y; the pixel electrode 160c has a first side 161c adjacent to the scan line 120c and opposite to the first side 161c and the pixel electrode 160c' has a first side 161c' adjacent to the scan line 120c' and a second side (not shown) opposite to the first side 161c'.

In the top view of the display device 100c of the present embodiment, the second side 162c of the pixel electrode 160c and the first side 161c' of the pixel electrode 160c' adjacent along the direction Y face each other. That is, the first side 161c' of the pixel electrode 160c' is adjacent to the second side 162c of the pixel electrode 160c, and the first side 161c' of the pixel electrode 160c' is away from the first side 161c of the pixel electrode 160c. In other embodiments, the first side 161c, 161' and the second side 162c of the pixel electrodes 160c, 160c' (and the second side (not shown) of the pixel electrode 160c') may be non-linear edges (eg, having arc or concave edge), the first side 161c and the second side 162c are two separated sides, and the first side 161c is adjacent to the scan line 120c relative to the second side 162c, and the second side 162c is opposite to the first side 161c Away from the scan line 120c; the second side (not shown) of the first side 161c' relative to the pixel electrode 160c' is adjacent to the scan line 120c', and the second side (not shown) of the pixel electrode 160c' is opposite to the first side 161c 'Away from scan line 120c'.

4A and 4B, in this embodiment, the first insulating layer 140c has openings 141c and 142c, the second insulating layer 180c has openings 181c, and the third insulating layer 182c has openings 183c. The opening 141c of the first insulating layer 140c exposes a part of the source electrode SD1 (or the first signal line 130). The opening 142c of the first insulating layer 140c exposes a portion of the drain electrode SD2. The opening 181c of the second insulating layer 180c communicates with the opening 142c of the first insulating layer 140b and also exposes part of the drain electrode SD2. The opening 183c of the third insulating layer 182c communicates with the opening 181c of the second insulating layer 180c and the opening 142c of the first insulating layer 140b and also exposes part of the drain electrode SD2.

In this embodiment, the second signal line 131c can be disposed on the first insulating layer 140c and in the opening 141c of the first insulating layer 140c, so that the second signal line 131c can pass through the opening 141c and the source SD1 (or the first The signal line 130) is electrically connected. The pixel electrode 160c can be disposed on the third insulating layer 182c and located in the opening 183c, the opening 181c and the opening 142c, so that the pixel electrode 160c can be electrically connected to the drain electrode SD2 through the opening 183c, the opening 181c and the opening 142c.

FIG. 5A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 5B is a schematic cross-sectional view of the display device of FIG. 5A along the section line F-F'. 4A-4B and FIGS. 5A-5B at the same time, the display device 100d of this embodiment is substantially similar to the display device 100c of FIGS. 4A-4B , so the same and similar components in the two embodiments will not be repeated here. The display device 100d of this embodiment is different from the display device 100c mainly in that the display device 100d of this embodiment further includes a transition pad 190d.

5A and 5B, in this embodiment, the first insulating layer 140d has openings 142d, the second insulating layer 180d has openings 181d, and the third insulating layer 182d has openings 183d. The opening 142d of the first insulating layer 140d exposes a portion of the drain electrode SD2. The opening 181d of the second insulating layer 180d communicates with the opening 142d of the first insulating layer 140d and also exposes part of the drain electrode SD2. The opening 183d of the third insulating layer 182d exposes part of the transfer pad 190d.

In this embodiment, the transfer pad 190d is disposed on the first insulating layer 140d, the second signal line 131c and the second insulating layer 180d. The second insulating layer 180d is disposed between the second signal line 131c and the transfer pad 190d. The transfer pad 190d is disposed between the third insulating layer 182d and the second insulating layer 180d. The transfer pad 190d can also be disposed in the opening 181d of the second insulating layer 180d and the opening 142d of the first insulating layer 140d, so that the transfer pad 190d can pass through the opening 181d of the second insulating layer 180d and the opening 142d of the first insulating layer 140d. The opening 142d is electrically connected to the drain electrode SD2. Next, since the pixel electrode 160d is not only disposed on the third insulating layer 182d, but also can be disposed in the opening 183d, so that the pixel electrode 160d can be electrically connected to the transfer pad 190d through the opening 183d. That is to say, the drain electrode SD2 can be electrically connected to the pixel electrode 160d through the transfer pad 190d.

In this embodiment, the transfer pad 190d is disposed corresponding to the drain electrode SD2. The orthographic projection of the transfer pad 190 d on the substrate 110 and the orthographic projection of the drain SD2 on the substrate 110 may at least partially overlap, and the area of the orthographic projection of the transfer pad 190 d on the substrate 110 is larger than that of the drain SD2 on the substrate 110 . The area of the orthographic projection. In the top view of the display device 100d (as shown in FIG. 5A ), along the direction Y, the maximum width W3' of the transfer pad 190d is greater than the maximum width W4' of the drain electrode SD2. In this embodiment, the material of the transfer pad 190d may be the same as or similar to that of the transfer pad 190 , and details are not described herein again.

In addition, in some embodiments, an insulating layer (not shown) may be disposed between the pixel electrode 160d and the third insulating layer 182d, so as to reduce the damage probability of the third insulating layer 182d during the manufacturing process of the display device 100d . In some embodiments, an insulating layer (not shown) may also be disposed between the third insulating layer 182d and the transfer pad 190d to reduce the damage probability of the transfer pad 190d during the manufacturing process of the display device 100d.

To sum up, in the display device of the embodiment of the present disclosure, since the second signal line is disposed on the first signal line, and the second signal line can be electrically connected to the first signal line through the opening of the first insulating layer, the As a result, the display device of this embodiment can utilize the double-layered signal lines (ie, the first signal line and the second signal line) for signal transmission. Therefore, in the display device of this embodiment, the resistance of the signal lines can be reduced by the arrangement of the double-layered signal lines (ie, the first signal line and the second signal line), so as to increase the panel driving capability. For example, it is beneficial to Drive at high frequencies (eg greater than 90Hz).

Although the present disclosure has been disclosed above with examples, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure shall be determined by the scope of the appended patent application.

100, 100a, 100b, 100c, 100d: Display devices 110: Substrate 120, 120', 120c, 120c': scan lines 130: The first signal line 131, 131c: The second signal line 140, 140b, 140c, 140d: first insulating layer 141, 141a, 141c, 142, 142b, 142c, 142d, 181, 181b, 181c, 181d, 183, 183b, 183c, 183d: Opening 150: Transistor 160, 160', 160b, 160c, 160c', 160d: pixel electrodes 161, 161', 161c, 161c': first side 162, 162', 162c: second side 170: Buffer layer 171: Masking layer 172: Dielectric layer 172a, 172b: Opening 180, 180b, 180c, 180d: the second insulating layer 182, 182b, 182c, 182d: the third insulating layer 184: Fourth insulating layer 185: Common electrode 186: Fifth insulating layer 190, 190d: Adapter pad GE: gate GI: gate insulating layer GIa, GIb: Opening SD1: source SD2: Drain SE: Semiconductor layer W1, W2, W3, W3', W4, W4': maximum width X, Y: direction

FIG. 1A is a schematic top view of a display device according to an embodiment of the disclosure. FIG. 1B is a schematic cross-sectional view of the display device of FIG. 1A along the section line A-A'. FIG. 1C is a schematic cross-sectional view of the display device of FIG. 1A along the section line B-B'. FIG. 2A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 2B is a schematic cross-sectional view of the display device of FIG. 2A along the section line C-C'. FIG. 3A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 3B is a schematic cross-sectional view of the display device of FIG. 3A along the section line D-D'. FIG. 4A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 4B is a schematic cross-sectional view of the display device of FIG. 4A along the section line E-E'. FIG. 5A is a schematic top view of a display device according to another embodiment of the disclosure. FIG. 5B is a schematic cross-sectional view of the display device of FIG. 5A along the section line F-F'.

100: Display device 110: Substrate 120, 120': scan line 130: The first signal line 131: The second signal line 141, 142, 181, 183: Openings 160, 160': pixel electrode 161, 161': first side 162, 162': second side SD2: Drain SE: Semiconductor layer W1, W2: maximum width X, Y: direction

Claims (10)

A display device, comprising: a substrate; a scanning line disposed on the substrate; a first signal line disposed on the substrate; a first insulating layer disposed on the first signal line and having an opening; a second a signal line, disposed on the first insulating layer, and electrically connected to the first signal line through the opening; a transistor, electrically connected to the scan line and the first signal line; and a pixel an electrode electrically connected to the transistor and having a first side adjacent to the scan line and a second side opposite the first side, wherein the opening is adjacent to the second side and away from the second side On the first side, the extending direction of the first signal line is substantially parallel to the extending direction of the second signal line. The display device of claim 1, wherein the openings are trenches, and the trenches extend in a direction parallel to the scan lines. The display device of claim 1, further comprising: a transfer pad disposed on the first insulating layer and the second signal line, wherein the transistor includes a drain, and the drain passes through the The transfer pad is electrically connected to the pixel electrode. The display device of claim 3, further comprising: a second insulating layer disposed between the second signal line and the transfer pad. The display device according to claim 4, wherein the first insulating layer further has another opening, the second insulating layer has an opening, and the opening of the second insulating layer communicates with the first insulating layer of said other opening. The display device of claim 5, wherein the transfer pad is electrically connected to the drain electrode through the opening of the second insulating layer and the other opening of the first insulating layer. The display device of claim 3, wherein a maximum width of the transfer pad is greater than a maximum width of the drain. The display device of claim 1, wherein a maximum width of the first signal line is different from a maximum width of the second signal line. The display device of claim 8, wherein a ratio of the maximum width of the second signal line to the maximum width of the first signal line is greater than or equal to 0.5 and less than or equal to 2. The display device of claim 1, wherein a maximum width of the second signal line is greater than or equal to a maximum width of the first signal line.

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