TWI758408B - Semiconductor structure - Google Patents

Abstract

A semiconductor structure includes a main circuit region and a dummy region adjacent to the main circuit region. The dummy region includes dummy patterns. Along a first direction, the more the dummy regions are away from the main circuit region, the larger size and gap the dummy patterns have.

Description

semiconductor structure

The present invention relates to a semiconductor structure, and more particularly, to a semiconductor structure having a dummy pattern.

In recent years, due to the continuous change of the semiconductor structure, the number of process steps of the semiconductor structure is increased accordingly, which tends to reduce the process yield of the semiconductor structure. Especially when the component has defects, it is easy to cause the yield of the subsequent process to decrease.

Therefore, designers are all dedicated to reducing defects in the semiconductor process to improve product yield.

The present invention relates to a semiconductor structure, which can avoid the problem of lowering product yield.

According to a concept of the present disclosure, a semiconductor structure is proposed, which includes a main circuit region and a dummy region adjacent to each other. The dummy area includes several dummy patterns. The dummy patterns have larger size and spacing in a first direction away from the main circuit area.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

102: Main circuit area

104: Dummy area

104A: First area

104B: Second area

104C: Tertiary Area

106A: First dummy pattern

106B: Second dummy pattern

106C: Third dummy pattern

108: Conductive Pattern

108S: Pattern Side

D1: first direction

D2: Second direction

K1: The first distance

K2: Second distance

K3: The third distance

W1, W2, W3, L1, L2, L3: Dimensions

S1, S2, S3: Spacing

P1, P2, P3: pitch

Mn: nth metal layer

Mn+1: n+1 metal layer

FIG. 1 illustrates a top view of a semiconductor structure according to an embodiment.

FIG. 2 is a cross-sectional scanning electron microscope (SEM) image of a semiconductor structure of an embodiment.

FIG. 3 is a cross-sectional SEM image of a semiconductor structure of a comparative example.

The following are some examples to illustrate. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn according to the actual product scale. Therefore, the contents of the description and illustrations are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure. In addition, the descriptions in the embodiments, such as detailed structures, process steps, and material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of protection of the present disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following, the same/similar symbols are used to represent the same/similar elements for description.

Please refer to FIG. 1, which shows a top view of a semiconductor structure according to an embodiment. The semiconductor structure includes a main circuit area 102 and a dummy area 104 adjacent to each other. The dummy area 104 includes a first area 104A, a second area 104B, and a third area 104C that are sequentially away from the main circuit area 102 in the first direction D1. In an embodiment, the dummy area 104 includes dummy patterns, which include, for example, a first dummy pattern 106A, a second dummy pattern 106B, and a third dummy pattern 106C. The first dummy pattern 106A is along the first The directions D1 are arranged at intervals in the first region 104A. The second dummy patterns 106B are arranged in the second region 104B at intervals along the first direction D1. The third dummy patterns 106C are arranged in the third region 104C at intervals along the first direction D1.

In one embodiment, the first distance K1 between the boundary of the first area 104A farther from the main circuit area 102 and the pattern side 108S of the conductive pattern 108 in the main circuit area 102 closest to the dummy area 104 is equal to or less than 1 μm . The second distance K2 between the boundary of the second region 104B farther from the main circuit region 102 and the pattern side 108S of the conductive pattern 108 is 1 um-2 um. The third distance K3 between the boundary of the third region 104C farther away from the main circuit region 102 and the pattern side 108S of the conductive pattern 108 is greater than 2um. However, the present disclosure is not limited to this, and the size ranges of the first region 104A, the second region 104B, and the third region 104C can also be appropriately adjusted according to actual needs.

The first dummy patterns 106A have a dimension W1 along the first direction D1, and adjacent first dummy patterns 106A are separated from each other by a spacing S1. The second dummy patterns 106B have a dimension W2 along the first direction D1, and adjacent second dummy patterns 106B are separated from each other by a spacing S2. The third dummy patterns 106C have a dimension W3 along the first direction D1, and adjacent third dummy patterns 106C are separated from each other by a spacing S3. In the embodiment, size W1 < size W2 < size W3. In addition, pitch S1 < pitch S2 < pitch S3 .

The sum of the size W1 and the pitch S1 of the first dummy pattern 106A is the pitch P1 of the first dummy pattern 106A. The sum of the size W2 of the second dummy pattern 106B and the pitch S2 is the pitch P2 of the second dummy pattern 106B. The sum of the size W3 and the spacing S3 of the third dummy pattern 106C is the third dummy pattern 106C The pitch P3. In one embodiment, the value of dividing the dimension W1 by the pitch S1 (which can be expressed as dimension W1/pitch S1 ) may be the value of the process limit minimum pitch P1 . The value of dimension W2/pitch S2 may be 1.5 times the value of process limit minimum pitch P2. The value of dimension W3/pitch S3 may be greater than 3 times the value of process limit minimum pitch P3. However, the present disclosure is not limited to this, and the size and spacing of each dummy pattern may be appropriately adjusted according to actual needs.

In one embodiment, all the first dummy patterns 106A in the first area 104A may have the same size W1, and no adjacent first dummy patterns 106A are disposed in the first direction D1 with a size different from the size W1 other patterns (conductive patterns and/or dummy patterns). All the second dummy patterns 106B in the second area 104B may have the same size W2, and no other pattern (conductive pattern) having a size different from the size W2 in the first direction D1 is disposed between the adjacent second dummy patterns 106B. pattern and/or dummy pattern). All the third dummy patterns 106C in the third region 104C may have the same size W3, and no other pattern (conductive) having a size different from the size W3 in the first direction D1 is disposed between the adjacent third dummy patterns 106C. pattern and/or dummy pattern).

In one embodiment, there is no other area between the first area 104A and the second area 104B having a dimension between the dimension W1 of the first dummy pattern 106A and the dimension W2 of the second dummy pattern 106B in the first direction D1 Patterns (conductive patterns and/or dummy patterns). Between the second area 104B and the third area 104C, there are no other patterns (conductive pattern and / or dummy pattern).

In other embodiments, it may be further away from the main circuit than the third region 104C Other dummy patterns are arranged in the area of the region 102 , for example, a fourth dummy pattern (not shown) having a larger size and spacing than the third dummy pattern 106C in the first direction D1 , and so on.

The first dummy pattern 106A has a dimension L1 along a second direction D2 different from the first direction D1. The second dummy pattern 106B has a dimension L2 along the second direction D2. The third dummy pattern 106C has a dimension L3 along the second direction D2. For example, the first direction D1 may be substantially perpendicular to the second direction D2. The first dummy pattern 106A, the second dummy pattern 106B, and the third dummy pattern 106C may have a long shape extending along the second direction D2. In other words, the dimension L1 (eg, length) of the first dummy pattern 106A is larger than the dimension W1 (eg, width). The dimension L2 (eg, length) of the second dummy pattern 106B is larger than the dimension W2 (eg, width). The dimension L3 (eg, length) of the third dummy pattern 106C is larger than the dimension W3 (eg, width). In one embodiment, the size L1, the size L2, and the size L3 may be the same.

In one embodiment, the first dummy pattern 106A occupies 50% of the area of the first region 104A. The second dummy pattern 106B occupies 50% of the area of the second region 104B. The third dummy pattern 106C occupies 40% to 50% of the area of the third region 104C. However, the present disclosure is not limited to this, and the pattern density of the dummy patterns in each region can also be appropriately adjusted according to actual needs.

In an embodiment, the dummy patterns have conductive properties and are located at the same level as the conductive patterns 108 in the main circuit area 102 . For example, the first dummy pattern 106A, the second dummy pattern 106B, the third dummy pattern 106C, and the conductive pattern 108 are all an n-th metal layer (ie, Mn), such as a 0-th metal layer (M0 , ie n=0), Either all are the first metal layer (M1, that is, n=1), or both are the second metal layer (M2, that is, n=2), or other higher-level metal layers (that is, n=3, 4, 5, and so on for larger integers).

In the embodiment, the semiconductor structure is configured with the dummy region 104 according to the concept of the embodiment (ie, the dummy pattern is configured therein), so that the entire hierarchy of the n-th metal layer (ie, all the metal layers of the n-th layer, including the conductive pattern) 108 and the chemical mechanical polishing process of each dummy pattern) to achieve better polishing flatness, that is, the top surface of the n-th metal layer left after the chemical mechanical polishing process is located in a substantially uniform horizontal position, which can To avoid the defect problem caused by the poor flatness of the n-th metal layer formed in higher-level components later. For example, please refer to FIG. 2, which is a cross-sectional scanning electron microscope (SEM) image of a semiconductor structure of an embodiment, wherein the horizontal position difference of the top surface of the n-th metal layer (Mn) is less than about 100 angstroms, Then the n+1 th metal layer (Mn+1) formed can have a desired shape. In addition, please refer to FIG. 3, which is a cross-sectional SEM image of a semiconductor structure of a comparative example. The n-th metal layer of the comparative example is not configured with a dummy area, and it can be found that the n-th layer (including the n-th dielectric layer and the After the CMP process, the horizontal position of the top surface of the n-th metal layer (Mn) in the main circuit area is obviously and gradually shifted upward from left to right, and the (maximum) horizontal position difference is about 400 angstroms, and then The formed n+1th metal layer will leave unexpected metal residues after the portion corresponding to the recessed area of the nth metal layer is subjected to the chemical mechanical polishing process, causing the conductive patterns of the n+1th metal layer to be inconsistent. The desired bridge problem reduces product yield. Therefore, the semiconductor structure according to the embodiment concept has a higher product yield as compared with the semiconductor structure of the comparative example.

According to the above, in the semiconductor structure of the embodiment concept, the dummy pattern is arranged in the dummy area adjacent to the circuit area, and the dummy pattern is arranged so that the top surfaces of the elements of the same level in the main circuit area are positioned at substantially the same horizontal position, so that the The higher-level components formed thereon have desired structural patterns to avoid the problem of reduced product yield caused by structural defects.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

102: Main circuit area

104: Dummy area

104A: First area

104B: Second Area

1O4C: The third area

106A: First dummy pattern

106B: Second dummy pattern

106C: Third dummy pattern

108: Conductive Pattern

108S: Pattern Side

D1: first direction

D2: Second direction

K1: The first distance

K2: Second distance

K3: The third distance

W1, W2, W3, L1, L2, L3: Dimensions

S1, S2, S3: Spacing

P1, P2, P3: pitch

Claims (8)

A semiconductor structure includes a main circuit area and a dummy area adjacent to each other, wherein the dummy area includes a first area, a second area and a first area that are sequentially away from the main circuit area in a first direction three regions, and the semiconductor structure includes a conductive pattern, a plurality of first dummy patterns, a plurality of second dummy patterns and a plurality of third dummy patterns, the conductive patterns are arranged in the main circuit region, the The first dummy patterns are arranged in the first area, the second dummy patterns are arranged in the second area, the third dummy patterns are arranged in the third area, and the second dummy patterns are arranged in the third area. The dummy patterns have a larger size and spacing in the first direction than the first dummy patterns, and the third dummy patterns have a larger size in the first direction than the second dummy patterns Size and spacing, a first distance between a boundary of the first region farther from the main circuit region and a pattern side of the conductive pattern closest to the dummy region is equal to or less than 1 μm, the second A second distance between the boundary of the area which is farther from the main circuit area and the pattern side of the conductive pattern closest to the dummy area is between 1um and 2um, and the third area is farther from the main circuit. A third distance between the boundary of the circuit area and the pattern side of the conductive pattern closest to the dummy area is greater than 2um. The semiconductor structure of claim 1, wherein the first dummy patterns and/or the second dummy patterns have elongated shapes extending along a second direction, and the second direction is different from the first dummy pattern. one direction. The semiconductor structure as described in claim 1, wherein the first dummy patterns and the second dummy patterns are not disposed in the first direction in a dimension between the first dummy patterns and the first dummy patterns. other dummy patterns among the second dummy patterns. The semiconductor structure of claim 1, wherein the first dummy patterns have the same size in the first direction, and the second dummy patterns have the same other dimension in the first direction one size. The semiconductor structure of claim 1, wherein the first dummy patterns and the second dummy patterns have the same size in a second direction different from the first direction. The semiconductor structure as described in claim 1, wherein the third dummy patterns have an elongated shape extending along a second direction. The semiconductor structure of claim 1, wherein the first dummy patterns, the second dummy patterns and the third dummy patterns have conductive properties. The semiconductor structure of claim 1, wherein the conductive pattern, the first dummy patterns, the second dummy patterns and the third dummy patterns have conductive properties and are located at the same level .

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