TWI758117B - Flash memory and writing method thereof - Google Patents

Abstract

A flash memory and a writing method thereof are provided. The flash memory includes a plurality of memory blocks and a plurality of multiplex circuits. The memory blocks are arranged into a plurality of memory banks. Each of the memory blocks transports a plurality of erase voltages or a plurality of program voltage to corresponding memory bank for executing an erase operation or a program operation. According to a programming while erasing instruction, when the erase operation is executed by one of the memory banks, the program operation is executed by another one of the memory banks.

Description

Flash memory and method of writing the same

The present invention relates to a flash memory and a writing method thereof, and more particularly, to a flash memory and a writing method thereof capable of performing programming actions during erasing.

In reverse-OR flash memory, the speed of executing the erase action is much lower than the speed of executing the program action. In the application of the Internet of Things, the so-called on-the-air firmware update (on-the-air firmware update) for the flash memory is a very important function. Therefore, if the time required for data updating by the flash memory can be effectively reduced, the risk of the content of the flash memory caused by power loss or defective software version can be effectively reduced.

The present invention provides a flash memory and a writing method thereof, which can accelerate the data writing speed of the memory and save power consumption by executing the programmed action during erasing.

The flash memory of the present invention includes a plurality of memory blocks and a plurality of multiplexing circuits. The memory block is divided into multiple memory banks. The multiplexing circuits are respectively coupled to the memory banks. Each multiplexer circuit is used for transmitting a plurality of erase voltages or a plurality of programming voltages so that the corresponding memory banks perform the erase operation or the programming operation. Wherein, according to the programming command during erasing, when one of the memory banks executes the erasing action, the other one of the memory banks executes the programming action.

The flash memory writing method of the present invention includes: distinguishing a plurality of memory blocks into a plurality of memory banks; providing a plurality of multiplexing circuits to correspond to the memory banks respectively, so that each multiplexing circuit transmits a plurality of erase voltages or A plurality of programming voltages are used to cause the corresponding memory banks to perform the erasing action or programming action; The other of them performs the programmed action.

Based on the above, the present invention divides the memory block into a plurality of memory banks. And provide different voltage supply channels through the multiplexing circuit, according to the programming command during erasing, provide a plurality of erasing voltages for one of the memory banks to execute the erasing action, and provide a plurality of programming voltages to make the other one memory to perform programmed actions. In the embodiment of the present invention, the programming action and the erasing action can be performed synchronously between different memory banks, which effectively reduces the time required for memory writing.

Please refer to FIG. 1A . FIG. 1A is a schematic diagram of a flash memory according to an embodiment of the present invention. The flash memory 100 includes a plurality of memory blocks 111 - 11A and 121 - 12A and a plurality of multiplexing circuits 130 and 140 . Among them, the memory blocks 111 to 11A are divided into a memory bank BK1, and the memory blocks 121 to 12A are divided into a memory bank BKN. The multiplexing circuits 130 and 140 are respectively coupled to the memory banks BK1 and BKN. Each of the multiplexing circuits 130 and 140 is used for transmitting a plurality of erasing voltages ERSV or a plurality of programming voltages PGV, so that each corresponding memory bank performs an erasing operation or a programming operation.

In this embodiment, the multiplexing circuits 130 and 140 can conduct appropriate operating voltages according to the programming command PGMCMD or the erasing command ERSCMD. One of the multiplexing circuits 130 and 140 may cause the corresponding memory bank (one of the memory banks BK1 and BKN) to perform an erase operation according to the erase command ERSCMD, and the other of the multiplexing circuits 130 and 140 may At the same time, according to the programming command PGMCMD, the corresponding memory bank (the other one of the memory banks BK1 and BKN) executes the programming action.

For example, please refer to FIG. 1A and FIG. 1B simultaneously, wherein FIG. 1B shows a block diagram of a flash memory chip according to an embodiment of the present invention. The flash memory chip 102 includes an address generator 1021, a data register 1022, a mode logic circuit 1023, a clock generator 1024, a static memory buffer 1025, a state machine 1026, a high voltage (HV) generator 1027, Sense amplifier 1028 , output buffer 1029 , memory array 1030 , X decoder 1031 and Y decoder 1032 . The output buffer 1029 outputs the signal SO or the signals SIO0 - SIO3 through the I/O interface circuit 1033 . The data register 1022 and the mode logic circuit 1023 can receive the signals SI, SIO0-SIO3, WP#, HOLD#, RESET# and CS# through the I/O interface circuit 1033 . Here, the multiplexing circuits 130 and 140 in FIG. 1A may be part of the circuits of the high voltage generator 1027 , the X decoder 1031 and the Y decoder 1032 . The mode logic circuit 1023 can determine the commands received through the I/O circuit 1033 and transmit the commands to the state machine 1026 to generate commands to operate the flash memory chip 102 accordingly.

When the flash memory chip 102 receives the erase command ERSCMD, the multiplexing circuit 130 can provide the erase voltage ERSV to the memory bank BK1 and enable the memory bank BK1 to perform the erase operation. At the same time, if the programming command PGMCMD is received along with the address of the non-memory bank BK1 (the erased memory bank) (eg, corresponding to the memory bank BKN), the multiplexing circuit 140 can provide the programming voltage PGV to the memory bank BKN , so that the memory bank BKN can perform programmed actions. Please note that, in this example, the corresponding memory banks BK1 and BKN can respectively set a plurality of status flags to record bits in a plurality of rows. Taking the memory bank BK1 as an example, one state flag records an in-progress erase state of the corresponding memory bank BK1 , and the other state flag records an in-progress programming state of the corresponding memory bank BK1 . The multiplexing circuits 130 and 140 can cause the corresponding memory banks BK1 and BKN to perform an erase operation or a programming operation according to the value of the status flag.

It is particularly worth noting that, in the embodiment of the present invention, following the above-mentioned example, the programming action of the memory bank BKN is executed synchronously with the erasing action of the memory bank BK1. On the premise that the erasing action requires a relatively long operation time, the programmed action of the memory bank BKN does not require additional operation time. Therefore, the programming action of the memory bank BKN does not need to be completed in a hurry, but can be performed through a degraded program action. Here, the so-called degraded programming operation is performed by reducing the number of bits of the programmed memory cells and/or reducing the programming voltage (relative to the general programming operation) that produces the hot carrier injection effect. The voltage value, and thereby reducing the programming current required in the programming action, and making the programming current less than a desired value (the expected value can be equal to the current value of the programming current required for the general programming action), it can be more Reduce power consumption.

Regarding the way of distinguishing the memory blocks in the embodiment of the present invention, reference may be made to the schematic diagrams of the way of distinguishing the memory blocks in the embodiment of the present invention in FIGS. 2A to 2C . In FIG. 2A , the flash memory has memory blocks 2101 to 2116 with consecutive physical addresses. The memory blocks 2101-2116 can be divided into memory banks BK1 and BK2. In the embodiment of FIG. 2A , the memory bank BK1 may include memory blocks 2101 to 2108 with consecutive physical addresses, and the memory bank BK2 may include memory blocks 2109 to 2116 with consecutive physical addresses.

In FIG. 2B , in the plurality of memory blocks respectively included in the memory bank BK1 and the memory bank BK2 , the physical addresses of each other may be interleaved. For example, according to the arrangement order of the physical addresses of the memory blocks 2101-2116, the memory bank BK1 may include the odd-numbered memory blocks 2101, 2103..., 2015; the memory bank BK1 may include the even-numbered memory areas Blocks 2102, 2104..., 2016. The memory banks BK1 and BK2 can be arranged in a staggered configuration. If the memory blocks of consecutive addresses are updated by erasing and post-programming operations, the above-mentioned staggered configuration is helpful for erasing operations in application programming. That is, in the flash memory, in progress, it is achievable to perform program operation and erase operation individually.

In addition, in FIG. 2C, corresponding to the embodiment of FIG. 2A, each memory block 2101-2108 included in the memory bank BK1 can be divided into a plurality of sub-blocks 2101-L, 2101-R-2108-L, 2108- R; the memory blocks 2109 to 2116 included in the memory bank BK2 can be divided into a plurality of sub-blocks 2109-L, 2109-R to 2116-L, and 2116-R. In the physical layout of the integrated circuit, taking the memory bank BK1 as an example, the sub-blocks 2101-L~2108-L can be arranged on the first side of the corresponding multiplexing circuit, and the sub-blocks 2101-R~2108-R Then, it can be arranged on the second side of the corresponding multiplexing circuit, and the first side is opposite to the second side.

Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of a flash memory according to another embodiment of the present invention. The flash memory 300 is a NOR flash memory. The plurality of memory blocks of the flash memory 300 can be divided into a memory bank BK1 and a memory bank BK2. The flash memory 300 includes multiplexing circuits 321 and 322 corresponding to the memory banks BK1 and BK2, respectively. The memory bank BK1 further includes a bit line selection switch driver 331, a word line driver 341, and a P-type well area (P-type well Inside deep N-type well, PWI area) and N-type well area in the N-type deep well, respectively. The drivers 351 and 361 of the deep N-type well (NWD area). The memory bank BK2 further includes a bit line selection switch driver 332, a word line driver 342, and drivers 352 and 362 for driving the PWI area and the NWD area, respectively.

In addition, the multiplexing circuit 321 is used to provide the erase voltage ERSV or the programming voltage PGV to the bit line selection switch driver 331 , the word line driver 341 , and the drivers 351 and 361 , so that a plurality of memory blocks in the memory bank BK1 Perform an erase action or a stylized action. The multiplexing circuit 322 is used to provide the erase voltage ERSV or the programming voltage PGV to the bit line select switch driver 332, the word line driver 342, and the drivers 352 and 362, so that the plurality of memory blocks in the memory bank BK2 can be erased Except actions or stylized actions. Among them, the bit line selection switch drivers 331 and 332 are used to control the opening or closing of a plurality of bit line switches; the word line drivers 341 and 342 respectively provide a plurality of word line voltages to the plurality of word lines; the drivers 351 and 352 The drivers 361 and 362 are used to provide a plurality of bias voltages to a plurality of PWI regions, and the drivers 361 and 362 are used to provide a plurality of bias voltages to a plurality of NWD regions.

For the implementation details of the multiplexing circuits 321 and 322 , reference may be made to the schematic diagrams of multiple implementations of the multiplexing circuits in the flash memory according to the embodiments of the present invention shown in FIG. 4A and FIG. 4B . In FIGS. 4A and 4B , the multiplexing circuit 400 includes a plurality of voltage selectors MX11 to MX56. The multiplexing circuit 400 receives the power supply voltage VDD, the reference ground voltage VSS, the positive boost voltage VPCP, the negative boost voltage VNCP, the positive mask voltage VPCP_INH, the negative mask voltage VNCP_INH, and the read voltage RDP.

In FIG. 4A, multiplexing circuit 400 performs programmed actions. At this time, the multiplexing circuit 400 uses the voltage selectors MX11 to MX56 to select the power supply voltage VDD, the reference ground voltage VSS, the positive boost voltage VPCP, the negative boost voltage VNCP, the positive mask voltage VPCP_INH, and the negative mask voltage. The mask voltage VNCP_INH and the read voltage RDP are selected, and the power supply voltage VDD, the positive boost voltage VPCP, the negative mask voltage VNCP_INH and the reference ground voltage VSS are output as a plurality of programming voltages.

In detail, the memory block corresponding to the multiplexing circuit 400 has a selected PWI area SPWI and a plurality of unselected PWI areas DSPWI. In the part corresponding to the selected PWI region SPWI, through the first path formed by the voltage selectors MX41, MX31, MX21, and MX11, the multiplexing circuit 400 provides the forward boost voltage VPCP to the selected PWI through the output of the voltage selector MX11. The word line of the selected memory cell in the SPWI of the middle PWI area. Corresponding to the embodiment of FIG. 3 , the forward boosted voltage VPCP output by the voltage selector MX11 can be first provided to the word line driver 341 to drive the word line of the selected memory cell. In addition, the second path formed by the voltage selectors MX42, MX32, MX12; the third path formed by the voltage selectors MX42, MX32, MX22, MX13; and the fourth path formed by the voltage selectors MX42, MX32, MX22, MX14 , the multiplexing circuit 400 can respectively provide the negative mask voltage VNCP_INH to the word lines of the unselected memory cells in the selected PWI area SPWI. The above four paths can be corresponding to the global word line flag GWL and the local word line flag LWL corresponding to the word line of the decoded memory cell, and receive the forward boost voltage VPCP or The corresponding relationship of the negative mask voltage VNCP_INH is shown in the following table: GWL LWL corresponding path 1 1 first path 1 0 second path 0 1 third path 0 0 fourth path

The memory cells connected by the first path are selected memory cells, and the memory cells connected by the second path to the fourth path are all unselected memory cells.

In addition, in the part corresponding to the unselected PWI area DSPWI, the fifth path formed by the voltage selectors MX34 and MX15; the sixth path formed by the voltage selectors MX34 and MX16; the seventh path formed by the voltage selectors MX34 and MX17 Path; the eighth path formed by the voltage selectors MX34 and MX18 is used to output the reference ground voltage VSS. Because the memory cells in the unselected PWI area DSPWI are all unselected memory cells, the reference ground voltage VSS can be provided to all the unselected memory cells in the unselected PWI area DSPWI through the above-mentioned seventh to eighth paths. Select the character line of the memory cell.

On the other hand, the voltage selector MX51 selects the forward boost voltage VPCP for output, and transmits it to the corresponding bit line selection switch driver to turn on the selected bit line selection switch. The voltage selector MX52 selects the reference ground voltage VSS for output, and thereby cuts off the unselected bit line selection switch. The voltage selector MX53 selects the power supply voltage VDD for output, and drives the selected NWD area through the corresponding driver. The voltage selector MX54 selects the reference ground voltage VSS for output, and drives the selected PWI area through the corresponding driver. The voltage selectors MX55 and MX56 respectively select the power supply voltage VDD and the reference ground voltage VSS for output. The outputs of the voltage selectors MX55 and MX56 are used to drive the unselected NWD area and the unselected PWI area, respectively.

Hereinafter, in FIG. 4B , the multiplexing circuit 400 is used to perform the erase operation. At this time, the multiplexing circuit 400 uses the voltage selectors MX11 to MX56 to select the power supply voltage VDD, the reference ground voltage VSS, the positive boost voltage VPCP, the negative boost voltage VNCP, the positive mask voltage VPCP_INH, and the negative mask voltage. The mask voltage VNCP_INH and the read voltage RDP are selected, and the power supply voltage VDD, the forward boost voltage VPCP, the negative boost voltage VNCP, the forward mask voltage VPCP_INH and the reference ground voltage VSS are output as a plurality of erase voltages.

In detail, the memory block corresponding to the multiplexing circuit 400 has a selected PWI area SPWI and a plurality of unselected PWI areas DSPWI. In the part corresponding to the selected PWI area SPWI, through the first path formed by the voltage selectors MX42, MX32, and MX11, the multiplexing circuit 400 provides the negative boost voltage VNCP to the selected PWI through the output of the voltage selector MX11. The word line of the selected memory cell in the SPWI area. The negative boosted voltage VNCP output by the voltage selector MX11 can be firstly supplied to the word line driver, thereby driving the word line of the selected memory cell. The second path formed by the voltage selectors MX42, MX32 and MX12 provides the negative boost voltage VNCP to the word line of the selected memory cell in the selected PWI area SPWI through the output of the voltage selector MX12. In addition, the multiplexing circuit 400 can respectively provide the forward mask voltage VPCP_INH to The word lines of unselected memory cells in the SPWI of the PWI area are selected. The above four paths can be corresponding to the global word line flag GWL and the local word line flag LWL corresponding to the word line of the decoded memory cell, and receive the negative boost voltage VNCP or The corresponding relationship of forward mask voltage VPCP_INH is shown in the following table: GWL LWL corresponding path 1 1 third path, fourth path 0 1 first path, second path

The memory cells connected to the first path and the second path are selected memory cells, and the memory cells connected to the third path and the fourth path are all unselected memory cells.

In addition, in the part corresponding to the unselected PWI area DSPWI, the fifth path formed by the voltage selectors MX34 and MX15; the sixth path formed by the voltage selectors MX34 and MX16; the seventh path formed by the voltage selectors MX34 and MX17 Path; the eighth path formed by the voltage selectors MX34 and MX18 is used to output the reference ground voltage VSS. Because the memory cells in the unselected PWI area DSPWI are all unselected memory cells, the reference ground voltage VSS can be provided to all the unselected memory cells in the unselected PWI area DSPWI through the above-mentioned seventh to eighth paths. Select the character line of the memory cell.

On the other hand, the voltage selector MX51 selects the reference ground voltage VSS for output, and transmits to the corresponding bit line selection switch driver to turn off the selected bit line selection switch. The voltage selector MX52 selects the reference ground voltage VSS for output, and thereby cuts off the unselected bit line selection switch. The voltage selector MX53 selects the forward boost voltage VPCP for output, and drives the selected NWD area through the corresponding driver. The voltage selector MX54 selects the forward boost voltage VPCP for output, and drives the selected PWI region through the corresponding driver. The voltage selectors MX55 and MX56 respectively select the power supply voltage VDD and the reference ground voltage VSS for output. The outputs of the voltage selectors MX55 and MX56 are used to drive the unselected NWD area and the unselected PWI area, respectively.

Please refer to FIG. 5 below. FIG. 5 is a schematic diagram illustrating an implementation manner of multiple multiplexing circuits corresponding to different memory banks in a flash memory according to an embodiment of the present invention. 5 has multiplexing circuits 510 and 520, wherein the multiplexing circuit 510 includes voltage selectors MX11a to MX56a, and the multiplexing circuit 520 includes voltage selectors MX11b to MX56b. In this embodiment, the multiplexing circuit 510 can perform the programming operation as shown in FIG. 4A , and the multiplexing circuit 520 can simultaneously perform the erasing operation as shown in FIG. 4B . In this way, the erasing operation for one memory bank (providing the erasing voltage through the multiplexing circuit 520 ) can be successfully completed, while the programming operation for the other memory bank (providing the programming voltage through the multiplexing circuit 510 ) can be successfully completed. It can effectively reduce the time required for data writing in the flash memory.

Incidentally, in this embodiment, the forward boost voltage VPCP_BK1 output by the voltage selector MX41a is used to provide the memory bank corresponding to the multiplexing circuit 510; the forward boost voltage VPCP_BK2 output by the voltage selector MX41b is used to provide To the memory bank corresponding to the multiplexing circuit 520; the negative boost voltage VNCP_BK1 output by the voltage selector MX42a is used to provide the memory bank corresponding to the multiplex circuit 510; the negative boost voltage VNCP_BK2 output by the voltage selector MX42b is used to provide To the memory bank corresponding to the multiplexer circuit 520.

In addition, in the embodiments of FIGS. 4A to 5 , the so-called forward boost voltage VPCP is based on a reference voltage and is generated by a boost mechanism (eg, a charge pump) to a voltage greater than 0 volts voltage. The negative boost voltage VNCP is also based on a reference voltage, and generates a voltage less than 0 volts through a negative boost mechanism (eg, a charge pump). The positive mask voltage VPCP_INH and the negative mask voltage VNCP_INH are designed according to the voltage values in the flash memory suitable for masking the unselected memory cells. In the present invention, it can be set and implemented in a manner well known to those skilled in the art, and there is no specific limitation.

In addition, the control signals received by the voltage selectors MX11a ~ MX56a and MX11b ~ MX56b can be generated by a controller provided in the corresponding flash memory. As for the implementation details of the voltage selectors MX11a~MX56a and MX11b~MX56b, any voltage selection circuit known to those skilled in the art can be used for implementation, and there is no specific limitation.

Next, please refer to FIG. 6 . FIG. 6 illustrates a flow chart of a write operation when the flash memory is erased according to an embodiment of the present invention. In FIG. 6 , steps S610 to S6130 are used to perform an erasing operation, and steps S601 to S605 are used to perform a programming operation. Among them, the erase action and the programmed action are applied to different memory banks respectively.

In detail, in step S610, the erasing action for the first memory bank is activated, in step S620, the preprogrammed action is performed first, and then in step S630, the stage i=0 and the number of shots j=0 are set. Please note here that the erasing action of this embodiment is performed in a multi-stage and multi-shot manner. Here, the so-called one gun refers to applying one erasing voltage pulse to the memory cell performing the erasing operation. In the so-called multi-stage multi-gun method, a target voltage is set for each erasing stage, and in each erasing stage, one or more erasing voltage pulses (guns) are applied to make the erased stage The threshold voltage of the memory cells can be less than the set target voltage. And after a plurality of erasing stages, the threshold voltage of the memory cell can be made smaller than the final set erasing target voltage.

Next, in step S640, the voltage value of the erase voltage is set, and in step S650, an erase voltage pulse is applied to the memory cells according to the voltage value set in step S640. Note here that the erase voltage pulse can be maintained for a time interval. In this time interval, the programmed actions of steps S601 to S605 can be performed synchronously for the second memory bank.

First, step S601 may determine whether to activate the programmed action again according to whether the programmed action has occurred before. If the determination result is yes, step S603 can be directly executed to start the programming process. On the other hand, if the determination result is negative, it is determined in step S602 whether a new programmed action needs to be executed. Here, if the determination result of step S602 is yes, then step S603 is performed; on the contrary, if the determination result of step S602 is no, step S670 is performed.

Please note that in step S603, one or more programming voltage pulses can be applied to the programmed memory cells, and then step S604 is used to determine whether the threshold voltage Vt of the programmed memory cells is greater than the programming target voltage . If the threshold voltage Vt of the memory cell is greater than the programming target voltage, it indicates that the programming operation has been completed, and step S670 can be executed. On the contrary, if the threshold voltage Vt of the memory cell is not greater than the programming target voltage in the time interval, it indicates that the programming operation is not completed, and the retry marking operation is performed through a flag in step S605.

Please note that the time interval for applying the erase voltage pulse in step S650 is limited. Therefore, if the time interval for the erase voltage pulse is not long enough to complete the programming of the memory cells, step S605 The marked action of retry is to perform the programming action of the unfinished memory cell in another time interval when the next erase voltage pulse is applied.

It is worth mentioning that when the erase voltage pulse is supplied stably, the power consumption of the flash memory for the erase operation is relatively low, and therefore, the programming operation of another memory bank is simultaneously executed at this time. , will not cause the problem of excessive power consumption.

It can be known from the above description that, in the embodiment of the present invention, since the programmed action in the programmed action during erasing is executed by being embedded in the erase action, no additional time interval is required. Therefore, it is not necessary to complete the programming action very quickly, but can be performed through a degraded program action, thereby reducing the programming current required in the programming action, and making the programming current less than A desired value can reduce power consumption.

Step S670 is succeeded after step S650 and is used to perform erasure verification. In step S680, it is determined whether the threshold voltage Vt of the erased memory cell is lower than the target voltage V1 at this stage, or whether j is greater than a preset maximum value. If one of the above two judgments is yes, step S6100 is executed, and if both judgment results are negative, step S690 is executed.

In step S690, j is incremented by 1 (j++), and step S650 is executed to apply the next erasing voltage pulse.

In step S6100, it is determined whether the threshold voltage Vt of the erased memory cell is less than the erasing target voltage and not less than the erasing target voltage, or whether j is greater than the maximum value. If one of the above two judgments is yes, then the erase operation is completed (step S6130 ). If the judgment results are both negative, step S6120 is executed to increment i by 1 (i++); set j to zero; and execute the erase Except for the next phase of the action.

Next, please refer to FIG. 7 , which is a flowchart illustrating a method for writing a flash memory according to an embodiment of the present invention. Wherein, in step S710, a plurality of memory blocks are distinguished into a plurality of memory banks. In addition, in step S720, a plurality of multiplexing circuits are provided to correspond to the memory banks respectively, so that each multiplexing circuit transmits a plurality of erase voltages or a plurality of programming voltages so that the corresponding memory banks perform an erase operation or Programmatic actions. And, in step S730 , according to the programming instruction during erasing, when one of the memory banks performs the erasing action, the other one of the memory banks performs the programming action.

Please refer to FIG. 8 , which is a flowchart illustrating a method for writing a flash memory according to another embodiment of the present invention. Wherein, in step S810, the host starts the programmed Sino-US elimination operation (PwE). The host may be an electronic device outside the flash memory. In step S820, the host inquires whether any erase operation is performed on the flash memory. If the query result in step S820 is YES, the PwE operation ends. If the query result in step S820 is no, step S830 is executed.

In step S830, the host sends a block erase command along with the block address of the target memory, and the flash memory is activated in step S840 to erase the block of the target address. Then, in step S850, the host inquires the flash memory whether any programmed actions are performed. If the query result in step S850 is yes, the PwE operation ends. If the query result in step S850 is negative, step S860 may be executed. In step S860, the flash memory issues a programming command accompanied by the address of the target block, and in step S870 it is checked whether the programmed address is erased.

If the check result of step S870 is YES, the PwE operation can be ended, and if the check result of step S870 is NO, the flash memory starts to program the block at the target address in step S880.

Please refer to FIG. 9 , which is a block diagram of a flash memory and a host chip according to an embodiment of the present invention. The flash memory 910 has the same hardware architecture as the flash memory 102 of FIG. 1B . The host chip 920 is coupled to the flash memory 910 . The flash memory 910 includes flash array bank 0 and flash array bank 1 . Each of the flash array bank 0 and the flash array bank 1 has a plurality of blocks (block 0 to block N+2). The host chip 920 has to a serial peripheral (SPI) interface 921, which is coupled to the serial peripheral (SPI) interface 912 of the flash memory 910 to transmit one or more commands. The host chip 920 and the flash memory 910 may be used to perform the steps of FIG. 8 , and here, the flash memory 910 may be a flash memory chip.

To sum up, the present invention provides a programming command during erasing, so that when one memory bank performs the erasing operation, another memory bank performs the programming operation. Under the condition of a large amount of data update, by inserting a programming operation that can be completed relatively quickly into an erasing operation having a relatively slow speed, the time required for the writing operation of the flash memory can be effectively reduced. Furthermore, the embodiments of the present invention can program the action during erasing, reduce the required power consumption by providing a degraded programming action, and further improve the working performance of the flash memory.

100, 300: Flash memory 111~11A, 121~12A, 2101~2116: Memory block 2101-L~2108-L, 2101-R~2108-R: Subblocks 130, 140, 321, 322, 400, 510, 520: Multiplex circuit 331, 332: Bit line selection switch driver 341, 342: word line driver 351, 361, 352, 362: drives BK1, BK2, BKN: memory bank ERSV: Erase Voltage MX11~MX56, MX11a~MX56a, MX11b~MX56b: Voltage selector PGV: Programmable Voltage PGMCMD: stylized command ERSCMD: Erase command VDD: Power supply voltage VSS: reference ground voltage VPCP, VPCP_BK1, VPCP_BK2: Forward boost voltage VNCP, VNCP_BK1, VNCP_BK2: Negative boost voltage VPCP_INH: Forward mask voltage VNCP_INH: Negative Mask Voltage RDP: read voltage SPWI: select the PWI area DSPWI: PWI area not selected GWL: Global character line flag LWL: area word line flag S601~S6130, S710~S730: Steps

FIG. 1A is a schematic diagram of a flash memory according to an embodiment of the present invention. FIG. 1B is a block diagram of a flash memory chip according to an embodiment of the present invention. FIG. 2A to FIG. 2C are schematic diagrams illustrating a way of distinguishing memory blocks according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a flash memory according to another embodiment of the present invention. 4A and 4B are schematic diagrams illustrating multiple implementations of multiplexing circuits in a flash memory according to an embodiment of the present invention. 5 is a schematic diagram illustrating an implementation of multiple multiplexing circuits corresponding to different memory banks in a flash memory according to an embodiment of the present invention. FIG. 6 is a flow chart of a write operation when the flash memory is erased according to an embodiment of the present invention. FIG. 7 is a flowchart illustrating a method for writing a flash memory according to an embodiment of the present invention. FIG. 8 is a flowchart illustrating a method for writing a flash memory according to another embodiment of the present invention. FIG. 9 is a block diagram of a flash memory and a host chip according to an embodiment of the present invention.

100: flash memory

111~11A, 121~12A: Memory block

130, 140: Multiplexing circuit

BK1, BKN: memory bank

ERSV: Erase Voltage

PGV: Programmable Voltage

PGMCMD: stylized command

ERSCMD: Erase command

Claims (13)

A flash memory includes: a plurality of memory blocks divided into a plurality of memory banks; and a plurality of multiplexing circuits respectively coupled to the memory banks, and each of the multiplexing circuits is used for transmitting a plurality of erase voltages or a plurality of programming voltages to cause the corresponding memory banks to perform an erase action or a programmed action, wherein, according to an erase-time programming command, when one of the memory banks performs the erase action, Another of the memory banks performs the programmed action. The flash memory of claim 1, wherein the memory blocks include a plurality of first memory blocks corresponding to a first memory bank, and a plurality of second memory blocks corresponding to a second memory bank. The flash memory of claim 2, wherein the physical addresses of the first memory blocks and the second memory blocks are interleaved. The flash memory of claim 2, wherein the first memory blocks have consecutive physical addresses, and the second memory blocks have consecutive physical addresses. The flash memory of claim 1, wherein when the first memory bank performs the erase operation, a corresponding first multiplexer circuit provides an erase voltage pulse to the first memory bank in a time interval , a second multiplexing circuit corresponding to the second memory bank causes the second memory bank to perform the programming action in the time interval. The flash memory according to claim 1, further comprising: in the process, the programming operation and the erasing operation are individually performed respectively. The flash memory according to claim 1, wherein a plurality of status flags respectively correspond to the memory banks, and each of the status flags records an in-progress erase state or an in-progress state of the corresponding memory bank. Stylized state. The flash memory of claim 1, wherein according to the erase-time programming command, the programming action is a degraded programming action, and the programming current corresponding to the programming action is less than an expected value. A method for writing a flash memory, comprising: distinguishing a plurality of memory blocks into a plurality of memory banks; providing a plurality of multiplexing circuits to correspond to the memory banks respectively, so that each of the multiplexing circuits transmits a plurality of erasures voltage or programming voltages to cause each of the corresponding memory banks to perform an erasing action or a programming action; and according to an erasing-time programming command to cause one of the memory banks to perform the erasing action, and causing the other one of the memory banks to perform the programmed action. The method for writing a flash memory as claimed in claim 9, wherein when one of the memory banks performs the erasing action according to the erase-time programming instruction, one of the memory banks is made to execute the erase operation. Another step of performing the programming operation includes: providing an erase voltage pulse to a first memory bank during a time interval to perform the erase operation; and causing a second memory bank to execute the program during the time interval change action. The method for writing a flash memory according to claim 9, wherein the erasing voltages include a power supply voltage, a reference ground voltage, a negative boost voltage, A forward boost voltage and a forward mask voltage, the programming voltages include the power supply voltage, the reference ground voltage, the forward boost voltage and a negative mask voltage. The method for writing a flash memory according to claim 9, further comprising: according to the erasing programming instruction, according to a degraded programming action to execute the programming action, and corresponding to the programming action The programming current is less than a desired value. The method for writing a flash memory according to claim 9, wherein the step of distinguishing the memory blocks as the memory banks comprises: distinguishing the memories according to the arrangement order of the physical addresses of the memory blocks Blocks are these memory banks.

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