TWI757583B - Method and testing device for testing memory - Google Patents

Abstract

A testing device is disclosed for testing a memory, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response of the first memory circuit. The testing device includes a comparing circuit and a calculating circuit. The comparing circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operated in conditions that are different from each other, to generate a plurality of first comparing results. The calculating circuit is configured to output, according to the plurality of first comparing results, a maximum hamming distance between two of the first responses and the plurality of responses of the first memory circuit. A method for testing a memory is also disclosed herein.

Description

Test device and method for testing memory

The present disclosure relates to a test device for testing memory, and more particularly, to a Hamming Distance analyzer and an analysis method thereof.

Due to many process factors, each integrated circuit (IC) is unique even though the integrated circuits are fabricated with the same process and the same materials. Every integrated circuit has the opportunity to operate in different operating environments depending on its actual application. Therefore, the robustness of one of the plurality of integrated circuits under different operating environments is a key issue in the field of semiconductor technology.

An aspect of the present disclosure discloses a test apparatus for testing a memory, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first one of the plurality of responses of the first memory circuit, and the first memory circuit is configured to store a second one of the plurality of responses of the second memory circuit response. Test Set Package Including comparison circuit and calculation circuit. The comparison circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses that the first memory circuit operates under a plurality of operating conditions corresponding to different operating environments to generate a plurality of first comparison results, and configured to compare a second response stored in the first memory circuit with a plurality of responses of the second memory circuit operating under a plurality of operating conditions corresponding to different operating environments to generate a plurality of second comparison results, wherein the comparison circuit It is further configured to generate a final result according to the first comparison result and the second comparison result. The calculation circuit is configured to output the maximum Hamming distance according to the final result, wherein the maximum Hamming distance is between two of the plurality of responses of the first memory circuit.

One aspect of the present disclosure discloses a method for testing a memory, comprising: maintaining one of a plurality of responses of a first memory circuit of a memory under a first operating condition of a plurality of operating conditions a first response; the first responses stored in a second memory circuit of the memory are sequentially compared with the responses of the first memory circuit under operating conditions corresponding to different operating environments to generate a plurality of first comparisons As a result, wherein each comparison result of the first comparison result is generated by adjusting the previous comparison result of the first comparison result; maintaining a plurality of a second memory circuit of a memory under a second operation condition of the operation condition A second response among the responses; the second responses stored in the first memory circuit of the memory are sequentially compared with responses of the first memory circuit under operating conditions corresponding to different operating environments to generate multiple responses a second comparison result, wherein each comparison result of the second comparison result is generated by adjusting the previous comparison result of the second comparison result; second response The coping with the second memory circuit produces a final result; and according to the final result, a maximum difference between the two of the copings with the first memory circuit is obtained.

An aspect of the present disclosure discloses a method for testing a memory, comprising: operating a first memory circuit of a memory under a plurality of operating conditions corresponding to different operating environments to obtain the first memory circuit A plurality of responses, and a first response that stores the responses of the first memory circuit is in the second memory circuit of the memory; the first memory circuit of the second memory circuit stored in the memory is sequentially performed. A mutually exclusive OR operation of the first response to the response and the other responses of the first memory circuit to generate multiple comparison results of the response of the first memory circuit; the operations are performed in a plurality of operations corresponding to different operating environments the second memory circuit under the condition to obtain a plurality of responses of the second memory circuit, and store a second response of the response of the second memory circuit in the first memory circuit; sequentially store in the memory The second response of the first memory circuit, the second response of the second memory circuit, and the second response of the second memory circuit are mutually exclusive or operated with a plurality of responses of the second memory circuit to generate a plurality of responses of the second memory circuit a comparison result; a final comparison result is generated according to the mutual exclusion or operation of the first response of the first memory circuit and the mutual exclusion or operation of the second response of the second memory circuit; and according to the final comparison result, output A maximum Hamming distance between the two for the response of the first memory circuit.

100: Device

105: Device to be tested

120: Memory array

140: Comparison circuit

142: mutex or gate

160: Computational Circuits

162: Counter

164: Maximum Hamming distance generation circuit

180: Recorder

100A: Device

101A/103A: Memory circuit

105A: Device under test

140A: Comparison circuit

160A: Computing Circuits

162A: Counter

164A: Maximum Hamming Distance Generation Circuit

180A: Recorder

182A/184A: Recording Circuit

200: Method

202-216: Operations

202A-216A: Operation

C0: Start reference value

C1-C4: Comparison results

R1-R5: Coping

FC: Final Comparison Results

HD: Hamming distance

Aspects of the present disclosure will be better understood from the following detailed description read in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, the dimensions of many features can be arbitrarily scaled for clarity of discussion.

[FIG. 1] is a schematic diagram illustrating a device and a device under test according to various embodiments of the present disclosure.

[ FIG. 2 ] is a flowchart illustrating a method of operating the device under test of the device of FIG. 1 according to various embodiments of the present disclosure.

[ FIG. 3 ] is a schematic diagram illustrating a comparison step for the device of FIG. 1 and the device under test according to various embodiments of the present disclosure.

4 is a schematic diagram illustrating a device and a memory according to various embodiments of the present disclosure.

[ FIG. 5 ] is a flowchart illustrating a method for the device of FIG. 4 to perform operations on memory according to various embodiments of the present disclosure.

The following disclosure provides many different embodiments or illustrations for implementing various features of the invention. The specific illustrations of components and arrangements described below are for the purpose of simplifying the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, a description that a first feature is formed on or over a second feature includes embodiments in which the first feature and the second feature are in direct contact, as well as embodiments where other features are formed between the first feature and the second feature, Embodiments such that the first feature and the second feature are not in direct contact. The dimensions of many features may be drawn at different scales for simplicity and clarity. In addition to this, this disclosure is Symbols and/or letters are repeated in the illustration. This repetition is for simplicity and clarity and does not imply any relationship between the various embodiments and/or configurations discussed.

Terms used in the specification generally have their original meanings in the art, and each term is used for a specific context. Specific examples (including specific examples of any terms discussed herein) used in this specification are for illustration only, and are not intended to limit the scope and meaning of the disclosure or any explanatory terms. Likewise, the present disclosure is not limited to the various embodiments in this specification.

Although the terms "first" and "second" may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish this element from the others. For example, a first element could be a second element, and similarly, a second element could be a first element, without departing from the scope of the embodiments. As used, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Terms such as "comprise", "comprising", "include", "including", "has", "having", etc. used in this specification are open Formula and means "including but not limited to".

See Figure 1. 1 is a schematic diagram of a device 100 and a device under test 105 according to various embodiments of the present disclosure.

In some embodiments, device 100 is a testing device. The device 100 is configured to test the robustness of the device under test 105 . In some embodiments, the apparatus 100 is applied or implemented as an Intra-hamming Analyzer. Device 100 is configured to generate the The maximum Hamming Distance (HD) of the measuring device 105 is measured. The maximum Hamming distance HD represents the robustness of the device under test 105 . In some embodiments, the Hamming distance HD indicates the number of different bits between two bins.

In some embodiments, the device under test 105 is a memory array under test. In some other embodiments, the device under test 105 includes a memory array under test. The memory array to be tested is, for example, but not limited to, static random access memory (SRAM), flash memory, or the like. Various memory arrays or cells used to construct various memory arrays or cells in or to be built into the device under test 105 are within the scope of the present disclosure.

In some embodiments, the device under test 105 operates under different operating conditions depending on its actual application. Operating conditions correspond to different operating environments. For illustration, different operating conditions correspond to different supply voltages, different operating temperatures, different operating frequencies, or a combination of the foregoing.

In some embodiments, the device under test 105 responds differently when the device under test 105 operates under different operating conditions. In some embodiments, each response is related to the content of the device under test 105 under a particular operating environment. For the sake of illustration, the handling of the device under test 105 operating at 10°C is different from the handling of the device under test 105 operating at 50°C.

As shown in FIG. 1 , in some embodiments, the device 100 includes a memory array 120 , a comparison circuit 140 and a computing circuit 160 . In some embodiments, the device 100 further includes a recorder 180 . The memory array 120 is coupled to the device under test 105 . The comparison circuit 140 is coupled to the memory array 120 and the device under test 105 . The recorder 180 is coupled to the comparison circuit 140 . Calculate electricity Road 160 is coupled to recorder 180 .

The above discussion is merely to describe exemplary connections that may be used in accordance with various embodiments. It should be understood that the various embodiments are not limited to the specific connections described above or those shown in FIG. 1 .

In addition, in this specification, the term "coupled" may also be referred to as "electrically coupled", and the term "connected" may also be referred to as "electrically connected" )". "Coupled" and "connected" may also be used to indicate that two or more elements cooperate or interact with each other.

As shown in FIG. 1 , the memory array 120 is configured to generate at least one response for the device under test 105 and store the at least one response. In some embodiments, the aforementioned at least one pair is copied or overwritten from the device under test 105 to the memory array 120 . In some embodiments, memory array 120 is a replica of device under test 105 , whereby memory array 120 generates at least one response that is identical to at least one response of device under test 105 .

In some embodiments, the storage capacity of the memory array 120 corresponds to the number of bits corresponding to at least one of the devices under test 105 . For example, if at least one pair of the device under test 105 has n bits, the storage capacity of the memory array 120 has at least n bits.

As shown in FIG. 1 , the comparison circuit 140 receives responses from the memory array 120 . The comparison circuit 140 also receives responses obtained from the device under test 105 under different operating conditions. Comparison circuit 140 is configured to sequentially compare responses from memory array 120 with multiple responses from device under test 105. a response to produce a corresponding comparison result.

As shown in FIG. 1 , in some embodiments, the comparison circuit 140 includes at least one exclusive OR gate 142 . The exclusive OR gate 142 has a first input terminal, a second input terminal and an output terminal. The first input terminal is coupled to the memory array 120 to receive responses from the memory array 120 . The second input is coupled to the device under test 105 to receive responses obtained from the device under test 105 under different operating conditions. The output of the mutex OR gate 142 is coupled to the recorder 180 .

The exclusive OR gate 142 is configured to sequentially perform the exclusive OR operation of the responses from the memory array 120 and the responses from the device under test 105 to generate corresponding comparison results. These comparison results are output to the recorder 180 .

The configuration of the comparison circuit 140 is for illustration purposes only. Various configurations of the comparison circuit 140 are within the scope of the present disclosure. For example, in some other embodiments, the comparison circuit 140 includes more than one mutex or gate, while in other embodiments, the comparison circuit 140 includes a plurality of mutex or gates, the number of which corresponds to the number of The same number as the device 105 should handle. In some other embodiments, the comparison circuit 140 is implemented by other logic elements.

As shown in FIG. 1 , the recorder 180 is configured to temporarily store the comparison results generated by the comparison circuit 140 . Next, according to the comparison result, the recorder 180 generates a final comparison result FC. In some embodiments, the final comparison result FC indicates the comparison result produced by comparing the response from the memory array 120 with the final response from the device under test 105 .

The number of recorders 180 is for illustration purposes only. Various numbers of recorders 180 are within the scope of the present disclosure. In some other embodiments, device 100 includes more than one recorder. For example, in some other embodiments, device 100 includes two recorders. A first recorder of the two recorders is coupled to the comparison circuit 140 to temporarily store the comparison of the two corresponding bits from the comparison circuit 140 . A second recorder of the two recorders is coupled to the first recorder and is configured to generate a final comparison result FC based on a plurality of comparisons of two corresponding bits that are different from the first recorder.

As shown in FIG. 1 , the calculation circuit 160 is configured to receive the final comparison result FC from the recorder 180 . The calculation circuit 160 is further configured to output the maximum Hamming distance HD according to the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between the two responses from the device under test 105 .

As shown in FIG. 1 , in some embodiments, the calculation circuit 160 includes a counter 162 and a maximum Hamming distance generating circuit 164 . Counter 162 is coupled to recorder 180 . The maximum Hamming distance generating circuit 164 is coupled to the counter 162 .

The counter 162 is configured to receive the aforementioned final comparison result FC from the recorder 180 . According to the final comparison result FC, the value counted by the counter 162 indicates the number of bits in which the final comparison result FC has the same logical value. In some embodiments, the same logic value is "1". In other words, if the 4 bits of the final comparison result FC have the logic value "1", the counter 162 outputs the data indicating 4 to the maximum Hamming distance generating circuit 164 . in some real In an embodiment, the counter 162 is implemented as a group counter composed of a plurality of adders (not shown). In other embodiments, the counter 162 is implemented with other logic gates.

Next, the maximum Hamming distance generating circuit 164 generates the maximum Hamming distance HD according to the aforementioned value and the total number of bits of the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between the two responses from the device under test 105 . In some embodiments, the maximum Hamming distance generating circuit 164 is constructed with a subtractor (not shown) or includes a subtractor, but not limited thereto. In other embodiments, the maximum Hamming distance generating circuit 164 is implemented with other logic gates.

The configuration of computing circuit 160 is for illustration purposes only. Various configurations of computing circuit 160 are within the scope of the present disclosure.

Furthermore, the configuration of the device 100 in FIG. 1 is for illustration purposes only. Various configurations of device 100 are within the scope of the present disclosure.

Please refer to Figure 2 and Figure 3. FIG. 2 is a flowchart illustrating a method 200 of operating the device under test 105 of the device 100 of FIG. 1 according to various embodiments of the present disclosure. 3 is a schematic diagram illustrating a comparison step for the device 100 and the device under test 105 of FIG. 1 according to various embodiments of the present disclosure.

The operation between the device 100 in FIG. 1 and the device under test 105 is described by the method 200 depicted in FIG. 2 below. For a better understanding of the present disclosure, the method 200 is described with reference to FIGS. 1 and 3 .

In operation 202, when the device under test 105 is operated under the first operating condition, the response R1 of the device under test 105 can be obtained. In some embodiments, the first operating condition is the initial operating condition of the device under test 105, but not This is limited. Therefore, the contents of the R1 system under the initial operating condition of the device under test 105 should be addressed. As shown in Figure 3, the response R1 is 01010101. In other words, when the device under test 105 is operating under the initial condition, the content of the device under test 105 is 01010101. Furthermore, when the device under test 105 is operating under the first operating condition, the initial reference value C0 in the recorder 180 is reset to 0000000.

The number of bits for response R1 and other responses of the device under test 105 are for illustration purposes only. The various bit numbers of the device under test 105 for R1 and other responses are within the scope of the present disclosure. For example, in other embodiments, the device under test 105 has less than 8 bits or more than 8 bits for each of the responses R1 or the other.

In operation 204 , pair R1 is copied into the memory array 120 . In some embodiments, the R1 should be copied or overwritten from the device under test 105 and retained in the memory array 120 . In other words, for the sake of illustration, in the following operations, the response R1 of 01010101 is stored in the memory array 120 and cannot be changed. In various embodiments, the memory array 120 is a replica of the device under test 105 , and thus, the memory array 120 generates at least one response that is identical to the response from the device under test 105 .

In operation 206, the operating conditions of the device under test 105 are changed. For example, the operating condition of the device under test 105 is changed from the first operating condition to the second operating condition. In some embodiments, the second operating conditions are different from the first operating conditions.

In operation 208, a new response for the device under test 105 is obtained. As described above, when the operating conditions of the device under test 105 change, the content of the device under test 105 changes accordingly. In some embodiments, the new coping R2 line is considered to be tested Contents changed in device 105. For illustration, the response R2 of the device under test 105 is 01000101.

In operation 210, the comparison circuit 140 compares the response R1 and the response R2 of the device under test 105 to generate a comparison result C1. In some embodiments, the exclusive OR gate 142 performs an exclusive OR operation on each bit of R1 and the corresponding bit of R2 to adjust the starting reference value C0 so that the starting reference value C0 is adjusted to be Compare result C1.

Referring to FIG. 3 for description, the exclusive OR gate 142 performs a mutually exclusive OR operation on the first element of R1 and the first element of R2. In some embodiments, the first bit is considered to correspond to the rightmost bit of the octets within R1, such as shown in FIG. 3, and the second bit is considered to correspond to the octets within R1 The bit adjacent to the rightmost bit in the cell, and so on. As illustrated in Figure 3, the first bit corresponding to R1 and the first bit corresponding to R2 have the same logical value "1", so the result of the mutually exclusive OR operation on the aforementioned two cells is the logical value "0" . Therefore, the first bit of the comparison result C1 remains with the logical value "0", which is the same as the first bit of the initial reference value C0.

Next, the exclusive OR gate 142 performs an exclusive OR operation on the second bit corresponding to R1 and the second bit corresponding to R2. Since the second bit corresponding to R1 and the second bit corresponding to R2 have the same logical value "0", the result of the mutually exclusive OR operation on the aforementioned two bits is the logical value "0". Therefore, the second bit of the comparison result C1 remains with the logical value "0", which is the same as the second bit of the initial reference value C0.

Correspondingly, the third bit of the comparison result C1, the fourth bit of the comparison result C1, the sixth bit of the comparison result C1, the seventh bit of the comparison result C1 The bit and the eighth bit of the comparison result C1 remain with the logical value "0".

For the sake of illustration, the fifth bit of R1 should have a logical value of "1", but the fifth bit of R2 should have a logical value of "0", so the result of the mutually exclusive OR operation on the aforementioned two bits is logical Value "1". Therefore, the fifth bit of the comparison result C1 traverses from the logical value "0" to the logical value "1".

Therefore, the initial reference value C0 is adjusted to the comparison result C1. The comparison result C1 is 00010000. The comparison result C1 is temporarily stored in the recorder 180 .

In operation 212 , it is confirmed whether there are other operating conditions for testing the device under test 105 . In some embodiments, the confirming step is performed by a controller (not shown) or a process circuit (not shown), but not limited thereto. If there are other operating conditions for testing (eg, the third operating condition), perform operation 206 again. In other words, the operating condition of the device under test 105 is changed from the second operating condition to the third operating condition. In some embodiments, the third operating condition is different from the second operating condition and is different from the first operating condition.

When the device under test 105 operates under the third operating condition, a new response of the device under test 105 can be obtained. As shown in FIG. 3 , the new response of the device under test 105 is 01111001. Then, the exclusive OR gate 142 performs the exclusive OR operation on the pair R1 and the pair R3 stored in the memory array 120 .

In some embodiments, if the Xth bit of a comparison result has a predetermined logic value (eg, logic value "1"), the Xth bit of the following comparison result is maintained. For illustration, the fifth bit of the comparison result C1 has the logical value "1". Either the mutex or operation is in response to the fifth bit of R1 and in response to R3 The result on the fifth bit of , the fifth bit of the following comparison result C2 is maintained to have a logic value of "1", as shown in FIG. 3 .

In addition, if the Y-th bit of the comparison result has a specific logic value (eg, logic value "0"), the Y-th bit of the following comparison results may be changed. In some embodiments, X and Y are positive integers. For illustration, as described above, each pair has n bits. X and Y are less than or equal to n, and Y is different from X.

For the sake of illustration, since the first bit corresponding to R1 and the first bit corresponding to R3 have the same logic value (for example, the logic value "0"), the result of the mutually exclusive OR operation on the aforementioned two bits is: Logical value "0". Therefore, the first bit of the comparison result C2 is maintained to have the logical value "0".

Accordingly, the second bit of the comparison result C2, the seventh bit of the comparison result C2, and the eighth bit of the comparison result C2 are maintained to have the logical value "0".

For the sake of illustration, since the third bit corresponding to R1 and the third bit corresponding to R3 have different logic values, the result of the mutually exclusive OR operation on the aforementioned two bits is the logic value "1". Therefore, the third bit of the comparison result C2 is changed to the logical value "1".

Accordingly, the third bit of the comparison result C2, the fourth bit of the comparison result C2, and the sixth bit of the comparison result C2 are maintained to have the logic value "1".

Therefore, the comparison result C1 of 00010000 is adjusted to form the comparison result C2 of 00111100. The comparison result C2 is temporarily stored in the recorder 180 . In other words, the comparison result C2 is adjusted by adjusting the previous comparison result produced by C1.

After the comparison result C2 is generated, if there are other operating conditions for testing (eg, the fourth operating condition), the operation 206 is input again. Next, the device under test 105 operates under the fourth operating condition. Therefore, the corresponding response R4 can be obtained. In some embodiments, the fourth operating conditions are different from the preceding operating conditions.

As shown in FIG. 3 , the new response R4 of the device under test 105 is 01000101. Then, exclusive OR gate 142 performs an exclusive OR operation on pair R1 and pair R4 from memory array 120 .

Taking FIG. 3 as an illustration, only the fifth bit corresponding to R4 and the corresponding bit corresponding to R1 have different logical values from each other. The fifth bit of the comparison result C2 has the logical value "1". Therefore, the fifth bit of the comparison result C3 still has the logic value "1". Every other bit corresponding to R4 has the same logical value as the corresponding bit corresponding to R1. Therefore, the other bits of the comparison result C3 are maintained. Therefore, the comparison result C3 is the same as the comparison result C2. The comparison result C3 is temporarily stored in the recorder 180 .

After the comparison result C3 is generated, if there are other operating conditions for testing (eg, the fifth operating condition), operation 206 is input again. Next, the operating condition of the device under test 105 is changed from the fourth operating condition to the fifth operating condition. Therefore, the corresponding response R5 can be obtained. In some embodiments, the fifth operating conditions are different from the preceding operating conditions.

Taking FIG. 3 as an illustration, the new response R5 of the device under test 105 is 10000110. Then, exclusive OR gate 142 performs an exclusive OR operation on pair R1 and pair R5 from memory array 120 .

The first bit corresponding to R5 and the first bit corresponding to R1 have different logical values. Therefore, the first bit of the comparison result C4 is adjusted to have the logical value "1". Correspondingly, the second bit of the comparison result C4, the seventh bit of the comparison result C4, and the eighth bit of the comparison result C4 are adjusted to have the logical value "1". Therefore, the comparison result C3 of 00111100 is adjusted to form the comparison result C4 of 11111111. The comparison result C4 is temporarily stored in the recorder 180 .

Referring to FIG. 3 as an illustration, after the comparison result C4 is generated, if there is no operating condition for testing, the operation 214 of the method 200 is performed. The comparison result C4 is regarded as the aforementioned final comparison result FC.

In other embodiments, the comparison circuit 140 includes a plurality of mutually exclusive OR gates 142 . By way of illustration, compare circuit 140 includes eight exclusive OR gates 142 . Each mutex OR gate performs a mutex OR operation corresponding to the corresponding bit of R1 and one of the corresponding bits corresponding to it.

The number of mutually exclusive OR gates 142 within comparison circuit 140 is for illustration purposes only. Various numbers of mutually exclusive OR gates 142 within comparison circuit 140 are within the scope of the present disclosure.

In operation 214, the counter 162 generates a value having the same logical value as the bit in the comparison result C4. In some embodiments, the logic value of the bit in the comparison result C4 is the logic value "1". In other words, the counter 162 counts the number of bits having the logical value "1" in the comparison result FC. As an illustration, the comparison result FC is 11111111. Therefore, the value counted by the counter 162 is equal to the value eight. As mentioned above, in some embodiments, the counter 162 is a group counter composed of a plurality of adders (not shown). to build. Therefore, in the foregoing embodiment, the value 8 is a binary format, such as 1000, but not limited thereto.

In operation 216, the maximum Hamming distance generating circuit 164 generates the maximum Hamming distance HD according to the aforementioned value from the counter 162 and the total number of bits of the comparison result FC. Illustratively, the maximum Hamming distance generating circuit 164 calculates the ratio of the value generated by the counter to the total number of bits of the comparison result FC. In other words, if the comparison result C4 has n bits, and the comparison result C4 has m bits with logical value "1", the maximum Hamming distance HD is substantially equal to m/n, where m and n are positive integers.

In some embodiments, the maximum Hamming distance HD is presented as a percentage. As shown in FIG. 3, the total number of bits of the comparison result FC is 8. The number of bits of the bit having the logical value "1" in the comparison result FC is also 8. Therefore, the maximum Hamming distance HD is 100%.

The foregoing method 200 includes exemplary operations, but the operations of the method 200 do not necessarily have to be performed in the described order. The order of the operations of the method 200 disclosed in the present disclosure may be varied, or the operations may be performed concurrently or partially concurrently, as appropriate, within the spirit and scope of the various embodiments of the present disclosure.

Furthermore, since the aforementioned maximum Hamming distance HD is generated according to the response of the same device under test 105 , in some embodiments, the maximum Hamming distance HD is the internal Hamming distance of the device under test 105 . The maximum Hamming distance HD represents the maximum difference between any of the responses R1-R5 shown in FIG. 3 . Referring to FIG. 3 as an illustration, among the corresponding bits R1-R5 of the device under test 105, all the bits corresponding to R3 are respectively different from the corresponding bits corresponding to R5. In other words, the difference between responding to R3 and responding to R5 is 100%. Therefore, the maximum value of the device under test 105 Hamming distance HD is 100%.

In some embodiments, when the maximum Hamming distance HD of the device under test is 0%, it means that the device under test is perfectly repeatable and robust in different operating environments.

In some embodiments, when the maximum Hamming distance HD is higher than a preset value, the device under test 105 needs to be corrected or debugged. The preset value can be dynamically adjusted, but is not limited thereto.

In some embodiments, the device 100 and the device under test 105 are disposed on the same wafer or the same die. Thus, the apparatus 100 measures the device under test 105 directly on the wafer or wafer. In some embodiments, the device 100 measures the device under test 105 on a wafer acceptance testing (WAT) station.

In the device 100 discussed in this disclosure, the device 100 measures the device under test 105 on-line without downloading any response of the device under test 105 . Besides, only the maximum Hamming distance HD is output. Therefore, the time for downloading the response can be saved, and the storage space for storing the downloading response can also be saved.

See Figure 4. 4 is a schematic diagram illustrating a device 100A and a memory 105A according to various embodiments of the present disclosure.

In some embodiments, device 100A is a test device. Device 100A is configured to test the robustness of memory 105A. In some embodiments, the apparatus 100A is applied or implemented as an inner Hamming distance analyzer. Device 100A is configured to generate the maximum Hamming distance HD of memory 105A. The maximum Hamming distance HD represents the robustness of the memory 105A. In some embodiments, Hamming distance HD indicates the number of different bits between two bins.

In some embodiments, the memory 105A is, for example, but not limited to, static random access memory, flash memory, or the like. Various memory arrays or cells used to build the device under test 105 or to be built into the device under test 105 are within the scope of the present disclosure. In other embodiments, memory 105A includes memory circuit 101A and memory circuit 103A. In some embodiments, the memory circuit 101A is the device under test.

In some embodiments, the memory circuit 101A and the memory circuit 103A operate under various operating conditions depending on the actual application. Various conditions correspond to various operating environments. By way of illustration, various operating conditions include various supply voltages, various operating temperatures, various operating frequencies, or combinations of the foregoing.

As shown in FIG. 4, in some embodiments, device 100A includes comparison circuit 140A and calculation circuit 160A. In some embodiments, device 100A further includes recorder 180A. Comparison circuit 140A is coupled to memory 105A. Recorder 180A is coupled to comparison circuit 140A. Computing circuit 160A is coupled to recorder 180A. In some embodiments, the comparison circuit 140A includes or is implemented by a mutex OR gate.

The above discussion is merely a description of example connections that may be used in accordance with various embodiments. It should be understood that the various embodiments are not limited to the specific connection methods described above or shown in FIG. 4 .

As shown in FIG. 4, memory circuit 103A is configured to generate at least one response of memory circuit 101A and store at least one response. In some embodiments, the aforementioned at least one response is copied by the memory circuit 101A or is overwritten to the memory circuit 103A, so the memory circuit 103A generates At least one response of is the same as at least one response generated by the memory circuit 101A.

As shown in FIG. 4, the comparison circuit 140A receives the response from the memory circuit 103A. In some embodiments, comparison circuit 140A also receives responses obtained from memory circuit 101A under different operating conditions. The comparison circuit 140A is configured to sequentially compare the responses from the memory circuit 103A and the responses from the memory circuit 101A to generate corresponding comparison results.

In some embodiments, the comparison circuit 140A is configured to sequentially perform a mutually exclusive OR operation of the response from the memory circuit 103A and the response from the memory circuit 101A to generate corresponding comparison results. These comparison results are output to the recorder 180A. In some embodiments, when the comparison result is obtained, the roles of the memory circuit 101A and the memory circuit 103A are reversed, and the aforementioned operations are performed again.

As shown in FIG. 4, the recorder 180A is configured to temporarily store the comparison results generated by the comparison circuit 140A. Next, the recorder 180A generates a final comparison result FC according to the comparison result. In some embodiments, the final comparison result FC indicates the comparison result produced by comparing the response from memory circuit 103A with the final response from memory circuit 101A.

In some embodiments, recorder 180A includes recording circuit 182A and recording circuit 184A. The recording circuit 182A is configured to temporarily store the comparison results generated by comparing the responses from the memory circuit 103A with the responses from the memory circuit 101A under different operating conditions. Recording circuit 184A is configured to temporarily store responses from memory circuit 101A by comparing responses from memory circuit 103A under different operating conditions corresponding to the results of the comparison.

As shown in FIG. 4, the calculation circuit 160A is configured to obtain the final comparison result FC from the recording circuit 182A and the recording circuit 184A. The calculation circuit 160A is further configured to output the maximum Hamming distance HD according to the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between the two responses from memory circuit 101A and the two responses from memory circuit 103A.

As shown in FIG. 4, in some embodiments, the calculation circuit 160A includes a counter 162A and a maximum Hamming distance generating circuit 164A. Counter 162A is coupled to recording circuit 182A and recording circuit 184A. Maximum Hamming distance generating circuit 164A is coupled to counter 162A.

The counter 162A is configured to receive the aforementioned final comparison result FC from the recording circuit 182A and the recording circuit 184A. According to the final comparison result FC, the value counted by the counter 162A indicates the number of bits in which the final comparison result FC has the same logical value. In some embodiments, the same logic value is "1". In other words, if the 4 bits of the final comparison result FC have the logic value "1", the counter 162A outputs the data indicating 4 to the maximum Hamming distance generating circuit 164A. In some embodiments, the counter 162A is implemented as a group counter composed of a plurality of adders (not shown). In other embodiments, the counter 162A is implemented with other logic gates.

Next, the maximum Hamming distance generating circuit 164A generates the maximum Hamming distance HD according to the aforementioned value and the total number of bits of the final comparison result FC. The maximum Hamming distance HD represents the maximum difference between the two responses from memory circuit 101A. In some embodiments, the maximum Hamming distance produces electrical The circuit 164A is constructed with a subtractor (not shown) or includes a subtractor, but is not limited thereto. In other embodiments, the maximum Hamming distance generating circuit 164A is implemented with other logic gates.

See Figure 5. 5 is a flowchart illustrating a method 200A of operating the device 100A and memory 105A of FIG. 4 in accordance with various embodiments of the present disclosure.

The operations between the device 100A and the memory 105A are described below by the method 200A depicted in FIG. 5 . For ease of understanding, the method 200A is discussed in conjunction with FIG. 4 .

In operation 202A, the response of the memory circuit 101A is obtained when the memory circuit 101A operates under the first operating condition. In some embodiments, the first operating condition is the initial operating condition of the memory circuit 101A, but is not limited thereto.

In operation 204A, a copy or overwrite process is made to the memory circuit 103A. In some embodiments, the response is copied or overwritten from memory circuit 101A and maintained in memory circuit 103A.

In operation 206A, the operating conditions of the memory circuit 101A are changed. For example, the operating condition of the memory circuit 101A is changed from the first operating condition to the second operating condition. In some embodiments, the second operating conditions are different from the first operating conditions.

In operation 208A, a new response for memory circuit 101A is obtained. As described above, when the operating conditions of the memory circuit 101A change, the contents of the memory circuit 101A change accordingly.

In operation 210A, the comparison circuit 140A compares the new response and The response of the memory circuit 103A to generate the comparison result.

In operation 212A, it is determined whether there are other operating conditions for testing the memory circuit 101A. In some embodiments, the confirming step is performed by a controller (not shown) or a process circuit (not shown), but not limited thereto. If there are other operating conditions for testing (eg, the third operating condition), perform operation 206A again. In other words, the operating condition of the memory circuit 101A is changed from the second operating condition to the third operating condition. In some embodiments, the third operating condition is different from the second operating condition and is different from the first operating condition.

If there are no other operating conditions to test, operation 202B of method 200A is performed. In some embodiments, the roles of the memory circuit 101A and the memory circuit 103A are reversed, as will be described below.

In operation 202B, when the memory circuit 103A operates under the first corresponding operating condition, the response of the memory circuit 103A is obtained.

In operation 204B, a copy or overwrite process is performed into the memory circuit 101A. In some embodiments, the response is copied or overwritten from memory circuit 103A and maintained in memory circuit 101A.

In operation 206B, the operating conditions of the memory circuit 103A are changed. For example, the operating condition of the memory circuit 103A is changed from the first operating condition to the second operating condition. In some embodiments, the second operating conditions are different from the first operating conditions.

In operation 208B, a new response for memory circuit 103A is obtained. As described above, when the operating conditions of the memory circuit 103A change, the contents of the memory circuit 103A change accordingly.

In operation 210B, the comparison circuit 140A compares the new response with the response of the memory circuit 103A to generate a comparison result.

In operation 212B, it is determined whether there are other operating conditions for testing the memory circuit 103A. If there are other operating conditions for testing (eg, the third operating condition), perform operation 206B again.

If there are no other operating conditions to test, operation 214A of method 200A is performed.

In operation 214A, counter 162A generates a value having the same logical value as the bit in the comparison result. In some embodiments, the logical value of the bit in the comparison result is the logical value "1". In other words, the counter 162A counts the number of bits having the logical value "1" in the comparison result FC. As an illustration, the comparison result FC is 11111111 (binary). Therefore, the value counted by the counter 162A is equal to the value eight. As mentioned above, in some embodiments, the counter 162A is implemented as a group counter composed of a plurality of adders (not shown). Therefore, in the foregoing embodiment, the value 8 is a binary format, such as 1000, but not limited thereto.

In operation 216A, the maximum Hamming distance generating circuit 164A generates the maximum Hamming distance HD according to the aforementioned value from the counter 162A and the total number of bits of the comparison result FC. Illustratively, the maximum Hamming distance generating circuit 164A calculates the ratio of the value generated by the counter to the total number of bits of the comparison result FC. In other words, if the comparison result has n bits, and the comparison result has m bits with logical value "1", the maximum Hamming distance HD is substantially equal to m/n, where m and n are positive integers.

Compared to that shown in FIG. 1 , in some embodiments, the memory to be tested is The memory array 120 and the device under test 105 of the bulk array, the embodiment in FIG. 4 only shows a memory 105A including the memory circuit 101A and the memory circuit 103A, which are configured as the memory array and the device under test, respectively , or vice versa. In the embodiment of FIG. 4, memory 105A may be configured as the DUT for generating PUF bits, and the memory array is used to store responses from the DUT. Therefore, the overall area of the device in FIG. 4 can be reduced.

In some embodiments, an apparatus for testing a memory including a first memory circuit and a second memory circuit is disclosed. The second memory circuit is configured to store the first response of the first memory circuit. The device includes a comparison circuit and a calculation circuit. The comparison circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses in which the first memory circuit operates under different conditions to generate a plurality of first comparison results. The calculation circuit is configured to output a maximum Hamming distance according to the first comparison result, wherein the maximum Hamming distance is between two of the first pair and the plurality of pairs of the first memory circuit.

In some embodiments, the first memory circuit is configured to store the second response of the second memory circuit. The comparison circuit is configured to compare the second response stored in the first memory circuit with a plurality of responses operated by the second memory circuit under different conditions to generate a plurality of second comparison results.

In various embodiments, the computing circuit is configured to output a maximum Hamming distance based on the second comparison result, wherein the maximum Hamming distance is between the second pair and two of the plurality of pairs of the second memory circuit.

In some embodiments, the device further includes a recorder, and the recorder includes a first recording circuit and a second recording circuit. The first recording circuit system The first comparison result for calculating the maximum Hamming distance is arranged to store, and the second recording circuit is configured to store the second comparison result for calculating the maximum Hamming distance.

In various embodiments, the comparison circuit includes a mutex or gate. The mutual exclusion or gates are configured to perform a mutually exclusive OR operation of the first pair and each of the first memory circuits, and to perform a mutually exclusive OR operation of the second pair and each of the second memory circuits.

In some embodiments, the computing circuit includes a counter. The counter is configured to generate a first value, wherein the first value indicates the number of bits having the same logical value in a corresponding comparison result of the first comparison result, and the counter is configured to generate a second value, wherein the second value indicates a The number of bits with the same logic value in the corresponding comparison result of the second comparison result.

In various embodiments, the calculation circuit is further configured to generate the maximum Hamming distance according to the first value and the number of bits of the corresponding comparison result of the first comparison result, and to generate the maximum Hamming distance according to the corresponding comparison of the second value and the second comparison result The number of bits of the result to yield the maximum Hamming distance.

Also disclosed is a method comprising the following operations. A first response of the first memory circuit of the memory under the first operating condition is maintained. The first pair stored in the second memory circuit of the memory is sequentially compared with the plurality of pairs of the first memory circuit under operating conditions to generate a plurality of first comparison results. The aforementioned operating conditions are different from each other. Each of the plurality of first comparison results is generated by adjusting a previous comparison result of the plurality of first comparison results. Obtain the maximum difference value according to the plurality of first comparison results, wherein the maximum difference value is between the first pair and the first memory circuit The response is between the two.

In some embodiments, the method further includes the following operations. A second response of the second memory circuit maintaining the memory under the second operating condition. The second pair stored in the first memory circuit of the memory is sequentially compared with the plurality of responses of the second memory circuit under operating conditions to generate a plurality of second comparison results. The aforementioned operating conditions are different from each other. Each of the plurality of second comparison results is generated by adjusting a previous comparison result of the plurality of second comparison results.

In various embodiments, maintaining the first response of the first memory circuit includes the following operations. The first pair is copied into the second memory circuit of the memory. The replicated first pair is maintained within the second memory circuit.

In some embodiments, maintaining the first response includes the following operations. The first response is generated by the second memory circuit.

In various embodiments, maintaining the second response of the second memory circuit includes the following operations. The second pair is copied into the first memory circuit of the memory. The replicated second pair is maintained within the first memory circuit.

In some embodiments, maintaining the second response includes the following operations. A second response is generated by the first memory circuit.

In some embodiments, the method further includes the following operations. The first comparison result and the second comparison result are temporarily stored to calculate the maximum Hamming distance.

In various embodiments, the operation of obtaining the maximum difference value includes the following operations. A first value is generated, wherein the first value indicates the number of bits having the same logical value in a corresponding comparison result of the first comparison result. generates a second value, where the second value is indicated in the corresponding comparison result of the second comparison result The number of bits with the same logical value.

In some embodiments, outputting the maximum Hamming distance further includes the following operations. The maximum Hamming distance is generated according to the first value and the number of bits of the corresponding comparison result of the first comparison result. The maximum Hamming distance is generated according to the second value and the number of bits of the corresponding comparison result of the second comparison result.

In various embodiments, comparing the first pair of the second memory circuit stored in the memory with the pair of the first memory circuit includes the following operations. A mutually exclusive OR operation of the first pair stored in the second memory circuit and each pair of the first memory circuit is performed.

In some embodiments, comparing the second pair of the first memory circuit stored in the memory with the pair of the second memory circuit includes the following operations. A mutually exclusive OR operation of the second pair stored in the first memory circuit and each pair of the second memory circuit is performed.

Further disclosed is a method comprising the following operations. The first memory circuits of the memories under mutually different conditions are operated to obtain a plurality of responses of the first memory circuits. A plurality of responses of the first memory circuit are stored in the second memory circuit of the memory. The mutual exclusion or operation of the plurality of responses of the first memory circuit stored in the second memory circuit of the memory and the other responses of the responses of the first memory circuit is sequentially performed to generate a final comparison result. According to the final comparison result, output the maximum Hamming distance between the first response and the other responses.

In some embodiments, outputting the maximum Hamming distance includes the following operations. Generates a numerical value that indicates the number of bits that have the same logical value in the final comparison result. According to the value and the number of bits of the final comparison result, to produce the maximum Hamming distance.

The foregoing summarizes the features of many embodiments so that those of ordinary skill in the art may better understand aspects of the present disclosure. Those of ordinary skill in the art should appreciate that using the present disclosure as a basis, other processes and structures can be devised or modified to achieve the same purposes and/or achieve the same advantages as the described embodiments. Those skilled in the art should also understand that the equivalent structure does not deviate from the spirit and scope of the present disclosure, and can make various changes, exchanges and substitutions without departing from the spirit and scope of the present disclosure.

100: Device

105: Device to be tested

120: Memory array

140: Comparison circuit

142: mutex or gate

160: Computational Circuits

162: Counter

164: Maximum Hamming distance generation circuit

180: Recorder

FC: Final Comparison Results

HD: Hamming distance

Claims (10)

A testing device for testing a memory, wherein the memory includes a first memory circuit and a second memory circuit, the second memory circuit is configured to store a plurality of responses of the first memory circuit one of the first responses, and the first memory circuit is configured to store a second response of the plurality of responses of the second memory circuit, the testing device includes: a comparison circuit configured to compare the responses stored in the second memory circuit The first response of the second memory circuit and the responses of the first memory circuit operating under a plurality of operating conditions corresponding to different operating environments to generate a plurality of first comparison results, and are configured to compare stored in The second responses of the first memory circuit and the responses of the second memory circuit operating under operating conditions corresponding to the different operating environments to generate second comparison results, wherein the comparison circuit It is further configured to generate a final result according to the first comparison results and the second comparison results; and a calculation circuit configured to output a maximum Hamming distance according to the final result, wherein the maximum Hamming distance is in the These responses of the first memory circuit are between the two. The test apparatus of claim 1, wherein the computing circuit is configured to output a maximum Hamming distance according to the second comparison result, wherein the maximum Hamming distance is among the plurality of pairs of the second pair and the second memory circuit between the two. The test device as described in claim 2, further comprising: a recorder configured to store the first comparison results, the second comparison results and the final result, wherein the recorder includes a first recording circuit and a second recording circuit, the first recording circuit is configured to store to calculate the first comparison results of the maximum Hamming distance, and the second recording circuit is configured to store the second comparison results used to calculate the maximum Hamming distance. The test apparatus of claim 2, further comprising: a mutual exclusion OR gate configured to perform a mutual exclusion OR operation for each of the first pair and the responses of the first memory circuit, and to perform the A mutually exclusive OR operation of each of the pairs of the second pair and the second memory circuit. The test apparatus of claim 2, further comprising: a counter configured to generate a first value, wherein the first value indicates that one of the first comparison results has a same logic value as much as a corresponding comparison result A number of bits, and the counter is configured to generate a second value, wherein the second value indicates a number of bits having a same logical value in a corresponding comparison result of one of the second comparison results number. A method for testing a memory, comprising: maintaining a first response of a first memory circuit of a memory under a first operating condition of a plurality of operating conditions; storing a first response in the memory The first response in a second memory circuit of the body is sequentially matched with the first under the operating conditions corresponding to different operating environments The corresponding comparisons of the memory circuit generate a plurality of first comparison results, wherein each comparison result of the first comparison results is generated by adjusting the previous comparison result of the first comparison results; a second response of a plurality of responses of a second memory circuit of the memory under a second operating condition of some operating conditions; the second response stored in the first memory circuit of the memory sequentially compared with the responses of the first memory circuit under the operating conditions corresponding to the different operating environments to generate a plurality of second comparison results, wherein each of the second comparison results is compared A result is generated by adjusting a previous comparison result of the second comparison results; based on sequentially comparing the first pair with the responses of the first memory circuit and sequentially comparing the second pair with the first The responses of the two memory circuits produce a final result; and according to the final result, a maximum difference between two of the responses of the first memory circuit is obtained. The method of claim 6, wherein maintaining the first correspondence of the first memory circuit comprises: copying the first correspondence into the second memory circuit of the memory; maintaining the copied first correspondence within the second memory circuit. The method of claim 6, wherein maintaining the first response comprises: generating, by a second memory circuit, a first response, and wherein maintaining the second response of the second memory circuit comprises: Duplicating the second pair into the first memory circuit of the memory; and maintaining the duplicated second pair in the first memory circuit. A method for testing memory, comprising: operating a first memory circuit of a memory under a plurality of operating conditions corresponding to different operating environments to obtain a plurality of responses of the first memory circuit, and storing A first pair of the correspondences of the first memory circuit is in the second memory circuit of the memory; the first memory circuit of the second memory circuit stored in the memory is sequentially performed a mutual exclusion or operation of the first correspondence of the correspondences and other correspondences of the correspondences of the first memory circuit to generate comparison results of the correspondences of the first memory circuit; operating the second memory circuit under a plurality of operating conditions corresponding to the different operating environments to obtain a plurality of responses of the second memory circuit, and a first memory circuit storing the responses of the second memory circuit Two pairs are in the first memory circuit; the second pair of the pairs of the second memory circuit of the first memory circuit stored in the memory and the second memory circuit of the second memory circuit are sequentially performed. A mutual exclusion or operation of the other responses of the responses to generate a plurality of comparison results of the responses of the second memory circuit; according to the first responses of the responses of the first memory circuit The mutually exclusive OR operation and the second counterpart of the mutual exclusive OR operation of the second memory circuit generate a final comparison result; and output the first memory circuit according to the final comparison result Coping with a maximum Hamming distance between the two. The method of claim 9, wherein outputting the maximum Hamming distance comprises: generating a numerical value indicating a number of bits in the final comparison result having a same logical value; and according to the numerical value and The one-digit number of the final comparison result that yields the maximum Hamming distance.

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