TWI756971B - Memory device and read method thereof - Google Patents

Abstract

A memory device and a read method thereof are provided. The read method incudes: reading a memory cell array to obtain a page data; dividing the page data to a plurality of chunk data; performing a first error correction operation on each of the chunk data in sequential to respectively generate a plurality of corrected chunk data; performing a second error correction operation on the page data to generate a corrected page data; and outputting a readout data by referring to a indicating signal.

Description

Memory device and reading method thereof

The present invention relates to a memory device and a reading method thereof, and more particularly, to a memory device and a reading method thereof which can improve the reading rate.

In the conventional technical field, in the read operation of the non-volatile memory, the bottleneck of the performance of the read operation is often limited to the time consumed by the error correction operation to be executed. Theoretically, in the prior art, in order to reduce the time required for the reading operation, the reading operation of a plurality of consecutive memory pages can be performed, and after the page data of the previous memory page is read, the following A page address method can speed up the read continuation.

However, after a multi-bit error correction operation with a complex mechanism is applied in a memory device, the time required for each error correction operation becomes unpredictably long. Therefore, for the reading operation of a plurality of consecutive memory pages performed in the memory, the required reading time is often spent to perform the error correction operation, so that the efficiency of the reading operation cannot be improved.

The present invention provides a method for reading a memory, which can improve the reading rate.

The memory reading method of the present invention includes: reading a memory cell array to obtain page data; distinguishing page data into a plurality of blocks of data; sequentially performing a first error correction action for each block of data to generate a plurality of corrected block data; perform a second error correction action on the page data to generate corrected page data; and refer to an indication signal to output the corrected block data.

The memory device of the present invention includes a memory cell array, a page buffer, a data register, a first error correction circuit, a second error correction circuit, a control logic and a transmission interface. The page buffer is coupled to the memory cell array. The page buffer stores page data, wherein the page data is divided into a plurality of blocks of data. The data register is used to temporarily store block data. The first error correction circuit is coupled to the data register, and performs a first error correction operation for each block of data in sequence to generate a plurality of corrected blocks of data respectively. The second error correction circuit is coupled to the data register, and performs a second error correction operation on the page data to generate corrected page data. The control logic is coupled to the first error correction circuit and the second error correction circuit for controlling an error correction action and a second error correction action performed by the first error correction circuit and the second error correction circuit respectively. The transmission interface is coupled to the data register to output the corrected block data through the reference indication signal.

Based on the above, the present invention divides page data into a plurality of relatively small-sized chunks of data. The relatively fast error correction actions (the first error correction action) are sequentially performed for the block data, and the consecutive corrected block data can be read out immediately until there is a block data that cannot be corrected. The second error correction action may intervene and replace the execution of the error correction action of the subsequent read data. In this way, the error correction operation performed has a small number of error correction bits, which can reduce the time required for performing the error correction operation, thereby increasing the read rate of the memory. Further, if the corrected block data is not correct, the corrected page data generated by the relatively slow error correction action (the second error correction action) can be provided as read data. The correctness of the read operation of the memory device can be ensured.

Please refer to FIG. 1 . FIG. 1 is a flowchart illustrating a method for reading a memory according to an embodiment of the present invention. In step S110, a read operation is performed on a memory cell array, and a page of data is read out from the memory cell array. Wherein, the reading operation in step S110 may be performed for a memory page in the memory cell array, so as to read data of a page. In detail, a page address can be generated in advance, and a selected memory page can be selected from the memory cell array according to the page address, and a read operation is performed for the selected memory page. The data transmitted from the selected memory page can be sensed through a sense amplifier to generate the above-mentioned page data. In this embodiment, the page data has, for example, 2K or 4K bytes.

Next, in step S120 , the read page data is divided into a plurality of chunk data. In this embodiment, the page data can be evenly divided into a plurality of relatively small-sized blocks of data. In this embodiment, each block data has, for example, 256 bytes. Taking the page data having 2K bytes as an example, in step S120 one page of data can be distinguished as 8 blocks of data, and taking the page data having 4K bytes as an example, one page of data can be distinguished into 16 blocks of data in step S120 .

In step S130 , a first error correction code (ECC) operation is performed for each block data and the corresponding parity data in sequence, and a plurality of corrected block data are respectively generated. In this embodiment, the error correction action performed in step S130 is performed for block data with a smaller size, so the number of error bits that may occur in a single block of data may be small. Therefore, in this embodiment of the present invention, an error correction operation with a small number of error correction bits (eg, 1 bit) can be performed for each block of data in step S130, thereby reducing the time required for performing the error correction operation.

In this embodiment, the first error correction action in step S130 may be implemented according to a Hamming code, or other error correction codes and algorithms of those with ordinary knowledge in the art, and there is no fixed limits.

In step S140, when an error occurs in the first error correction action, a second error correction action is performed on the page data to generate corrected page data. In this embodiment, the speed of the first error correction action performed for the block data is faster than the speed of the second error correction action performed for the page data. Furthermore, the capability of the first error-correcting action is lower than the capability of the second error-correcting action. For example, the second error correction action may be performed according to a calculation method of a BCH code, an RS code or a low-density parity-check code (Low-density parity-check code, LDPC code).

In step S150, one of the corrected page data and the corrected block data can be outputted through the reference indication signal to generate the read data of the memory. In detail, if all corrected block data are correct, each block data can be output at once to generate read data. For example, the first block of data (block 0) may be corrected first, and the second block of data (block 1) may be simultaneously corrected when the first corrected block of data is output. In this way, multiple corrected block data can be output continuously without delay. On the contrary, if the first uncorrectable block data appears, then change and select the corrected page data as the read data. In addition, the memory can generate an indicator signal to indicate whether the read data is ready. The read data can be sent based on the indication signal.

Here, steps S130 and S140 may be performed simultaneously, or may be performed sequentially. And the above-mentioned indication signal may be an independent signal.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram illustrating an operation of a method for reading a memory according to an embodiment of the present invention. The memory cell array 210 has a plurality of memory pages PG0 ˜PGn+1. When performing the reading operation, the memory page PGn can be set as the selected memory page, and the data reading and sensing actions are performed for the selected memory page (memory page PGn), so as to obtain the data stored in the memory page PGn. page information. In this embodiment, page data can be temporarily stored in the page buffer 220 . The page data stored in the page buffer 220 can be divided into a plurality of block data CH0-CH3.

The block data CH0~CH3 can be provided in sequence to perform error correction, and the corrected block data CCH0~CCH3 are generated in sequence. The corrected block data CCH0 ˜ CCH3 can be sent to the transmission interface 230 to transmit the corrected page data composed of the corrected block data CCH0 ˜ CCH3 as read data.

In this embodiment, the memory cell array 210 may be a non-volatile memory cell array, such as a flash memory cell array.

Of course, the four pieces of data CH0-CH3 divided into a single page of data in FIG. 2 are only examples for illustration, and the number of pieces of data in other embodiments of the present invention can be determined by the designer, and there is no certain limitation.

Please refer to FIGS. 3A and 3B below. FIGS. 3A and 3B are flowcharts illustrating a method for reading a memory according to another embodiment of the present invention. In step S310, the reading operation is performed, and in step S320, the page data in a memory page (eg, the Nth memory page) is sensed by the sensing operation of the sense amplifier. In step S330 , the page data is latched in a data storage element such as the page buffer 310 . In step S340, the page data is transferred to the first cache 320, and in step S350, the address of the selected page is changed to the next page address. Wherein, in the first cache 320, the page data can be divided into a plurality of block data CH0-CH5.

Next, in step S361, one of the block data CH0-CH5 is sequentially performed an error correction (ECC) operation, and during the ECC operation of each block data CH0-CH5, it is determined whether it can pass 1 The ECC action of the bits is used to complete the error correction action of each block of data CH0~CH5 (step S371). If the judgment result is yes, then step S381 is executed; on the contrary, if the judgment result is no, step S372 is executed. Here, the number of error correction bits of the ECC operation executed in step S361 is 1.

It should be noted that, in this embodiment, step S362 simultaneously performs another ECC operation for the page data stored in the page buffer 310 , and the ECC operation in step S362 can be performed for multiple bit errors in the page data. correct.

When it is found in step S371 that the number of error bits in any piece of data exceeds one bit, and the error correction cannot be completed through the ECC operation in step S361, step S372 can be executed to target multiple pieces of data in the page. Error bits perform error correction actions.

Through step S381, a plurality of corrected block data corresponding to the block data can be obtained in sequence, and the corrected page data can be obtained accordingly. And through step S372, the corrected page data can be obtained directly. In step S390 , the corrected block data obtained in step S381 may be transferred to the second cache 330 . And, after step S390, the next block data is re-selected (step S3100) and step S340 is executed again.

In step S390 , the corrected page data obtained in step S372 may also be transferred to the second cache 330 . And in step S3110 , the read data is transmitted by reading the corrected page data in the second cache 330 to the transmission interface 340 .

In order to speed up the reading operation, when the page data is transferred to the first cache 320 in step S340, the selected page address can be changed to the next page address in step S350, and the next page address is executed through step S320. The page data of a memory page of a page address (such as the N+1th memory page, or the memory page preset by the host) is read and sensed, and the page data of the N+1th memory page is stored. into page buffer 310.

In addition, in this embodiment of the present invention, the different ECC actions performed in steps S361 and S362 may be performed simultaneously, or the execution of step S362 may be started only when the judgment result of step S371 is negative. There are no certain restrictions.

Incidentally, the ECC operation in step S361 may be performed according to the Hamming algorithm, and the ECC operation in step S362 may be performed according to BCH code, RS code or low-density parity-check code (Low-density parity-check code). code, LDPC code) to execute. Please note that the operation speed of the ECC action in step S361 is always faster than the operation speed of the ECC action in step S362.

Please note here that in step S3110, the read data sent from the memory is performed with reference to the instruction signal. The generation of the indication signal is carried out according to whether the read data is ready. In this way, the data receiver (eg, the host) can correctly obtain the read data without data loss.

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention. The memory device 400 includes a memory cell array 410 , a page buffer 420 , a first error correction code (ECC) circuit 431 , a second ECC circuit 432 , a data register 440 , a control logic 450 , a register 460 and a transmission interface 470 . The memory cell array 410 has a plurality of memory pages and is coupled to the page buffer 420 . When the reading operation is performed on the memory cell array 410 , a memory page in the memory cell array 410 can be selected for reading, and the read page data is temporarily stored in the page buffer 420 . Among them, the page data can be divided into a plurality of block data.

The data register 440 is coupled to the page buffer 420 . The data register 440 has a first cache 441 and a second cache 442 . The page data in the page buffer 420 may be flushed to the first cache 441 first. In addition, the first ECC circuit 431 can sequentially perform ECC operations for each block of data in the first cache 441, and sequentially generate a plurality of corrected blocks of data. And each corrected block data can be stored in the second cache 442 in sequence.

On the other hand, when the first uncorrectable block of data occurs, the second ECC circuit 432 can perform error correction actions. Under this method, the remaining uncorrected block data can complete the error correction action and output by correcting the following page data. In this embodiment, the error correction capability of the first ECC circuit 431 is lower than the error correction capability of the second ECC circuit 432 . For example, the number of error correction bits of the first ECC circuit 431 may be 1 bit, and the number of error correction bits of the second ECC circuit 432 may be multiple bits greater than 1. On the other hand, the speed of the ECC operation on each block data is faster than the speed of the ECC operation on the page data.

The control logic 450 is coupled to the memory cell array 410 , the page buffer 420 , the data register 440 , the first ECC circuit 431 and the second ECC circuit 432 . The control logic 450 can be used to perform data access operations of the memory cell array 410 . The control logic 450 can be used to control the transfer operation of the block data in the first cache 441 and control the activation time points of the first ECC circuit 431 and the second ECC circuit 432 .

In some embodiments, the memory device 400 may further include a third ECC circuit 433 . The third ECC circuit 433 is coupled between the control logic 450 and the data register 440 . The third ECC circuit 433 may perform another ECC action on the page data. The third ECC circuit 433 can correct more bits by the second ECC circuit.

In this embodiment, the control logic 450 may be used to execute the action flow shown in FIG. 3 , and for related details, please refer to the description of the embodiment in FIG. 3 .

The control logic 450 is coupled to the register 460 . Temporary registers 460 provide access to temporary data for the control logic 450 to perform various actions. The control logic 450 and the register 460 are coupled to the transmission interface 470 . The transmission interface 470 transmits and receives data or command signal I/O, receives the clock signal CLK, transmits and receives the chip selection signal CS# and transmits the data capture signal DQS.

The transmission interface 470 serves as a signal communication interface between the memory device 400 and an external electronic device. The transmission interface 470 may be a parallel transmission interface; a serial transmission interface; or a parallel serial transmission interface. It should be noted that, in the embodiment of the present invention, the transmission interface of the memory device 400 has no specific limitation on the transmission protocol. In this embodiment, one of the chip selection signal CS# and the data capture signal DQS can be selected as the indication signal. The transmission interface 470 can inform the external electronic device to receive the read data. The indication signal may be generated by the control logic 450 depending on whether the read data is ready. In some embodiments, the transmission interface 470 can provide the chip selection signal CS# and the interrupt signal RDY/BY# other than the data capture signal DQS as the indication signal.

Please refer to FIG. 5A to FIG. 7C below. FIGS. 5A to 7C are waveform diagrams of read operations of the memory device according to different embodiments of the present invention, respectively. In FIGS. 5A to 7C , the memory device may perform operations according to the clock signal SLCK.

In FIGS. 5A to 5C , the data capture signal DQS is selected as the indicator signal data. In addition, the data read command RD and the corresponding address information Addr can be transmitted from the host to the memory device through data or command signals IO[7:0]. In the read data DP1 of the first page, the data capture signal DQS is maintained in a static state. At the delay time t1, after the ECC operation for reading the data DP1 is completed, the data capture signal DQS is activated and starts to transition between logic high and low levels. The host can obtain the read data DP1 corresponding to the data capture signal DQS.

In FIG. 5B, the readout data DP2-DPn of the second to nth pages can be continuously read out. Since the read data DP2-DPn can be obtained from the corrected block data requiring only a short error correction time, the read data DP2-DPn can be sent out without delay time. The data capture signal DQS can be continuously transitioned.

In FIG. 5C , the read data DPn+1 is sent out, and the data capture signal DQS can be maintained at a low level when uncorrectable block data occurs until the error correction action performed on the page data is completed. In this page data, once the error correction action for the page data is completed, the block data that cannot be corrected and the read data DPn+2 corresponding to the remaining block data can acquire the signal with the re-transformed data. DQS is sent. Here, a longer delay time t2 is required to perform the error correction action of the page data. Then, the read data DPn+2 can be obtained based on the corrected page data.

It can be seen here that, in this embodiment, the read data can be sent according to the instruction signal, so that the host can obtain the read data correctly. Also, the data capture signal DQS can be dynamically adjusted based on the execution of the ECC action. And, the read delay of the memory device can be known by the host.

In FIGS. 6A to 6C , the wafer selection signal CS# is selected as the indication signal data. And when the read data is ready, a positive pulse can be generated on the chip select signal CS#, and the host can receive the read data by identifying the positive pulse on the chip select signal CS#. In FIG. 6A , the data read command RD and the corresponding address information Addr can be transmitted from the host to the memory device through data or command signals IO[7:0]. Then, after the delay time t1, the read data DP1 is ready, and a positive pulse is generated on the chip selection signal CS#. Then, the host can obtain the read data DP1 based on the clock signal SLCK.

In FIG. 6B, the read data DP1-DPn of the consecutive 1st to nth pages can be sequentially sent out according to the corrected block data without additional readout delay. The read data DP2-DPn can be sent without delay time. The chip select signal CS# in FIG. 6B is maintained at a logic low level.

In FIG. 6C, the read data DPn+1 is sent out, and the read data DPn+2 of the n+2th page is obtained by correcting the latter page data. After the delay time t2, the host can obtain the read data DPn+2 by identifying another positive pulse on the chip selection signal CS#.

In FIGS. 7A to 7C, the interrupt signal RDY/BY# is generated and selected as the indicator signal data. In this embodiment, the interrupt signal RDY/BY# is pulled down to a logic low level to indicate that the read data is not ready. On the other hand, when the read data is ready, the interrupt signal RDY/BY# is pulled to a logic high level to indicate that the read data is ready and available based on the clock signal SLCK.

In FIG. 7A , the data read command RD and the corresponding address information Addr can be transmitted from the host to the memory device through data or command signals IO[7:0]. Then, the interrupt signal RDY/BY# is pulled down to a logic low level to inform the host that the read data DP1 is not ready. After the delay time DP1, the interrupt signal RDY/BY# is pulled up to a logic high level, and the host can receive the read data DP1 of the first page of the memory device.

In FIG. 7B , the read data DP1 - DPn of the consecutive 1st to nth pages can be sequentially sent out according to the corrected block data without additional readout delay. The read data DP2-DPn can be sent without delay time. The interrupt signal RDY/BY# in FIG. 7B is maintained at a logic high level.

In FIG. 6C , after the read data DPn+1 is sent out, the read data DPn+2 of the n+2th page is obtained from the corrected page data, and the interrupt signal RDY/BY# is pulled low. After the delay time t2, the interrupt signal RDY/BY# is pulled high again, and the host can obtain the read data DPn+2 according to the clock signal SLCK.

In summary, the present invention divides page data into a plurality of blocks of data to reduce the size of data for performing error correction actions. Also, the error correction operation is performed for each block of data through the first error correction operation at high speed and with a low number of error correction bits. In this way, during the reading operation of the memory, the transmission delay of the read data caused by the error correction operation can be avoided, thereby effectively improving the working efficiency of the memory. Also, by providing an indicator signal, it can be determined that read data is available under conditions with different data delays due to different ECC operation conditions. In this way, the host can correctly obtain the read data according to the indication signal.

210, 410: Memory cell array 220, 310, 420: page buffer 230, 340, 470: Transmission interface 320, 441: The first cache 330, 442: Second cache 400: memory device 431: First ECC Circuit 432: Second ECC circuit 433: Third ECC circuit 440: Data register 450: Control Logic 460: Scratchpad CCH0~CCH3: Block data after correction CH0~CH3: block data CLK, SLCK: clock signal CS#: Chip Select Signal DQS: Data Capture Signal I/O, IO[7:0]: data or command signal PG0~PGn+1: Memory page RDY/BY#: interrupt signal t1, t2: delay time RD: data read command Addr: address information DP1~DPn+2: read data S110~S150, S310~S3110: Reading steps

FIG. 1 is a flowchart illustrating a method for reading a memory according to an embodiment of the present invention. FIG. 2 is a schematic diagram illustrating an operation of a method for reading a memory according to an embodiment of the present invention. 3A and 3B are flowcharts illustrating a method for reading a memory according to another embodiment of the present invention. FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention. 5A to 7C respectively illustrate waveform diagrams of read operations of the memory device according to different embodiments of the present invention.

S110~S150: Reading steps

Claims (19)

A method for reading a memory, comprising: reading a memory cell array to obtain a page of data; distinguishing the page of data into a plurality of blocks of data; sequentially performing a first error correction action for each of the blocks of data to generate respectively a plurality of corrected block data; outputting the corrected block data by referring to an indication signal; and when the first error correction operation fails, performing a second error correction operation on the data to generate a second corrected block data page information. The reading method of claim 1, wherein the error correction speed for each block of data is faster than the error correction speed for the page of data. The reading method of claim 1, wherein the error capability for each piece of material is lower than the error correction capability for the page of material. The reading method of claim 1, wherein the step of outputting the corrected block data or the page data by referring to the indication signal comprises: when the corrected block data are all correct, outputting the corrected block data block data until an uncorrectable block data occurs; and after the second error correction action is completed, output the remaining block data. The reading method of claim 1, wherein the first error correction action and the second error correction action are performed simultaneously. The reading method of claim 1, wherein the first error correction action and the second error correction action are performed in sequence. The reading method of claim 1, wherein a first error correction bit number of the first error correction action is 1 bit. The reading method according to claim 1, wherein the indication signal is an independent signal. The reading method of claim 1, wherein the indication signal is equivalent to a chip selection signal, a data capture signal or an interrupt signal. The reading method of claim 1, further comprising: performing a third error correcting action for the data of the page that cannot be corrected in the second error correcting action to obtain the corrected page data; and referring to the indication signal to output the The second corrected back page data is used as the read data, wherein the error correction capability of the third error correction action is higher than the error correction capability of the second error correction action. A memory device includes: a memory cell array; a page buffer, coupled to the memory cell array, the page buffer stores a page of data, wherein the page data is divided into a plurality of block data; a data register , used to temporarily store the block data; a transmission interface, coupled to the data register, referring to an indication signal to output a plurality of corrected block data; a first error correction circuit, coupled to the data register , perform a first error correction action for each block of data in sequence to generate the corrected block data respectively, a second error correction circuit, when the first correction operation fails, performs a second error correction operation on the page of data to respectively generate a corrected page of data; a control logic, coupled to the first error correction circuit and the The second error correction circuit is used for controlling the first error correction circuit and the second error correction circuit to perform the first error correction action and the second error correction action respectively. The memory device of claim 11, wherein the data register comprises: a first cache for temporarily storing the block data; and a second cache for temporarily storing the corrected blocks information or the information on the page after the correction. The memory device of claim 11, wherein the transmission interface outputs the corrected block data after the corrected block data until the uncorrectable block data occurs, and the transmission interface outputs the corrected block data after the second error action is completed Information on the back page. The memory device of claim 11, wherein the first error correction circuit performs the first error correction faster than the second error correction circuit performs the second error correction. The memory device of claim 11, wherein the error correction capability of the first error correction circuit is lower than the error correction capability of the second error correction circuit. The memory device of claim 11, wherein the control logic causes the first error correction action and the second error correction action to be performed simultaneously or sequentially. The memory device of claim 11, further comprising: A third error correction circuit performs a third error correction action for the page of data to generate a second corrected page of data. The memory device of claim 11, wherein the control logic generates the indication signal to indicate whether the read data is ready. The memory device of claim 11, wherein the indication signal is equivalent to a chip select signal, a data capture signal or an interrupt signal.

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