TWI753398B - Field-effect transistors with laterally-serpentine gates - Google Patents

Abstract

Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.

Description

Field effect transistor with laterally meandering gate

The present invention relates to semiconductor device fabrication and integrated circuits, and more particularly, to the structure of field effect transistors and methods of forming field effect transistors.

Device structures of field effect transistors typically include a body region, source and drain electrodes defined in the body region, and a gate configured to switch the current of carriers formed in a channel during operation in the body region electrode. When a control voltage exceeding a specified threshold voltage is applied to the gate electrode, the FET is turned "on" and carrier current occurs in the channel between the source and drain, resulting in a device output current.

Complementary metal-oxide semiconductor (CMOS) circuits can be used in mobile communication devices (eg, laptops, cell phones, tablet computers, etc.) to process high frequencies transmitted and/or received by the mobile communication device Signal. The circuitry on the chip may include a low noise amplifier and a high frequency switch to allow high frequency signals received by the antenna to be routed from the low noise amplifier to other chip circuits and to allow high frequency signals to be routed from the power amplifier to the antenna. The high frequency switch may comprise a stack or group of field effect transistors formed by a CMOS process.

The FET group may include a plurality of gate fingers having direct Lines are arranged in parallel. The source electrode and the drain electrode are arranged in the space between the adjacent gate fingers. Due to the parallel arrangement of the gate fingers in the straight line in the device layout, the FET stack may occupy a large area, making an inefficient use of the available space on the chip.

There is a need for improved field effect transistor structures and methods of forming field effect transistors.

In one embodiment, a field effect transistor structure is provided. The structure includes: a first gate electrode having a plurality of first segments arranged in series to define a first nonlinear chain; and a second gate electrode arranged adjacent to the first gate electrode. The second gate electrode includes a plurality of second segments arranged in series to define a second nonlinear chain. The plurality of second segments are laterally offset from the plurality of first segments of the first nonlinear chain of the first gate electrode. The structure further includes a source/drain region laterally disposed between the first gate electrode and the second gate electrode.

In one embodiment, a method of forming a field effect transistor is provided. The method includes: forming a first gate electrode, the first gate electrode including a plurality of first segments disposed in series to define a first nonlinear chain; and forming a second gate electrode disposed adjacent to the first gate electrode electrode. The second gate electrode includes a plurality of second segments arranged in series to define a second nonlinear chain. The plurality of second segments are laterally offset from the plurality of first segments of the first nonlinear chain of the first gate electrode. A source/drain region is laterally disposed between the first gate electrode and the second gate electrode.

10: Structure

12: Gate electrode

13: Top surface

14: Semiconductor substrate

16: Gate dielectric layer

18, 19: Fragments

20, 22: Sidewalls

21, 23: Vertical axis

24: Outside corners

25: Inside corner

24a, 25a: Angle

26: wide area, area

28: Narrow area, area

30: Sidewall spacers, spacers

32: source/drain area

34: silicide layer

36: Dielectric layer

38: Contact

40: Conformal layer

42: Etch Mask

44: Sacrificial Spacer

46: Part

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and are related to the general description of the invention made above and the implementation of the invention made below. The detailed description of the examples together serves to explain the described embodiments of the invention. In the drawings, like reference numerals are used to represent like features in the different views.

FIG. 1 shows a top view of a device structure at an initial manufacturing stage of a process method in accordance with an embodiment of the present invention.

FIG. 1A shows an enlarged view of the portion of FIG. 1, wherein the gate electrode angle is a right angle.

Figure 1B shows an enlarged view similar to Figure 1A of a portion of a gate structure in accordance with an alternative embodiment of the present invention, and wherein the gate electrode corners are chamfered.

Figure 2 shows a cross-sectional view taken generally along line 2-2 in Figure 1.

FIG. 3 shows a cross-sectional view of the device structure at a manufacturing stage subsequent to FIG. 2 .

FIG. 4 shows a cross-sectional view of the device structure at a manufacturing stage subsequent to FIG. 3 .

Figure 5 shows a simplified top view, wherein Figure 4 is generally taken along line 4-4.

6 shows a cross-sectional view of a device structure at an initial manufacturing stage of a process method in accordance with an alternative embodiment of the present invention.

Figures 7 and 8 show cross-sectional views of the device structure at a stage of continuous manufacturing subsequent to Figure 6 .

Figure 9 shows a cross-sectional view of a device structure at a manufacturing stage in accordance with an alternative embodiment of the present invention.

Figure 10 shows a cross-sectional view of a device structure at a manufacturing stage in accordance with an alternative embodiment of the present invention.

Referring to FIGS. 1 and 2 and according to an embodiment of the present invention, the structure 10 of the field effect transistor includes a gate electrode 12 as a set of fingers disposed on the top surface 13 of the semiconductor substrate 14 in an array. The semiconductor substrate 14 may be, for example, a bulk semiconductor wafer composed of a single crystal semiconductor material such as single crystal silicon, or a top crystalline film of a silicon-on-insulator (SOI) wafer. Doping wells (not shown) may be formed in the semiconductor substrate 14 . The doped well can be provided by ion implantation of dopants of a given conductivity type, such as boron to provide p-type conductivity for NFET wells and phosphorous to provide n-type conductivity for PFET wells. The gate electrode 12 and doped wells may be formed in the active device region of the semiconductor substrate 14 surrounded by shallow trench isolation (STI) regions (not shown). The STI region may, for example, surround the outer edges of the array of gate electrodes 12 to provide isolation from adjacent field effect transistors or from other adjacent active or passive devices.

A gate dielectric layer 16 is provided between each gate electrode 12 and the top surface 13 of the semiconductor substrate 14 . The gate dielectric layer 16 may be composed of a dielectric material, such as silicon dioxide grown by wet or dry thermal oxidation processes of the semiconductor material of the semiconductor substrate 14, or silicon dioxide deposited by atomic layer deposition. The gate electrode 12 may be composed of a doped semiconductor material such as doped polysilicon (eg, polysilicon) deposited by chemical vapor deposition. The gate electrode 12 may be formed by photolithography and etching processes that pattern the deposited layers of its constituent materials, as well as the deposited layers of materials that constitute the gate dielectric layer 16 . The photolithography process can form an etch mask comprising a layer of photosensitive material, such as an organic photoresist, applied by a spin coating process, pre-baked, exposed to light projected through the photomask, post-exposure bake baked, and developed with a chemical developer to form photoresist shapes covering corresponding areas on the deposited layer of the constituent material. These regions are masked during the etch process to provide gate electrodes 12 and gate dielectric layers 16 underlying each gate electrode 12 . Alternatively, gate dielectric layer 16 may be composed of a high-k dielectric material, such as hafnium oxide, and gate electrode 12 may be formed by, for example, a metal gate process or an alternative metal gate process composed of one or more metals.

The gate electrode 12 is patterned to form a plurality of segments 18, 19 arranged in succession, the segments exhibiting a directional offset relative to each other along their length such that each gate electrode 12 is non-linear. In one embodiment, this directional offset may occur in a given direction (eg, the x-direction) within the plane. Regions or portions of the semiconductor substrate 14 are exposed in the wide region 26 lying laterally between the segments 18 , 19 of adjacent gate electrodes 12 , and other regions or portions of the semiconductor substrate 14 are exposed to laterally lying adjacent gate electrodes 12 . In the narrow region 28 between the segments 18 . In one embodiment, the segments 18, 19 may have nominally the same length dimension along the length direction (eg, the y-direction). In one embodiment, the segments 18, 19 may have nominally the same width dimension along a direction in the plane perpendicular to the length direction (eg, the x-direction). This offset of the segments 18, 19 can give each gate electrode 12 an S-shape.

The consecutively arranged segments 18, 19 of each gate electrode 12 define a non-linear string or chain, wherein the alternating segments 18, 19 are laterally offset. The pattern of segments 18 , 19 along the length of the gate electrodes 12 is complementary to the pattern of each adjacent gate electrode 12 such that the segments 18 , 19 mirror between adjacent pairs of gate electrodes 12 . Each gate electrode 12 includes opposing sidewalls 20 , 22 that reflect the contours of the non-linear arrangement of segments 18 , 19 . The distance between the sidewall 20 and the opposite sidewall 22 of each gate electrode 12 defines the channel length in the underlying semiconductor substrate 14 . Segments 18 may be aligned along longitudinal axis 21 and segments 19 may be aligned along longitudinal axis 23 offset laterally from longitudinal axis 21 (ie, in the x-direction). The segments 18 , 19 of each gate electrode 12 are distributed to alternate in a respective non-linear chain between the alignment of the segments 18 along the longitudinal axis 21 and the alignment of the segments 19 along the longitudinal axis 23 .

This lateral displacement between the different linear chains causes the space between the nearest neighbor side walls 20 and 22 to have varying width dimensions. In particular, the sidewall 20 of one gate electrode 12 and the sidewall 22 of the adjacent nearest neighbor gate electrode 12 have a spacing associated with the wide region 26 and a different distance associated with the narrow region 28 The same spacing, the spacing associated with the narrow region 28 is smaller than the spacing associated with the wide region 26 . The side walls 20, 22 of each gate electrode 12 further comprise outer corners 24 and inner corners 25, where the segments 18, 19 have an overlapping arrangement. At each corner 24, 25, the corresponding side wall 20, 22 changes direction, and in one embodiment, the direction change may be approximately equal to a right angle (ie, 90°).

As shown in Figure 1B, the corners 24a, 25a of the gate electrode 12 may be chamfered to eliminate right angles and smooth the sidewalls 20, 22. This chamfering of the corners 24a, 25a of the gate electrode can be set during patterning by optical proximity correction, eg adding serifs to a photomask used during lithography. This angle chamfer can be used, for example, to keep the channel length more constant over the entire length of each gate electrode 12 .

Following this patterning of the gate electrode 12 , halo and source/drain extension regions (not shown) may be formed in the semiconductor substrate 14 . The annular region and source/drain extension regions may be formed by ion implantation of one or more dopants of a given conductivity type.

Please refer to FIG. 3, wherein similar reference numerals represent similar features in FIGS. 1 and 2, and in the next manufacturing stage, sidewall spacers 30 are formed at the sidewalls 20, 22 of the gate electrode 12. Conformal layers composed of dielectric materials such as silicon dioxide, silicon nitride, or low-k dielectric materials can be deposited by atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, etc., and by anisotropic A reactive etch process such as reactive ion etching etches the deposited layer to form sidewall spacers 30 . The deposition is controlled so that the conformal layer does not reach a thickness that would pinch the narrow region 28 . The anisotropic etch process may be an overlay etch process, which may be performed without a pre-applied etch mask, or may also be performed using a pre-applied etch mask. The sidewall spacers 30 follow this non-linear arrangement of the segments 18 , 19 , in particular the contours of the sidewalls 20 , 22 of the gate electrode 12 , with the lateral direction variation introduced by the lateral offset of the segments 18 , 19 .

Structure 10 further includes source/drain regions 32 of a given conductivity type, which form In the semiconductor substrate 14 adjacent to and on opposite sides of each gate electrode 12 and its sidewall spacers 30 . In particular, the source/drain regions 32 are formed in the regions 26 , 28 between the gate electrodes 12 and achieve this alternating width dimension along the length of the gate electrodes 12 . The source/drain regions 32 may be formed by introducing dopants into the semiconductor substrate 14 . In one embodiment, source/drain regions 32 may be formed by implanting ions containing the dopant into semiconductor substrate 14 under a given set of implant conditions (eg, ion species, dose, kinetic energy, tilt angle). . In one embodiment, source/drain regions 32 may include n-type dopant concentrations (eg, phosphorous, arsenic, and/or antimony) that provide n-type conductivity. The ions used to form the source/drain regions 32 can be generated from a suitable source gas and implanted into the semiconductor substrate 14 under the given set of implant conditions using an ion implantation tool. The given set of implant conditions can be selected to adjust the electrical and physical properties (eg, resistivity and depth profile) of the source/drain regions 32 .

Please refer to FIGS. 4 and 5, wherein similar reference numerals denote similar features in FIG. 3, and in the next manufacturing stage, the regions 26, A portion of the silicide layer 34 may be formed on the top surface 13 of the semiconductor substrate 14 in 28 . The silicide layer 34 has a lower resistance compared to the semiconductor substrate 14 and facilitates subsequent contact formation with the source/drain regions 32 . The silicide layer 34 may be formed by a self-aligned silicide process, including depositing a silicide-forming metal layer by, for example, chemical vapor deposition or physical vapor deposition, followed by one or more annealing steps (eg, rapid thermal annealing) to The silicide phase is formed by reacting the silicide-forming metal layer with the contacting semiconductor material of the semiconductor substrate 14 . Since the silicide-forming metal does not react with contacting dielectric materials such as sidewall spacers 30 , the silicide process is self-aligned with regions on the top surface 13 of the semiconductor substrate 14 in regions 26 , 28 . Candidate materials for the silicide-forming metal include, but are not limited to, nickel, titanium, cobalt, palladium, platinum, or combinations of these metals, or capable of reacting with semiconductor materials (eg, silicon) to form low resistivity thermally stable silicides of other metals. The silicide layer 34 may also be formed on the top surface of the gate electrode 12 part, or part of a different silicide layer.

Next, a middle-of-line (MOL) process and a back-end-of-line (BEOL) process are performed, which include forming contacts, via holes, and lines. The interconnect structure includes a dielectric layer 36 , and contacts 38 disposed in contact openings in the dielectric layer 36 as vertical interconnects extending to the source/drain regions 32 . Contacts (not shown) to connect to the portion of silicide layer 34 on gate electrode 12 may also be formed.

Contacts 38 are coupled to portions of silicide layer 34 in wide regions 26 laterally between segments 18 of adjacent gate electrodes 12 . Portions of silicide layer 34 may also be present in narrow regions 28 laterally between segments 18 of adjacent gate electrodes 12 that are not contacted.

The structure may be a switch configured as a multi-finger field effect transistor. The shape of the gate electrodes 12 may allow more gate electrodes 12 to be placed in a given device footprint with an area-optimized layout characterized by a high density of gate electrodes. This density increase is achieved while meeting ground rules for the layout, including but not limited to gate length, contact width, and minimum contact-gate spacing.

Please refer to FIG. 6 , where like reference numerals denote like features in FIG. 1 , and according to an alternative embodiment, sidewall spacers 30 may be formed on the sidewalls of gate electrode 12 with larger thicknesses in the next manufacturing stage. In particular, the conformal layer 40 may be deposited at a thickness sufficient to be sandwiched within the narrow regions 28 . Due to the narrowness of the narrow regions 28 compared to the wide regions 26 , the etch process that forms the sidewall spacers 30 does not fully etch the conformal layer 40 in the narrow regions 28 . The thickening of the sidewall spacers 30 does not interfere with the formation of the contacts 38 in the wide regions 26 .

After the sidewall spacers 30 are formed, an etch mask 42 may be formed over the semiconductor substrate 14 by photolithography. The etch mask 42 may include, for example, an organic photoresist layer applied by a spin-on process, prebaked, exposed to light projected through the photomask, post-exposure bake, and developed with a chemical developer, Thereby openings are defined at predetermined locations of the cuts to be formed in the conformal layer 40 in the narrow regions 28 . This cut is required to separate the conformal layer 40 into additional spacers 30 and to reopen the narrow regions 28 for subsequent formation of the silicide layer 34 .

Please refer to FIG. 7, where similar reference numerals denote similar features in FIG. 6, and in the next manufacturing stage, an etch process is used to remove the conformal layer over the portion of the narrow region 28 that is not masked by the etch mask 42 40 materials. The etching process may be an anisotropic etching process, such as reactive ion etching, selected to stop on the semiconductor material of the semiconductor substrate 14 . The size and placement of the openings in the etch mask 42 determine the size and location of the sidewall spacers 30 formed in the narrow regions 28 .

Please refer to FIG. 8, wherein similar reference numerals represent similar features in FIG. 7, and in the next manufacturing stage, the process is continued to form the source/drain regions 32, and then as described in conjunction with FIGS. 4 and 5, to complete the formation of the field effect transistor. The increased thickness of the sidewall spacers 30 can effectively reduce the size of the source/drain regions 32 .

Please refer to FIG. 9, wherein like reference numerals refer to like features in FIG. 1, and according to an alternative embodiment, sidewall spacers 30 are formed on the sidewalls of gate electrode 12, the thickness of which is selected so as not to sandwich narrow region 28 . After the sidewall spacers 30 are formed, the active device regions of the semiconductor substrate 14 may then be implanted with masked or unpatterned implants to dope the ring, extension, and/or source/drain regions 32 of the structure 10 . Sacrificial spacers 44 may then be formed adjacent to sidewall spacers 30 in wide regions 26 . Sacrificial spacers can be formed by depositing conformal layers of materials such as silicon dioxide, silicon nitride, or low-k dielectric materials by atomic layer deposition and etching the deposited layer using anisotropic etching processes such as reactive ion etching body 44. Portions 46 of the conformal layer are clamped inside the narrow regions 28 , filling and closing the spaces between the sidewall spacers 30 in the narrow regions 28 . The material of sacrificial spacer 44 is selected to allow selective removal relative to the material of sidewall spacer 30 . References herein to material removal processes (eg, etching) The term "selectivity" is used to indicate that the material removal rate (ie, etch rate) of a target material is higher than the material removal rate (ie, etch rate) of at least one other material exposed to the material removal process. In one embodiment, sidewall spacers 30 may be composed of silicon dioxide, sacrificial spacers 44 and portions 46 of the conformal layer may be composed of silicon nitride, and may be opposed to silicon dioxide without the need for photolithography and photomasking. The silicon nitride is selectively removed by using, for example, an aqueous phosphoric acid solution. As described in conjunction with FIGS. 4 and 5 , after the sacrificial spacer 44 is formed, the process is continued to complete the formation of the structure 10 of the field effect transistor.

Please refer to FIG. 10, wherein like reference numerals refer to like features in FIG. 9, and according to an alternative embodiment, after additional processing and before the formation of silicide layer 34, the sidewall spacers in narrow region 28 may be removed Sacrificial spacers 44 and portions 46 of the conformal layer are removed between 30 . As described in conjunction with FIGS. 4 and 5, the process is continued to complete the formation of the structure 10 of the field effect transistor. Similar to the widened spacers of FIGS. 6-8 , the temporarily increased thickness of sidewall spacers 30 due to the presence of sacrificial spacers 44 reduces the size of source/drain regions 32 .

The method as described above is used in the manufacture of integrated circuit chips. Manufacturers may distribute the resulting integrated circuit chips in raw wafer form (eg, as a single wafer with a plurality of unpackaged chips), as bare chips, or in packaged form. The chip may be combined with other chips, discrete circuit elements, and/or other signal processing devices as an intermediate product or part of an end product. The final product can be any product that includes an integrated circuit chip, such as a computer product with a central processing unit or a smart phone.

References herein to terms modified by approximate language such as "about," "approximately," and "substantially" are not limited to the precise value specified. The approximation language may correspond to the precision of the instrument used to measure the value, and unless relied on the precision of the instrument, may represent +/- 10% of the value.

Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a frame of reference, not limitation. The term "horizontal" as used herein is defined as being parallel to the conventional plane of the semiconductor substrate plane, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to the direction within the horizontal plane.

A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intervening features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intervening features may be present. A feature may be "directly on" or "directly in contact with" another feature if there are no intervening features. A feature may be "not directly on" or "not in direct contact with" another feature if at least one intervening feature is present.

Various embodiments of the present invention have been described for purposes of example, and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over techniques known in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

10: Structure

12: Gate electrode

13: Top surface

14: Semiconductor substrate

26: wide area, area

28: Narrow area, area

30: Sidewall spacers, spacers

32: source/drain area

Claims (20)

A structure of a multi-finger field-effect transistor, the structure includes: a first gate electrode, including a plurality of first segments arranged continuously to define a first nonlinear chain; a second gate electrode, adjacent to the first gate electrode Electrode arrangement, the second gate electrode includes a plurality of second segments arranged continuously to define a second nonlinear chain, the plurality of second segments are laterally offset from the first nonlinear chain of the first gate electrode a plurality of first segments, the plurality of second segments are spaced apart from the plurality of first segments of the first gate electrode to alternate between a first pitch and a second pitch smaller than the first pitch; source The source/drain region is laterally disposed between the first gate electrode and the second gate electrode, and the source/drain region includes between the plurality of first segments and the plurality of second segments with the first spacing a plurality of first regions therebetween, and the source/drain region includes a plurality of second regions between the plurality of first segments and the plurality of second segments having the second spacing; and a silicide layer having A plurality of first portions respectively located on the plurality of first regions of the source/drain region and a plurality of second portions respectively located on the plurality of second regions of the source/drain region. The structure of claim 1, further comprising: a contact level located above the first gate electrode, the second gate electrode, and the source/drain regions, the contact level including contacting the source/drain regions, respectively The plurality of contacts of the plurality of first regions of the drain region are coupled. The structure of claim 2, wherein the plurality of second regions of the source/drain regions are not in contact. The structure of claim 1, wherein the plurality of first segments of the first gate electrode include a plurality of corners defined by the plurality of first regions adjacent to the source/drain regions. The structure of claim 4, wherein each of the plurality of corners is chamfered. The structure of claim 1, wherein the first gate electrode has a first sidewall, the second gate electrode has a second sidewall, and the first sidewall of the first gate electrode is defined by the The first pitch or the second pitch is spaced apart from the second sidewall of the second gate electrode. The structure of claim 1, wherein the first gate electrode includes a sidewall having a profile that reflects a change in direction of the first nonlinear chain of the plurality of first segments, and further comprising: a sidewall a spacer adjacent the sidewall of the first gate electrode, the sidewall spacer being positioned to follow the contour of the sidewall of the first gate electrode. The structure of claim 1, wherein the plurality of first segments are distributed between alignment along a first longitudinal axis and alignment along a second longitudinal axis laterally offset from the first longitudinal axis alternating in the first non-linear chain. The structure of claim 1, wherein the plurality of second regions have a first width dimension, and the plurality of second regions have a second width dimension smaller than the first width dimension. The structure of claim 1, wherein the plurality of first segments of the first gate electrode and the plurality of second segments of the second gate electrode have nominally equal width dimensions. A method of forming a multi-finger field effect transistor, the method comprising: forming a first gate electrode, the first gate electrode comprising a plurality of first segments arranged in series to define a first nonlinear chain; forming adjacent to the first gate electrode a second gate electrode disposed with a gate electrode; a source/drain region laterally disposed between the first gate electrode and the second gate electrode; and A silicide layer formed on the source/drain regions, wherein the second gate electrode includes a plurality of second segments arranged in series to define a second nonlinear chain, and the plurality of second segments are opposite to the first gate The plurality of first segments of the electrode electrode are spaced apart to alternate between a first pitch and a second pitch smaller than the first pitch, the source/drain region including the plurality of first segments located at the first pitch A plurality of first regions between a segment and the plurality of second segments, and the source/drain region includes a plurality of first segments located between the plurality of first segments and the plurality of second segments with the second spacing two regions, and the silicide layer has a plurality of first parts respectively located on the plurality of first regions of the source/drain region and a plurality of second parts respectively located on the plurality of second regions of the source/drain region part. The method of claim 11, wherein the first gate electrode includes a first sidewall having a first profile that reflects a change in direction of the first nonlinear chain of the plurality of first segments, and Further comprising: forming a first sidewall spacer adjacent the first sidewall of the first gate electrode, wherein the first sidewall spacer is positioned to follow the first sidewall of the first gate electrode first outline. The method of claim 12, wherein the second gate electrode includes a second sidewall having a second profile that reflects a change in direction of the second nonlinear chain of the plurality of second segments, the The second sidewall of the second gate electrode is disposed adjacent to the first sidewall of the first gate electrode, and further includes: forming a second sidewall spacer adjacent to the second sidewall of the second gate electrode, wherein the second sidewall spacer is disposed to follow the second contour of the second sidewall of the second gate electrode. The method of claim 13, wherein the plurality of second regions have a first width dimension, and the plurality of second regions have a second width dimension smaller than the first width dimension. The method of claim 13, wherein forming the first sidewall spacer adjacent to the first sidewall of the first gate electrode comprises depositing a dielectric layer filling the source / the space between the first sidewall and the second sidewall above the plurality of second regions of the drain region; and patterning the dielectric layer in the space by photolithography and etching The first sidewall spacers are formed in two regions. The method of claim 13, wherein forming the first sidewall spacer adjacent to the first sidewall of the first gate electrode comprises: the plurality of second sidewalls in the source/drain region depositing a dielectric layer over regions including a first portion on the first sidewall and a second portion on the second sidewall; and the first portion of the dielectric layer and the dielectric in the plurality of second regions Sacrificial spacers are formed in the spaces between the second portions of the electrical layer. The method of claim 16, further comprising: removing the sacrificial spacer from each space, wherein after removing the sacrificial spacer from each space, forming the silicide layer on the source/drain region. The method of claim 11, further comprising: forming a contact level over the first gate electrode, the second gate electrode, and the source/drain region, wherein the contact level comprises The plurality of contacts of the plurality of first regions of the source/drain regions are coupled. The method of claim 11, wherein the first gate electrode includes sidewalls, and the first gate electrode is formed including the plurality of first segments arranged in series to define the first nonlinear chain The method includes: patterning the plurality of first segments to have chamfered corners at the direction change of the sidewall of the first gate electrode generated by the first non-linear chain. The method of claim 11, wherein the source/drain regions are formed by ion implantation.

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