TWI751944B - Chip packaging structure - Google Patents

Abstract

A chip packaging method and a chip packaging structure are disclosed. The disclosed chip packaging method includes: forming a protective layer having material properties on an active surface of a die; mounting the die whose active surface is formed with the protective layer on a carrier, wherein the active surface faces the carrier, the back surface faces away from the carrier; forming a plastic sealing layer having material properties for encapsulating the die; peeling the carrier to expose the protective layer; forming a conductive layer and a dielectric layer; the packaging method can reduce or eliminate the warpage in the panel packaging process, reduce the precision requirement on the dies on the panel, reduce the difficulty of the panel packaging process, and make the packaged chip structure have a durable lifetime, especially suitable for large panel-level package and large electric flux, thin chip package.

Description

Chip package structure

The present disclosure relates to the field of semiconductor technology, and in particular, to a chip packaging method and a packaging structure.

Panel-level package is to cut a wafer to separate a large number of dies, arrange and paste the dies on a carrier board, and package the many dies simultaneously in the same process flow. As a technology emerging in recent years, panel-level packaging has received extensive attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost and suitable for mass production.

However, there are many technical barriers in panel packaging, such as the problem of warpage of the panel and the accuracy of die alignment on the panel.

Especially in the current trend of small and lightweight electronic equipment, small and thin chips are increasingly favored by the market. However, the packaging process of using large panel packaging technology to package small and thin chips cannot be underestimated.

The present disclosure aims to provide a semiconductor chip packaging method and a chip packaging structure, the packaging method can reduce or eliminate warpage during the panel packaging process, reduce the precision requirements of the die on the panel, reduce the difficulty of the panel packaging process, and The packaged chip structure has a durable service cycle, and is especially suitable for large-scale panel-level packaging and packaging of large electric flux and thin chips.

The present disclosure provides a chip package structure, comprising: at least one die; a protective layer formed on the active surface of the die, and a conductive filled through hole is formed in the protective layer, at least a part of the conductive filled through hole and at least a part of the conductive filled through hole are formed in the protective layer. A part of the electrical connection points are electrically connected; a plastic sealing layer is used to encapsulate the die; a conductive layer is formed at least partially on the surface of the protective layer, and the conductive layer is connected to at least a part of the conductive filling. The holes are electrically connected; the dielectric layer is formed on the conductive layer.

In one embodiment, the Young's modulus of the protective layer is any one of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa.

In one embodiment, the material of the protective layer is an organic/inorganic composite material.

In another embodiment, the thickness of the protective layer is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, 50 μm.

In yet another embodiment, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In another preferred embodiment, the protective layer and the plastic sealing layer have the same or similar thermal expansion coefficients.

In yet another preferred embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm.

In an advantageous embodiment, the diameter of the inorganic filler particles is 1-2 μm.

In an advantageous embodiment, the conductively filled via is formed by an opening of a conductive medium filled protective layer, the conductively filled via has a lower surface of the conductively filled via and an upper surface of the conductively filled via, and the lower surface of the conductively filled via is formed. The area ratio of the surface to the upper surface of the conductive filled via is 60%-90%.

In an advantageous embodiment, there is a gap between the lower surface of the conductively filled via and the insulating layer, and/or the lower surface of the conductively filled via is located near the center of the electrical connection point.

In a preferred embodiment, the protective layer opening is a protective layer opening formed by laser patterning.

In another preferred embodiment, the conductive layer includes conductive traces and/or conductive bumps; wherein: at least a part of the conductive traces closest to the active surface of the die is formed on the surface of the protective layer, and the The conductive filled vias are electrically connected; the conductive bumps are formed on the pads or connection points of the conductive traces.

In yet another preferred embodiment, the conductive layer is one or more layers.

In a preferred embodiment, a conductive cover layer is formed on the electrical connection points.

In an advantageous embodiment, the thickness of the conductive cover layer is 2-3 μm.

In an advantageous embodiment, the conductive capping layer is a Cu layer.

In a preferred embodiment, at least a portion of the conductive traces closest to the active surface of the die are formed on the front side of the molding layer and extend to the edge of the package body.

In a preferred embodiment, the backside of the die is exposed from the molding layer.

In a preferred embodiment, the surface of the dielectric layer has grooves at positions corresponding to the conductive layers.

In a preferred embodiment, the at least one die is a plurality of die, and the plurality of die is electrically connected according to product design.

In a preferred embodiment, the plurality of dies are dies with different functions to form a multi-chip module.

The present disclosure provides a chip packaging method, comprising: forming a protective layer on a die active surface of a die; mounting the die on which the protective layer is formed on the die active surface on a carrier, and the die active surface is facing the carrier board, the back of the die faces away from the carrier board; forming a plastic encapsulation layer for encapsulating the die; peeling off the carrier board to expose the protective layer.

In one embodiment, forming the protective layer on the active surface of the die includes: forming the protective layer on the active surface of the wafer, and dicing the wafer on which the protective layer is formed into a plurality of dies with the protective layer.

In one embodiment, the material of the protective layer is an organic/inorganic composite material.

In one embodiment, the Young's modulus of the protective layer is any one of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500 MPa .

In one embodiment, the thickness of the protective layer is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, and 50 μm.

In another embodiment, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In one embodiment, the thermal expansion coefficient of the plastic sealing layer is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In yet another embodiment, the protective layer and the plastic sealing layer have the same or similar thermal expansion coefficients.

In a preferred embodiment, the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1 to 2 μm.

In another preferred embodiment, the step of forming a protective layer opening on the protective layer is further included, and the ratio of the lower surface of the protective layer opening to the area of the upper surface of the protective layer opening is 60%-90%.

In a preferred embodiment, the protective layer openings are formed by laser patterning.

In yet another preferred embodiment, the method further includes the step of thinning the backside of the plastic encapsulation layer to expose the backside of the die.

In a preferred embodiment, the method further includes the step of forming grooves at positions corresponding to the conductive layer on the dielectric layer by metal etching.

In a preferred embodiment, the step of subjecting the wafer and/or the surface of the protective layer to plasma surface treatment and/or chemically accelerated modifier treatment is further included.

In a preferred embodiment, an electroless plating process step is further included on the active surface of the wafer to form a conductive cover layer on the electrical connection points.

In order to make the technical solutions of the present disclosure clearer and the technical effects clearer, the preferred embodiments of the present disclosure will be described and explained in detail below with reference to the accompanying drawings. public restrictions.

1 to 12 are flowcharts of a chip packaging method proposed according to an exemplary embodiment of the present disclosure.

As shown in FIG. 1, at least one wafer 100 is provided, the wafer 100 has a wafer active surface 1001 and a wafer back surface 1002, the wafer 100 includes a plurality of dies 113, wherein the active surface of each die constitutes a The active surface 1001 of the wafer is formed, and the active surface of each die in the wafer 100 is formed by a series of processes such as doping, deposition, and etching to form a series of active components and passive components. The active components include diodes, triodes Passive components include voltages, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form functional circuits, thereby realizing various functions of the chip. The wafer active surface 1001 further includes an electrical connection point 103 for drawing out the functional circuit and an insulating layer 105 for protecting the electrical connection point 103 .

Preferably, an electroless plating process step is performed on the active surface 1001 of the wafer to form a conductive cover layer on the electrical connection points 103 . Optionally, the conductive cover layer is one or more layers of Cu, Ni, Pd, Au, Cr; preferably, the conductive protective layer is a Cu layer; the thickness of the conductive protective layer is preferably 2-3 μm. The conductive cover layer is not shown in FIG. 1 . The conductive cover layer can protect the electrical connection points 103 on the active surface 1001 of the wafer from laser damage in the subsequent steps of forming the protective layer openings.

As shown in FIG. 2 , a protective layer 107 is applied on the active surface 1001 of the wafer.

In one embodiment, the protective layer is applied to the active surface 1001 of the wafer by lamination.

Optionally, before the step of applying the protective layer 107 on the active surface of the wafer 1001, the active surface 1001 of the wafer and/or the protective layer 107 is applied on the side of the wafer 100. Physical and/or chemical treatment to make the bonding between the protective layer 107 and the wafer 100 tighter. Optionally, the treatment method is plasma surface treatment to roughen the surface to increase the bonding area and/or chemical promotion modifier treatment, and a promotion modification group is introduced between the wafer 100 and the protective layer 107, For example, surface modifiers with both organic affinity and affinity inorganic groups increase the adhesion between organic/inorganic interface layers.

The protective layer 107 can be used to protect the active surface 1131 of the die. In the subsequent molding process, due to the molding pressure, the molding material flowing under the heating condition tends to penetrate into the gap between the die 113 and the carrier 117 , destroying the circuit on the active surface 1131 of the die. When the surface 1131 has a protective layer, the protective layer 107 can protect the active surface 1131 of the die from infiltrating the molding material so as to protect the active surface 1131 of the die from damage.

The existence of the protective layer 107 can also make the adhesion between the die 113 and the adhesive layer 121 stronger, so that during the plastic sealing process, the plastic sealing pressure is not easy to cause the die 113 to be stuck on the carrier board. A position shift occurs on 117.

In a preferred embodiment, the Young's modulus of the protective layer 107 is in the range of 1000-20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000-10000 MPa; further preferred The Young's modulus of the protective layer 107 is 1000-7000, 4000-7000 or 4000-8000 MPa; in the preferred embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.

In a preferred embodiment, the thickness of the protective layer 107 is in the range of 15-50 μm; more preferably, the thickness of the protective layer is in the range of 20-50 μm; in a preferred embodiment, the protective layer The thickness of the protective layer 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in another preferred embodiment, the thickness of the protective layer 107 is 50 μm.

When the Young's modulus value of the protective layer 107 is in the range of 1000-20000MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient support Acting force makes the protective layer 107 have sufficient support for the conductive layer on its surface. Meanwhile, when the thickness of the protective layer 107 is 15-50 μm, it is ensured that the protective layer 107 can provide sufficient buffer and support.

Especially in some types of chips, it is necessary to use thin die for packaging, and the conductive layer needs to reach a certain thickness to form a large electric flux. In this case, the thickness of the protective layer 107 is selected to be in the range of 15-50 μm , the value range of the Young's modulus of the protective layer 107 is 1000-10000MPa. The soft and flexible protective layer 107 can form a buffer layer between the die 113 and the conductive layer, so that the conductive layer will not press the die excessively during the use of the wafer. The grains 113 are prevented from being broken by the pressure of the thick conductive layer. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.

When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa, and the thickness of the protective layer 107 is 20-50 μm, due to the The material properties of the protective layer 107 enable the protective layer 107 to effectively protect the die against the thimble pressure of the die transfer equipment in the subsequent die transfer process.

The die transfer process is a process of rearranging and adhering the cut and separated die 113 to the carrier plate 117 (reconstruction process). The die transfer process requires the use of a bonder machine, which includes an ejector pin. , the die 113 on the wafer 100 is lifted up by an ejector pin, and the lifted die 113 is sucked up by a bonder head, transferred and bonded to the carrier board 117 .

During the process of ejecting the crystal grains 113 by the ejector pins, the crystal grains 113, especially the thin-type crystal grains 113, are brittle and are easily broken by the ejection pressure of the ejector pins. The protective layer 100 with material characteristics can protect the brittle crystal grains in this process. The grains 113 can maintain the integrity of the crystal grains 113 even under a relatively large jacking pressure.

In a preferred embodiment, the protective layer 107 is an organic/inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO ₂ particles; in one embodiment, the filler particles in the protective layer 107 are two or more different types inorganic oxide particles such as SiO ₂ TiO ₂ particles mixed. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, are spherical or spherical-like. In a preferred embodiment, the filling amount of filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO ₂ particles, such as SiO ₂ mixed TiO ₂ particles, is more than 50%.

The organic material has the advantages of easy operation and application. The die 113 to be encapsulated is made of an inorganic material such as silicon. When the protective layer 107 is made of an organic material alone, due to the difference between the material properties of the organic material and the material properties of the inorganic material , it will make the packaging process difficult and affect the packaging effect. The use of organic/inorganic composite materials in which inorganic particles are added to organic materials can modify the material properties of organic materials, so that the materials have both the characteristics of organic materials and inorganic materials.

In a preferred embodiment, when (T<Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm/K; in a preferred embodiment; the thermal expansion coefficient of the protective layer 107 is 7 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm/K.

In the ensuing molding process, the die 113 to which the protective layer 107 is applied will expand and contract correspondingly during the heating and cooling process of the molding process. When the thermal expansion coefficient of the protective layer 107 is in the range of 3-10 ppm/K , the degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent, the connection interface between the protective layer 107 and the die 113 is not easy to generate interface stress, and it is not easy to destroy the combination between the protective layer 107 and the die 113. The wafer structure is more stable.

In the process of using the packaged chip, it is often necessary to undergo cold and thermal cycles. The thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm/K and the die 113 has the same or similar thermal expansion coefficient. During the cold and thermal cycle, the protective layer 107 Maintaining a relatively consistent expansion and contraction degree with the die 113 , avoiding the accumulation of interface fatigue at the interface between the protective layer 107 and the die 113 , making the packaged chip durable and prolonging the service life of the chip.

On the other hand, if the thermal expansion coefficient of the protective layer is too small, it is necessary to fill the composite material of the protective layer 107 with too many filler particles, which will further reduce the thermal expansion coefficient and also increase the Young's modulus of the material, so that the protective layer material is The flexibility is reduced, the stiffness is too strong, and the buffering effect of the protective layer 107 is not good. It is optimal to limit the thermal expansion coefficient of the protective layer to 5-10 ppm/k.

In a preferred embodiment, the diameter of the filler particles in the protective layer 107 , such as inorganic oxide particles, such as SiO ₂ particles is less than 3 μm, preferably the filler particles in the protective layer 107 , such as inorganic oxide particles , for example _{, the diameter of SiO 2} particles is between 1 and 2 μm.

The diameter of the filler particles is controlled to be less than 3 μm, which is beneficial to forming a protective layer opening with smooth sidewalls on the protective layer 107 in the laser patterning process, so that the material can be fully filled in the conductive material filling process to avoid having a large size The concave-convex protective layer opening sidewall 109c cannot be filled with conductive material behind the sidewall shielded by the protrusions, which affects the conductivity of the conductive filled via 111 .

At the same time, the filling size of 1-2 μm will expose the filler with small particle size during the laser patterning process, so that the sidewall 109c of the opening of the protective layer has a certain roughness. The contact surface is larger and the contact is tighter, and the conductive filled through hole 111 with good conductivity is formed.

The diameter size of the above-mentioned filler is the average value of the particle diameter.

In a preferred embodiment, the tensile strength of the protective layer 107 ranges from 20 to 50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.

Optionally, after the process of applying the protective layer 107 on the active surface 1001 of the wafer, the back surface 1002 of the wafer is ground and thinned to a desired thickness.

Modern electronic devices are small and lightweight, and wafers tend to be thinned. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, the processing and transfer of thin wafers 100 are difficult, and grinding The thinning process is difficult, and it is often difficult to thin the wafer 100 to a desired thickness. When the surface of the wafer 100 has the protective layer 107 , the protective layer 107 with material properties will support the wafer 100 , thereby reducing the difficulty of processing, transferring and thinning the wafer 100 .

As shown in FIG. 3 a , a protective layer opening 109 is formed on the surface of the protective layer 107 .

A protective layer opening 109 is formed at a position of the protective layer 107 corresponding to the electrical connection point 103 on the wafer active surface 1001 to expose the electrical connection point 103 on the wafer active surface 1001 .

Preferably, there is a one-to-one correspondence between the protective layer openings 109 and the electrical connection points 103 on the active surface 1001 of the wafer.

Optionally, each of the protective layer openings 109 in at least a part of the protective layer openings 109 corresponds to a plurality of the electrical connection points 103 .

Optionally, at least a part of the electrical connection points 103 corresponds to a plurality of the protective layer openings 109 .

Optionally, at least a part of the protective layer openings 109 do not have corresponding electrical connection points 103 , or at least a part of the electrical connection points 103 do not have corresponding protective layer openings 109 .

Preferably, the protective layer opening is formed by laser patterning.

In the process flow of forming the protective layer opening 109 by laser patterning, the conductive cover layer formed on the electrical connection point 103 in the electroless plating process step can protect the electrical connection point 103 on the active surface 1001 of the wafer from being damaged by the laser.

Preferably, as shown in the partial enlarged view in FIG. 3a, there is a gap between the lower surface 109a of the protective layer opening and the insulating layer 105, and/or the lower surface 109a of the protective layer opening is close to the electrical connection point 103 central location.

In a preferred embodiment, the shape of the protective layer opening 109 is such that the area of the upper surface 109b of the protective layer opening is larger than the area of the lower surface 109a of the protective layer opening, and the ratio of the area of the lower surface 109a of the protective layer opening to the area of the upper surface 109b of the protective layer opening 60%~90%.

At this time, the inclination of the sidewall 109c of the protective layer opening can facilitate the filling of the conductive material. During the filling process, the conductive material will be uniformly and continuously formed on the sidewall.

Optionally, as shown in FIG. 3b, a conductive medium is filled in the protective layer opening 109, so that the protective layer opening 109 becomes a conductively filled through hole 111, and at least a part of the conductively filled through hole 111 is connected to the wafer. The electrical connection points 103 on the active surface 1001 are electrically connected. The conductively filled vias 111 extend the electrical connection points 103 on the active surface of the wafer 1001 to the surface of the protective layer unilaterally, and the protective layer is formed around the conductively filled vias 111 . The conductive medium can be gold, silver, copper, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metals A deposition process is formed to form conductive filled vias 111 in the protective layer openings 109 .

The filling of the conductive medium may be to completely fill the protective layer opening 109 , or it may be to form only a layer of conductive material in the protective layer opening 109 , which can be electrically connected to the conductive layer. Correspondingly, the conductive filled via 111 is understood as long as the protective layer opening 109 has a conductive medium that can be electrically connected to the conductive layer, and it is not necessary to completely fill the protective layer opening 109 .

By forming the protective layer opening 109 on the protective layer 107 in advance and/or filling the conductive medium, the position of the electrical connection point 103 on the active surface 1001 of the wafer can be accurately positioned through the protective layer opening 109, and the protective layer opening 109 area It can be made smaller, and the spacing between the openings can also be smaller, so that in the subsequent conductive layer forming step, the conductive traces can be tighter, and there is no need to worry about the positional deviation of the electrical connection point 103 .

As shown in FIG. 4 , the wafer 100 on which the protective layer 107 has been applied is cut along the dicing lines to obtain a plurality of die 113 formed with the protective layer. The die 113 has a die active surface 1131 and a die back surface 1132.

In one embodiment, the die 113 is formed by dicing the wafer 100 with the protective layer 107 as shown in FIG. 2 .

In one embodiment, the die 113 is formed by dicing the wafer 100 with the protective layer 107 and the protective layer openings 109 as shown in FIG. 3a.

In one embodiment, the die 113 is formed by dicing the wafer 100 with the protective layer 107 and the conductively filled vias 111 as shown in FIG. 3b.

Due to the material properties of the protective layer 107 , in the dicing process of the wafer 100 , the separated dies 113 are free of burrs and die chips.

In one embodiment, before the step of dicing the wafer 100 to separate the die 113 , the method further includes performing plasma surface treatment on the side of the wafer 100 having the protective layer 107 applied with the protective layer 107 , The surface roughness is increased to increase the adhesion of the die 113 on the carrier plate 117 in the subsequent process, and it is difficult to cause the die movement of the die 113 under the molding pressure.

It can be understood that, if the process allows, the wafer 100 can be selectively cut into the die 113 to be packaged according to the actual situation, and then the die active surface 1131 of each die 113 to be packaged is cut. form a protective layer.

As shown in FIG. 5a, a carrier 117 is provided, the carrier 117 has a carrier front 1171 and a carrier back 1172, and the divided die 113 are arranged on preset positions of the carrier front 1171 , the active surface 1131 of the die faces the carrier 117 , and the back surface 1132 of the die is arranged away from the carrier 117 .

The shape of the carrier board 117 is: circle, triangle, quadrilateral or any other shape. The size of the carrier board 117 can be a wafer substrate of small size, or a rectangular carrier board of various sizes, especially large size. The material of 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a large-sized quadrilateral panel made of stainless steel.

The carrier board 117 has a carrier board front side 1171 and a carrier board back side 1172, and the carrier board front side 1171 is preferably a plane.

In one embodiment, the die 113 is bonded and fixed on the carrier board 117 by using the adhesive layer 121 .

The adhesive layer 121 may be formed on the front surface 1171 of the carrier board by lamination, printing, spraying, coating, or the like. In order to facilitate the separation of the carrier board 117 and the back-molded die 113 in the subsequent process, the adhesive layer 121 is preferably made of an easily separable material, for example, a thermal separation material is used as the adhesive layer 121 .

Preferably, the position where the die 113 is arranged can be pre-marked on the carrier board 117 , and the marking can be formed on the carrier board 117 by means of laser, mechanical engraving, etc. At the same time, the die 113 is also provided with an alignment mark. , so as to be aligned with the pasting position on the carrier board 117 when pasting.

Optionally, as shown in FIG. 5b, in one encapsulation process, a plurality of dies 113a and 113b with different functions, two of which are shown in the figure, or more than two, may be assembled according to The actual product requirements are arranged on the carrier board 117 and packaged, and after the package is completed, it is cut into a plurality of packages; thus, one package includes a plurality of the dies 113a and 113b to form a multi-chip module (multi-chip module, MCM), and the positions of the plurality of the dies 113a and 113b can be freely set according to the needs of the actual product.

The form of the die 113 arranged on the carrier 117 may be the die 113 cut from the wafer 100 with the protective layer 107 as shown in FIG. 2 .

It can also be the die 113 cut from the wafer 100 with the protective layer 107 and the protective layer opening 109 as shown in FIG. After 113 is pasted on the adhesive layer 121 of the carrier board 117 , the protective layer opening 109 is in a hollow state.

It can also be a die 113 cut from the wafer 100 with the protective layer 107 and the conductive filled vias 111 as shown in FIG. 3 b .

As shown in FIG. 6 , the molding layer 123 is formed.

A plastic encapsulation layer 123 is formed around the to-be-packaged die 113 and the exposed surface of the front surface 1171 of the carrier board or the adhesive layer 121 . The plastic encapsulation layer 123 is used to completely encapsulate the front surface 1171 of the carrier board and the die 113 to be packaged, so as to reconstruct a flat structure, so that after the carrier board 117 is peeled off, the next steps can be performed on the reconstructed flat structure. packaging steps.

The surface of the plastic sealing layer 123 in contact with the front surface 1171 of the carrier or the adhesive layer 121 is defined as the front surface 1231 of the plastic sealing layer. The side of the plastic sealing layer 123 facing away from the front surface 1171 of the carrier or the adhesive layer 121 is defined as the back surface 1232 of the plastic sealing layer.

Preferably, the front surface 1231 of the plastic sealing layer and the back surface 1232 of the plastic sealing layer are substantially flat and parallel to the front surface 1171 of the carrier board.

In one embodiment, the plastic sealing layer 123 is formed by using an organic/inorganic composite material by molding.

Preferably, the thermal expansion coefficient of the plastic sealing layer 123 is 3-10 ppm/K; in a preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 5 ppm/K; in another preferred embodiment, the plastic sealing layer The thermal expansion coefficient of 123 is 7 ppm/K; in another preferred embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is 10 ppm/K.

Preferably, the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients.

The thermal expansion coefficient of the plastic sealing layer 123 is selected to be 3~10 ppm/K and the thermal expansion coefficient of the selected protective layer 107 is the same or similar. During the heating and cooling process of the plastic sealing process, the expansion and contraction between the protective layer 107 and the plastic sealing layer 123 The two materials are not easy to produce interface stress, and the low thermal expansion coefficient makes the thermal expansion coefficients of the plastic sealing layer, the protective layer and the die close to each other, so that the interfaces of the plastic sealing layer 123, the protective layer 107 and the die 113 are closely combined to avoid the occurrence of an interface. layer separation.

In the process of using the packaged chip, it is often necessary to undergo cold and heat cycles. Since the thermal expansion coefficients of the protective layer 107 , the plastic sealing layer 123 and the die 113 are similar, during the cooling and heating cycle, the protective layer 107 and the plastic sealing layer 123 and the die 113 have similar thermal expansion coefficients. The interface fatigue is small, and the interface gap is not easy to appear between the protective layer 107 , the plastic sealing layer 123 and the die 113 , so that the service life of the chip is increased, and the chip can be applied in a wide range of fields.

The difference in thermal expansion coefficient between the die 113 and the plastic encapsulation layer 123 will also cause warpage of the panel element after plastic encapsulation. Due to the warping phenomenon, it is difficult to locate the die 113 accurately in the panel element in the subsequent conductive layer forming process. The position has a great influence on the formation process of the conductive layer.

In particular, in the large-panel packaging process, due to the large size of the panel, even a slight panel warpage will cause the die of the outer and surrounding parts of the panel far from the center to have a larger size than before molding. Therefore, in the large-scale panel packaging process, solving the warpage problem has become one of the keys to the entire process. The warpage problem even limits the enlarged development of the panel size and becomes a technical barrier in the large-scale panel packaging.

The thermal expansion coefficients of the protective layer 107 and the plastic sealing layer 123 are limited within the range of 3 to 10 ppm/K, and preferably the plastic sealing layer 123 and the protective layer 107 have the same or similar thermal expansion coefficients, which can effectively The warpage of panel components is avoided, and the packaging process using large panels is realized.

At the same time, in the process of plastic sealing, since the plastic sealing pressure will generate pressure on the back of the die 113 , the pressure is easy to press the die 113 into the adhesive layer 121 , so that the die 113 is trapped in the process of forming the plastic sealing layer 123 . In the adhesive layer 121, after the plastic sealing layer 123 is formed, the die 113 and the front surface 1231 of the plastic sealing layer are not in the same plane, and the surface of the die 113 protrudes beyond the front surface 1231 of the plastic sealing layer, forming a stepped structure. During the formation of the conductive layer, the conductive traces 125 also have a stepped structure correspondingly, which makes the package structure unstable.

When the active surface 1131 of the die has a protective layer 107 with material properties, it can play a buffering role under the plastic sealing pressure to prevent the die 113 from sinking into the adhesive layer 121, thereby avoiding the generation of a stepped structure on the front surface 1231 of the plastic sealing layer.

As shown in FIG. 7a, the thickness of the plastic sealing layer 123 can be reduced by grinding or polishing the back surface 1232 of the plastic sealing layer.

In one embodiment, as shown in FIG. 7 b , the thickness of the plastic encapsulation layer 123 may be reduced to the backside 1132 of the die 113 , thereby exposing the backside 1132 of the die. The packaged chip structure is shown in Figure 13b.

As shown in FIG. 8 , the carrier plate 117 is peeled off to expose the front surface 1231 of the plastic sealing layer and the protective layer 107 .

In one embodiment, when the die 113 arranged on the carrier board 117 is in the form of die 113 having a protective layer 107 and a protective layer opening 109 as shown in FIG. 3a, the carrier board is peeled off. 1172, the protective layer opening 109 is also exposed.

In one embodiment, when the die 113 arranged on the carrier 117 is in the form of having the protective layer 107 as shown in FIG. 2 but a protective layer has not been formed on the protective layer 107 When the die 113 is cut from the open wafer 100 , after the carrier plate 117 is peeled off, there is a step of forming a protective layer opening on the protective layer 107 on the die 113 covered by the plastic sealing layer 123 .

In one embodiment, when the die 113 arranged on the carrier board 117 is in the form of die 113 cut from the wafer 100 with the protective layer 107 and the conductive filled vias 111 as shown in FIG. The conductive filled vias 111 are exposed.

The structure of the plastic encapsulation layer 123 coated with the die 113 after the carrier plate 117 is separated is defined as a panel module 150 .

FIGS. 9 and 10 illustrate an embodiment of a process of forming conductively filled vias on the die 113 in the molding layer 123 and patterning the conductive layer.

When the protective layer 107 covering the surface of the die 113 in the plastic encapsulation layer 123 has not yet formed conductive filled vias 111 , the protective layer openings 109 are filled with a conductive medium, so that the protective layer openings 109 become conductive filled vias 111 , the conductive filled vias 111 are electrically connected to the electrical connection points 103 on the active surface 1001 of the wafer. The conductively filled vias 111 extend the electrical connection points 103 on the active surface of the wafer 1001 to the surface of the protective layer unilaterally, and the protective layer is formed around the conductively filled vias 111 . The conductive medium can be gold, silver, copper, tin, aluminum and other materials or a combination of materials, or other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metals A deposition process is formed to form conductive filled vias 111 in the protective layer openings 109 .

The filling of the conductive medium may be to completely fill the protective layer opening 109 , or it may be to form a layer of conductive material only in the protective layer opening 109 , which can be electrically connected to the conductive layer. Correspondingly, the conductive filled via 111 is understood as long as the protective layer opening 109 has a conductive medium that can be electrically connected to the conductive layer, and it is not necessary to completely fill the protective layer opening 109 .

A conductive trace 125 is formed on the die 113 in the plastic encapsulation layer 123; at least a part of the conductive trace 125 is formed on the surface of the protective layer 107 on the active surface 1131 of the die, and at least a part of the conductive filling The through holes 111 are electrically connected; in one embodiment, the conductive traces 125 extend along the surface of the protective layer 107 and the front side 1231 of the plastic encapsulation layer, and extend to the edge of the packaged chip package when the package is completed. The packaged chip structure is shown in the figure 13b. The conductive traces 125 extend to the edge of the package body. At this time, the conductive traces 125 cover and connect the interface between the protective layer 107 and the plastic packaging layer 123 , which increases the stability of the packaged chip structure.

The conductive traces 125 may be one or more layers of copper, gold, silver, tin, aluminum, etc. materials or combinations thereof, or may be other suitable conductive materials by utilizing PVD, CVD, sputtering, electrolytic plating, electroless plating processes , or other suitable metal deposition processes.

Preferably, the conductive filling of the vias 111 and the conductive traces 125 is performed in the same conductive layer forming step.

Of course, alternatively, the conductive filled vias 111 are formed first, and then the conductive traces 125 are formed.

FIG. 10 shows the formation of conductive studs 127 on the pads or connection points of the conductive traces 125; the shape of the conductive studs 127 may be round or other shapes such as oval, square, line, etc. . The conductive bumps 127 can be one or more layers of copper, gold, silver, tin, aluminum and other materials or a combination of materials, or can be other suitable conductive materials by using PVD, CVD, sputtering, electrolytic plating, electroless plating process , or other suitable metal deposition processes.

The conductive layer is composed of conductive traces 125 and/or conductive bumps 127, and the conductive layer may be one layer or multiple layers. The conductive layer may function as a fan-out RDL.

As shown in Figures 11a and 11b, a dielectric layer 129 is formed on the conductive layer.

One or more dielectric layers 129 are formed on the surface of the conductive layer using lamination, coating, spraying, printing, molding, and other suitable methods.

The dielectric layer 129 can be BCB (benzocyclobutene), PI (polyimide), PBO (polybenzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide , alumina, polymer matrix dielectric film, organic polymer film; can also be organic composite materials, resin composite materials, polymer composite materials, polymer composite materials, such as epoxy resin with filler, ABF, or Other polymers for suitable fillers; other materials with similar insulating and structural properties are also possible. In a preferred embodiment, the dielectric layer 129 is ABF. The dielectric layer 129 functions to protect the conductive layer and to insulate. In one embodiment, the thickness of the dielectric layer 129 is thicker than that of the conductive layer, and the conductive layer is exposed through the grinding process; in another embodiment, the thickness of the dielectric layer 129 is the same as the thickness of the conductive layer, The conductive layer is just exposed after the dielectric layer 129 is applied.

In one embodiment, the steps of FIG. 9 to FIG. 11 b are repeated to form a multi-layer conductive layer on the die active surface 1131 of the die 113 .

Return to the steps of Figures 9 to 11b. In one embodiment, the forming step of the conductive layer may be: forming conductive traces 125 on the die active surface 1131 of the die 113; Using lamination, coating, spraying, printing, molding and other suitable methods to form one or more dielectric layers 129 on the surface of the conductive traces 125, the height of the dielectric layer 129 is higher than the height of the conductive traces 125, and the conductive traces 125 are formed. traces 125 are completely encapsulated in dielectric layer 129; and Openings are formed on the dielectric layer 129 at locations corresponding to pads or connection points of the conductive traces 125, and conductive bumps 127 are formed within the openings.

In yet another embodiment, the conductive bumps 127 may not be formed in the opening, so that the solder pads or connection points of the conductive traces 125 of the completed package are exposed from the opening.

In a preferred embodiment, after the step of applying the dielectric layer 129, the thickness of the outermost conductive layer is reduced by etching to form a groove 131 on the outer surface of the dielectric layer 129. The packaged chip structure is shown in FIG. 13b .

Optionally, as shown in FIG. 11b, in one encapsulation process, multiple, especially multiple dies 113a and 113a with different functions, two of which are shown in the figure, or more than two, may be encapsulated. As a multi-chip package module, the pattern design of the conductive layers of the plurality of dies 113a and 113b is designed according to the electrical connection requirements of the actual product. The packaged chip structure is shown in Figure 13c.

As shown in FIG. 12 , the packaged monomers are separated by dicing to form a packaged wafer, which can be diced by machine or laser.

13a, 13b and 13c are schematic diagrams of a chip package structure.

13a is a schematic diagram of a chip package structure obtained by the packaging method provided according to an exemplary embodiment of the present disclosure.

As shown in the figure, a chip package structure includes: a die 113, the die 113 includes a die active surface 1131 and a die back surface 1132, and the die active surface 1131 includes an electrical connection point 103 and an insulating layer 105; The protective layer 107 is formed on the active surface 1131 of the die, and a conductive filled via 111 is formed in the protective layer 107, and at least a part of the conductive filled via 111 is electrically connected to at least a part of the electrical connection points 103, used to lead out at least a part of the electrical connection points 103 from the active surface 1131 of the die; a plastic encapsulation layer 123, the plastic encapsulation layer 123 is used to encapsulate the die 113; a conductive layer, at least partially formed on the protection On the surface of the layer 107 , the conductive layer is electrically connected to at least a part of the conductive filled vias 111 ; the dielectric layer is formed on the conductive layers 125 and 127 .

In one embodiment, the Young's modulus of the protective layer 107 is any one of the following numerical ranges or values: 1000-20000 MPa, 1000-10000 MPa, 4000-8000 MPa, 1000-7000 MPa, 4000-7000 MPa, 5500MPa.

In one embodiment, the material of the protective layer 107 is an organic/inorganic composite material.

In one embodiment, the thickness of the protective layer 107 is any one of the following numerical ranges or values: 15-50 μm, 20-50 μm, 35 μm, 45 μm, and 50 μm.

In one embodiment, the thermal expansion coefficient of the protective layer 107 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, 10 ppm/K.

In one embodiment, the thermal expansion coefficient of the plastic sealing layer 123 is any one of the following numerical ranges or values: 3-10 ppm/K, 5 ppm/K, 7 ppm/K, and 10 ppm/K.

In one embodiment, the protective layer 107 and the plastic sealing layer 123 have the same or similar thermal expansion coefficients.

In one embodiment, the protective layer 107 includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm or the diameter of the inorganic filler particles is 1˜2 μm.

In one embodiment, the area ratio of the lower surface 111a of the conductively filled via to the area of the upper surface 111b of the conductively filled via is 60%˜90%.

In one embodiment, the conductive filled vias 111 are formed by the conductive dielectric filled protective layer openings 109 .

In one embodiment, a conductive cover layer is formed on the electrical connection points 103 .

In one embodiment, as shown in the partially enlarged view in FIG. 13 a , there is a gap between the lower surface 111 a of the conductive filled via and the insulating layer 105 .

In one embodiment, as shown in the enlarged partial view in FIG. 13 a , the lower surface 111 a of the conductive filled via is located near the center of the electrical connection point 103 .

In one embodiment, the conductive layer includes conductive traces 125 and/or conductive bumps 127; wherein: at least a part of the conductive traces 125 closest to the active surface 1131 of the die is formed on the surface of the protective layer 107, It is electrically connected to the conductive filled vias 111 .

The conductive bumps 127 are formed on pads or connection points of the conductive traces 125 .

The conductive layer may be one layer or multiple layers.

In one embodiment, as shown in FIG. 13b , at least a portion of the conductive traces 125 closest to the active surface 1131 of the die is formed on the front side 1231 of the molding layer and extends to the edge of the package body.

In yet another embodiment, as shown in FIG. 13 b , the backside 1132 of the die is exposed from the molding layer 123 .

In yet another embodiment, as shown in FIG. 13b, the surface of the dielectric layer 129 has grooves at positions corresponding to the conductive layers.

In one embodiment, as shown in FIG. 13c, the package structure includes a plurality of die 113, and the plurality of die 113 are electrically connected according to product design. Optionally, the plurality of die 113 are die with different functions to form a multi-chip module.

Fig. 14a shows a schematic diagram of the packaged wafer in use. During use, the packaged wafer is connected to a circuit board or substrate 161 by solder 160, and then connected to other circuit elements.

When the surface of the dielectric layer 129 of the package chip has the groove 131, the solder 160 can be connected stably and not easily moved.

FIG. 14b shows a schematic diagram of the packaged chip module in use. During use, the packaged chip module is connected to the circuit board or substrate 161 through solder 160, and then connected to other circuit elements.

The specific embodiments described above are intended to further describe the technical solutions and technical effects of the present disclosure in detail, but those skilled in the art will understand that the specific embodiments described above are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the inventive idea of the present disclosure should be included within the protection scope of the present disclosure.

100: Wafer 1001: Wafer Active Surface 1002: Wafer backside 103: Electrical connection point 105: Insulation layer 107: Protective layer 109: Protective layer opening 109a: Lower surface of protective layer opening 109b: upper surface of protective layer opening 109c: Protective layer opening sidewall 111: Conductive Filled Vias 111a: Conductive filled via lower surface 111b: conductive filled via upper surface 113: Die 113a: grain 113b: grain 1131: Grain Active Surface 1132: Die backside 117: carrier board 1171: front side of carrier board 1172: Back of carrier board 121: Adhesive layer 123: Plastic layer 1231: Front of plastic layer 1232: The back of the plastic layer 125: Conductive traces 127: conductive bump 129: Dielectric layer 131: Groove 150: Panel Module 160: Solder 161: Substrate

1 to 12 are flowcharts of a chip packaging method proposed according to an exemplary embodiment of the present disclosure; 1 is a schematic diagram of a semiconductor wafer in accordance with an exemplary embodiment of the present disclosure; 2 is a schematic diagram of a semiconductor wafer after applying a protective layer according to an exemplary embodiment of the present disclosure; 3a is a schematic diagram of a semiconductor wafer with protective layer openings formed in accordance with an exemplary embodiment of the present disclosure; 3b is a schematic diagram of a semiconductor wafer with conductive filled vias formed in accordance with an exemplary embodiment of the present disclosure; 4 is a schematic diagram of dicing a semiconductor wafer to form a die with a protective layer according to an exemplary embodiment of the present disclosure; FIG. 5a is a schematic diagram of pasting die on a carrier according to an exemplary embodiment of the present disclosure; FIG. 5b is a schematic diagram of a die combination attached to a carrier according to an exemplary embodiment of the present disclosure; 6 is a schematic diagram of forming a plastic encapsulation layer on a carrier according to an exemplary embodiment of the present disclosure; FIG. 7a is a schematic diagram of reducing the thickness of the plastic sealing layer according to an exemplary embodiment of the present disclosure; 7b is a schematic diagram of thinning the plastic encapsulation layer to expose the backside of the die according to an exemplary embodiment of the present disclosure; 8 is a schematic diagram of peeling off the carrier plate and the adhesive layer in accordance with an exemplary embodiment of the present disclosure; 9 is a schematic diagram of forming conductive filled vias and conductive traces on a panel module according to an exemplary embodiment of the present disclosure; 10 is a schematic diagram of forming conductive bumps on a panel module according to an exemplary embodiment of the present disclosure; 11a and 11b are schematic diagrams of forming a dielectric layer on a panel module according to an exemplary embodiment of the present disclosure; 12 is a schematic diagram of cutting a panel module to form a packaged wafer according to an exemplary embodiment of the present disclosure; 13a is a schematic diagram of a chip package structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; 13b is a schematic diagram of a chip package structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; 13c is a schematic diagram of a chip module package structure obtained by using the above-mentioned packaging method according to an exemplary embodiment of the present disclosure; 14a is a schematic diagram of a packaged wafer in use according to an exemplary embodiment of the present disclosure; FIG. 14b is a schematic diagram of a packaged chip module in use according to an exemplary embodiment of the present disclosure.

103: Electrical connection point

105: Insulation layer

107: Protective layer

111: Conductive Filled Vias

113: Die

1131: Grain Active Surface

1132: Die backside

123: Plastic layer

1231: Front of plastic layer

1232: The back of the plastic layer

125: Conductive traces

127: conductive bump

129: Dielectric layer

131: Groove

Claims (16)

A chip package structure, comprising: at least one die; a protective layer, located on one side of the active surface of the die, and the side of the protective layer is flush with the side of the die, and a conductive filling through hole is formed in the protective layer a hole, at least a part of the conductive filled through hole is electrically connected to the electrical connection point; a plastic sealing layer, the plastic sealing layer is used to encapsulate the die; a conductive layer, at least partially formed on the surface of the protective layer, at least a part of the conductive layer It is electrically connected with the conductive filled through hole; and a dielectric layer is formed on the conductive layer; wherein, the Young's modulus of the protective layer is in the range of 1000-20000 MPa. According to the chip package structure of claim 1, the material of the protective layer is an organic/inorganic composite material. According to the chip package structure of claim 1, the thickness of the protective layer is in the range of 15-50 μm. According to the chip package structure of claim 1, the thermal expansion coefficient of the protective layer is in the range of 3-10 ppm/K. According to the chip packaging structure of claim 1, the thermal expansion coefficient of the plastic packaging layer is in the range of 3-10 ppm/K. The chip package structure according to claim 1, wherein the protective layer and the plastic sealing layer have the same or similar thermal expansion coefficients. The chip package structure according to claim 2, wherein the protective layer includes inorganic filler particles, and the diameter of the inorganic filler particles is less than 3 μm. The chip package structure according to claim 1, wherein the conductively filled through hole is formed by filling an opening of a protective layer with a conductive medium, the conductively filled through hole has a lower surface of the conductively filled through hole and an upper surface of the conductively filled through hole, the conductively filled through hole is formed The ratio of the area of the lower surface of the through hole to the upper surface of the conductively filled through hole is 60% to 90%. According to the chip package structure of claim 8, there is a gap between the lower surface of the conductively filled through hole and the insulating layer, and/or the lower surface of the conductively filled through hole is located at a position close to the center of the electrical connection point. The chip package structure according to any one of claims 1 to 9, wherein the conductive layer includes conductive traces and/or conductive bumps; wherein at least a part of the conductive traces closest to the active surface of the die is formed on the protection The surface of the layer is electrically connected to the conductive filled via. The chip package structure according to any one of claims 1 to 9, wherein a conductive cover layer is formed on the electrical connection point. The chip package structure of claim 10, at least a part of the conductive traces closest to the active surface of the die is formed on the front surface of the plastic encapsulation layer and extends to the edge of the package body. The chip package structure according to any one of claims 1 to 9, wherein the backside of the die is exposed from the plastic sealing layer. The chip package structure according to any one of claims 1 to 9, wherein a surface of the dielectric layer has a groove at a position corresponding to the conductive layer. The chip package structure according to any one of claims 1 to 9, wherein the at least one die is a plurality of die, and the plurality of die is electrically connected according to product design. The chip package structure according to any one of claims 1 to 9, wherein the plurality of dies are dies with different functions to form a multi-chip module.

Images