TWI751501B - Control setting method for link state transition and electronic device using the same - Google Patents

Abstract

A link state transition method and an electronic device are provided. The link state transition method includes: setting a first ITPT from an operation mode into a low power consumption mode link state in an ASPM of a storage device, wherein the first ITPT is less than or equal to a second ITPT from the operation mode into a non-operation mode in an APST of the storage device; and applying the first ITPT of the ASPM to the storage device after a rebooting operation.

Description

The control setting method of link state transition and the method of using this method electronic device

The present disclosure relates to a link state transition method and an electronic device, and more particularly, to a link state transition method and an electronic device for avoiding the problem of link state transition.

Most of the current fast non-volatile memory solid state drives (Non-Volatile Memory Express Solid State Drive, NVMe SSD) support Active State Power Management (Active State Power Management, ASPM), and ASPM is used for consumer notebook computers. Language is also an important function. However, in the definition of the Peripheral Component Interconnect (PCI) specification, ASPM is a behavior triggered by the hardware (ie, the storage controller) autonomously. The host does not need to control the ASPM behavior of the SSD. ASPM enables PCIe SSD to switch from working mode to low-power mode by switching its PCIe link to low-power mode under certain circumstances, so as to achieve To reduce the power consumption of the entire link. The low power modes defined by ASPM include L0s and L1. L0s is a faster sleep mode to enter and exit, while L1 is a slower but less power-efficient mode to enter and leave.

NVMe relies on its own Timeout mechanism to determine the timing of entering L0s and L1. However, the current ASPM relies entirely on NVMe-initiated designs that are not ideal. If NVMe enters the low-power mode autonomously for its own power saving requirements or performance requirements, it will affect the system to some extent. For example, a poorly designed mechanism for an SSD to enter L1 autonomously may cause the system to fail to wake up and cause a Blue Screen of Death (BSoD), and frequent SSD entry into L1 may also lead to poor system performance. Therefore, how to solve the related problems derived from ASPM is the goal of those skilled in the art.

In view of this, the present disclosure provides a link state transition method and electronic device to avoid the problem of link state transition.

The present disclosure provides a link state transition method, including: setting a first pre-transition idle time from an operating mode to a low-power mode link state in active state power management of a storage device, wherein the first pre-transition idle time is less than or equal to the storage device a second pre-transition idle time from an operating mode to a non-operational mode in an autonomous power state transition of the device; and applying the first pre-transition idle time of active state power management to the storage device after a reboot operation.

The present disclosure provides an electronic device including a processor; and a storage device coupled to the processor. The processor sets a first pre-transition idle time from the operating mode to the low-power mode link state in the active state power management of the storage device, wherein the first pre-transition idle time is less than or equal to the transition from the operating mode in the autonomous power state of the storage device entering a second pre-transition idle time of a non-operational mode; and applying the first pre-transition idle time of active state power management to the storage device after a power cycle operation.

Based on the above, the link state transition method and electronic device of the present disclosure will set the idle time before the first transition from the operation mode to the low power mode link state in the active state power management to be less than or equal to the autonomous power state transition through the system side The second pre-transition idle time from the operating mode to the non-operational mode is applied, and the first pre-transition idle time is applied to the storage device. In this way, the problem caused by ASPM's reliance on NVMe's independent initiation can be solved.

100: Electronics

110: Processor

120: no device for storage

S201~S202: steps of the link state transition method

FIG. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure.

FIG. 2 is a flowchart of a link state transition method according to an embodiment of the present disclosure.

FIG. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure.

Please refer to FIG. 1 , an electronic device 100 according to an embodiment of the present disclosure includes a processor 110 and the storage device 120 are coupled to the processor 100 . The electronic device 100 is, for example, a personal computer, a notebook computer, a smart phone, a tablet computer, or other similar devices. The processor 110 is, for example, a central processing unit, a microprocessor or other similar devices. The storage device 120 is, for example, a solid state drive (eg, NVMe SSD, PCIe SSD, etc.) or other similar devices.

Table 1 is an example of the APST mechanism corresponding to the storage device 120 . The fast non-volatile memory power state PS0 corresponds to the normal operating mode and PS1 and PS2 correspond to the operating modes that may be throttled due to overheating of the system. Through the interaction between ITPS and ITPT, the storage device 120 can enter the non-operation mode for a certain period of time under the system to save power consumption.

In one embodiment, the processor 110 may set the active state power management (ASPM) of the storage device 120 to enter the low power mode link state from the operating mode (eg For example, the first idle time before transition (ITPT) of L1 or L1.2), wherein the first idle time before transition is less than or equal to the second time from the operation mode to the non-operation mode in the autonomous power state transition (APST) of the storage device 120 Idle time before conversion. The first pre-transition idle time of active state power management may be applied to the storage device 120 after a power cycle operation. The settings of the ITPT timeout parameters corresponding to APST and ASPM can be described with reference to Table 2 below.

Table 2 is an example of the APST mechanism and the ASPM mechanism corresponding to the storage device 120 . In one embodiment, ITPT_L1 and ITPT_L1.2 are PCIe link status timeout parameters for the storage device 120 to refer to in the operation mode. Storage device 120 must comply with The ITPT_L1 or ITPT_L1.2 link state can be entered only according to the timeout parameter set by the system of the electronic device 100 . It is worth noting that the ITPT_L1 corresponding to ASPM cannot be greater than the ITPT corresponding to APST, because the link state is the mechanism for entering shallow sleep in operation mode, if the timeout parameter corresponding to the ASPM link state is greater than the timeout parameter corresponding to the APST power state As a result, the storage device 120 cannot enter deep sleep. Therefore, if the system side mistakenly sets the ITPT_L1 of the ASPM to be greater than the ITPT of the APST, the storage device 120 can directly set the ITPT_L1 of the ASPM to be equal to the ITPT of the APST to avoid errors. The timeout parameter corresponding to ITPT_L1.2 is 0, which means that the storage device 120 is not allowed to enter the PCIe link state L1.2 under the power state of PS0/PS1/PS2. Through the link state conversion method of the present disclosure, different NVMe link states can be set in different system states, instead of only following the settings of the Basic Input Output System (BIOS) in the AC mode or the DC mode Timeout to uniformly enter PCIe link state L1 or PCIe link state L1.2.

In one embodiment, the processor 110 can obtain the current ITPS and ITPT status through a get feature of NVMe. When the system side needs to additionally set ITPS and ITPT, it can be set through the set feature of NVMe. For example, a system application can call an Intel Rapid Storage Technology (RST) application to create new ITPT_L1, ITPT_L1.2 timeout parameters, and time out the new ITPT_L1, ITPT_L1.2 when the system is rebooted The parameters are applied to the storage device 120 .

FIG. 2 is a flowchart of a link state transition method according to an embodiment of the present disclosure.

Referring to FIG. 2, in step S201, set the idle time before the first transition from the operating mode to the link state of the low power consumption mode in the active state power management of the storage device, wherein the idle time before the first transition is less than or equal to the storage device's idle time A second pre-transition idle time from an operating mode to a non-operating mode in an autonomous power state transition.

In step S202, the first pre-transition idle time of the active state power management is applied to the storage device after the reboot operation.

To sum up, the link state transition method and electronic device of the present disclosure will set the idle time before the first transition from the operation mode to the low power consumption mode link state in the active state power management to be less than or equal to the autonomous power supply through the system side The idle time before the second transition from the operation mode to the non-operation mode in the state transition is applied, and the first idle time before the transition is applied to the storage device. In this way, the problem caused by ASPM's reliance on NVMe's independent initiation can be solved.

Although the present disclosure has been disclosed above with examples, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure shall be determined by the scope of the appended patent application.

S201~S202: steps of the link state transition method

Claims (10)

A link state transition method, comprising: Setting a first Idle Time Prior to Transition (ITPT) in an Active State Power Management (ASPM) of a storage device from an operating mode to a low-power mode link state, wherein the first pre-transition idle time is less than or equal to a second pre-transition idle time from the operation mode to a non-operation mode in an Autonomous Power State Transition (APST) of the storage device; and The first pre-transition idle time of the active state power management is applied to the storage device after a reboot operation. The link state transition method according to claim 1, wherein the low power consumption mode link state includes a peripheral component interconnect express (PCIe) link state L1 and a fast peripheral component interconnect link In state L1.2, when the low power consumption mode link state is the fast peripheral element interconnection link state L1.2, the idle time before the second transition is zero. The link state transition method of claim 1, wherein the operation mode includes a fast non-volatile memory (Non-Volatile Memory Express, NVMe) power state (Power State) PS0, a fast non-volatile memory power supply State PS1 and a fast non-volatile memory power state PS2, and the non-operational mode includes a fast non-volatile memory power state PS3 and a fast non-volatile memory power state PS4. The link state transition method of claim 3, wherein when the operation mode is the fast non-volatile memory power state PS0, the first pre-conversion idle time is less than the second pre-conversion idle time, and when the operation When the mode is the fast non-volatile memory power state PS1 or the fast non-volatile memory power state PS2, the first pre-conversion idle time is equal to the second pre-conversion idle time. The link state transition method of claim 1, wherein the active state power management corresponds to an alternating current mode and a direct current mode. An electronic device, comprising: a processor; and a storage device coupled to the processor, wherein the processor Setting a first pre-transition idle time from an operating mode to a low-power mode link state in an active state power management of a storage device, wherein the first pre-transition idle time is less than or equal to an autonomous power supply of the storage device a second pre-transition idle time from the operating mode to a non-operating mode in state transitions; and The first pre-transition idle time of the active state power management is applied to the storage device after a reboot operation. The electronic device of claim 6, wherein the low power mode link state includes a fast peripheral element interconnect link state L1 and a fast peripheral element interconnect link state L1.2, when the low power consumption mode When the link state is the fast peripheral element interconnection link state L1.2, the idle time before the second transition is zero. The electronic device of claim 6, wherein the operation mode includes a fast non-volatile memory power state PS0, a fast non-volatile memory power state PS1 and a fast non-volatile memory power state PS2, and the non-volatile memory power state PS2 The operating modes include a fast non-volatile memory power state PS3 and a fast non-volatile memory power state PS4. The electronic device of claim 8, wherein when the operation mode is the fast non-volatile memory power state PS0, the first pre-conversion idle time is less than the second pre-conversion idle time, when the operation mode is the In the fast non-volatile memory power state PS1 or the fast non-volatile memory power state PS2, the first pre-conversion idle time is equal to the second pre-conversion idle time. The electronic device of claim 6, wherein the active state power management corresponds to an alternating current mode and a direct current mode.

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