TWI750650B - Emissive display substrate for surface mount micro-led fluidic assembly and method for making same - Google Patents

Abstract

Emissive display substrate for surface mount (SM) micro light emitting diodes (μLEDs) and a method for making the emissive display substrate are provided. The emissive display substrate includes: a support substrate with a planar top surface and a LED cross-point control matrix including an array of column and row conductive lines; a first thin-film layer overlying the support substrate top surface and including a plurality of wells. Each well has a convex bottom surface, a first substrate electrode connected to a corresponding column line, and a second substrate electrode connected to a corresponding row line.

Description

Light-emitting display substrate for surface mount micro LED fluid assembly and preparation method

The present invention relates generally to display technology, and more particularly to the design of surface mount (SM) inorganic micro light emitting diodes (μLEDs) with improved surface flatness of electrode interfaces.

Color displays consist of pixels that emit light of three wavelengths corresponding to visible light red, green, and blue, and are called RGB displays. The RGB components of a pixel are turned on and off in an orderly fashion to add up to produce the colors of the visible spectrum. There are several display types that can generate RGB images in different ways. Liquid crystal displays (LCDs) are the most popular technology, and they produce RGB images by illuminating a white light source (usually a phosphor-generated white LED) with a color filter of sub-pixels. Some parts of the wavelengths of white light are absorbed, while others are transmitted through the color filter through the color filter. Organic Light Emitting Diode (OLED) displays generate RGB light by directly emitting light at each of those wavelengths at the pixel level from within the organic light emitting material. Organic Light Emitting Diode (OLED) displays generate RGB light by directly emitting light at each of those wavelengths at the pixel level from within the organic light emitting material.

The third display technology is micro LED displays. The display technology uses micron-scale (10 to 150 μm in diameter) inorganic LEDs to directly emit pixel-level light. To make an RGB display using micro-LEDs, a large-area array of three different types of micro-LEDs emitting separately in each RGB wavelength range has to be assembled. Low-cost fabrication of microLED displays requires the use of massively parallel fluidic assembly techniques to place millions of individual microLEDs in a regular array. in the column. Current mainstream TVs with HDTV resolution have 6 million pixels, while the higher resolution 4K and 8K standards have 25 and 99 million pixels, respectively.

To produce high-yield, low-cost displays with appropriate brightness, fluidic assembly techniques place some unique requirements on micro-LED structures, some of which will be discussed in this article. Practical display technology must address the reality that displays are manufactured in different sizes and resolutions, thus requiring flexibility in pixel size, from 300 pixels per inch (ppi) for personal devices to very large 10-20ppi for large public information display applications . Display brightness requirements also vary by application, ranging from 300 nits (candela per square meter) for mobile phone displays, 1,000 nits for televisions, and 5,000 nits for outdoor information displays. Therefore, micro-LED technology must accommodate a wide range of resolution and brightness requirements, while still maintaining the physical properties necessary for assembly using fluids.

The development of gallium nitride (GaN)-based blue LEDs for general lighting and aluminum gallium phosphide (AlGaInP) red LEDs for various indicator lights has progressed over many generations and these processes can be produced at very low cost Reliable and efficient device. Therefore, perhaps the most important requirement is that the micro-LED structure be compatible with conventional metal-organic chemical vapor deposition (MOCVD) fabrication of commercial inorganic LEDs. There are many possible variants in LED manufacturing, so this overview only provides a very brief overview to identify the factors required to manufacture high-quality LEDs, while also describing the differences between conventional LEDs and the micro LEDs described here unique difference. By Zhang and Liu (Ning Zhang and Zhiqiang Liu, "InGaN Material Systems and Blue/Green Emitters", in Li, Jinmin, Zhang, GQ (eds), Light Emitting Diodes, Solid State Lighting Technology and Applications Series 4 (Springer, Switzerland, 2019)) and AlGaInP-based red LEDs by Wang et al. (Guohong Wang, Xiaoyan Yi, Teng Zhan, and Yang Huang, "AlGaInP/AlGaAs material systems and red/yellow LEDs", in Li, Jinmin, Zhang, GQ ( ed), Light Emitting Diodes, Solid State Lighting Technologies and Applications Series 4 (Springer, Switzerland, inventors: Schuele, Zhan, Sasaki, Ulmer and Lee 2019) is a useful summary of known LED technology in the visible spectrum.

1A to 1C are diagrams depicting GaN LED wafers for general lighting purposes (Prior Art). GaN-based LEDs emitting blue light (about 440 nanometers (nm)) and green light (about 530 nm) were fabricated in a series of complex high temperature MOCVD steps to produce the vertical LED structure shown in cross section of Figure 1A. Fabrication is performed on polished sapphire, silicon (Si), or silicon carbide (SiC) growth substrates 50 to 200 millimeters (mm) in diameter. The surface is prepared by depositing an optional AIN buffer layer and undoped GaN to produce a crystalline surface with low defects and GaN lattice constant. The thickness and temperature of this initial deposition are adjusted to compensate for the lattice mismatch between the growth substrate and GaN. Surface weight increases with thickness, so high-efficiency devices are thicker than about 3 micrometers (μm). Since the MOCVD deposition process is complex and expensive, it is important to optimize the micro LED process to make the most efficient use of the entire area of the growth wafer (growth substrate).

After the initial growth to prepare the crystalline GaN surface, a first LED layer was grown and Si doping was added to produce n+ GaN (n-GaN) for the cathode. Optionally, the stack may include layers tuned for electron injection and hole blocking. Next, the indium gallium nitride _{(In x Ga 1-x N} ) and depositing alternating layers of GaN multiple quantum well (MQW) structure in which indium content and thickness of the layer determines the wavelength of the emitted light of the device. The increase in indium content shifts the emission peak to longer wavelengths, but since lattice mismatch also increases internal stress, high-efficiency GaN devices cannot be fabricated for red light-emitting devices, and green light-emitting devices are less efficient than blue light-emitting devices efficiency of LEDs. After MQW, the stack can include layers tuned for electron blocking and hole injection. Finally, the MOCVD sequence is completed by depositing magnesium (Mg) doped GaN to form a p+ anode.

The finished substrate is then patterned and etched to form individual LEDs, and additional processing is performed to form electrodes on the anode and cathode, as shown in Figure IB. In the simplest process flow, _{a thin layer of nickel oxide (NiO x} ) is deposited to match the p+GaN (p-GaN) work function, followed by a 100 to 300 nm thick layer of indium tin oxide (ITO). A transparent conductive electrode is formed. This layer is patterned and etched to form a current spreading layer over the anode.

A small area is patterned and etched through the stack to make contact with the n+GaN. A passivation layer, typically silicon dioxide (SiO ₂ ), is deposited to prevent leakage currents between the anode and cathode and to open contact windows over the electrodes. Electrodes (usually made of titanium/aluminum (Ti/Al)) are deposited to form the cathode contact, and a second electrode is added which may be nickel/gold (Ni/Au), chromium/gold (Cr/Au), etc. (anode). The substrate is thinned to about 100 μm by grinding, and individual devices are singulated by dicing or sawing. Devices fabricated by this process are typically 100 μm thick and 150 to 1000 μm in size (cross-section), eg, as shown in FIG. 1C .

2A and 2B are diagrams illustrating a gallium arsenide (GaAs) LED wafer used to fabricate a red light-emitting indicator (conventional technique). As shown in Figure 2A, high-brightness red LEDs were fabricated using a significantly different MOCVD process sequence based on a GaAs material system. The growth substrate is an n-doped GaAs wafer several hundred microns thick, and the first layer that is deposited is GaAs to produce a high-quality crystalline surface. The next layer is aluminum/arsenide (AlAs), which is then used as a release layer. The LED stack can start with an optional n-doped Dispersed Bragg Reflector (DBR) layer or an n-doped GaInP window layer and an n-doped AlGaInP cladding layer. Then, alternating layers of AlGaInP and AlGaAs are deposited on the MQW active region, and their thickness and composition are adjusted to make the high-efficiency LED emit light at the selected wavelength. The active region is covered by a p-doped cladding layer of AlGaInP and a p-doped GaInP window layer to complete the LED. The thickness of the entire LED stack above the AlAs release layer can be 10 to 15 μm.

The MOCVD growth of the GaAs growth substrate and AlGaInP is lattice matched, but GaAs absorbs light and is very brittle, which is a serious disadvantage for LED packaging. Thus, as shown in Figure 2B, the LED device is removed from the substrate by either fully etching the substrate or by using a selective wet etch (usually hydrochloric acid (HCl):acetic acid) to undercut and release the device. Before removing the LEDs from the substrate, a thick layer of copper is deposited by electroplating to serve as a heat sink and each A device's processing interface. First, a gold strike layer was deposited and patterned to define copper regions, and then the copper was electroplated to a thickness of about 100 μm. Then, the LED stack is etched down around the copper islands until the GaAs buffer layer, followed by release of the etch undercut device by wet etching the AlAs layer. Device size (cross-section) is similar to 150 to 1000 microns for GaN general illumination LEDs.

3A and 3B depict partial cross-sectional views of conventional encapsulated blue and red LEDs (prior art), respectively. These figures are presented to differentiate between micro LEDs (provided in the detailed description below) and conventional packaging techniques for larger LEDs. For general illumination, white light is produced from a blue-emitting GaN device, as shown in Figure 1B, with an additional color-converting phosphor that covers the LED and converts some of the blue light to longer wavelengths, typically a broad yellow emitting Phosphors such as YAG doped with cerium (III) (YAG: Ce ^3- or Y ₃ Al ₅ O ₁₂ : Ce ³⁺ ). The package used has a lead frame for making electrical connections, heat sinks for dissipating the thermal energy generated in the LED, and a reflector for directing the light to the user. The LED is attached to the heat sink by thermally conductive adhesive, and the LED terminal is connected to the lead frame by wire bonding. After bonding, the package cavity is filled with a clear encapsulant, usually silicone or epoxy, that protects the device from mechanical damage and corrosion from ambient air and water. The encapsulant may also contain a color converting phosphor, or the phosphor may be in a separate film over the encapsulation (not shown). After packaging is complete, the device is tested for efficiency and peak wavelength in a process called binning. If the device has acceptable performance, it is bonded to a printed circuit board (PCB) along with the other devices in the array. It is important to note that the lighting array contains a plurality of devices in series, parallel or series/parallel depending on the desired operating voltage and brightness. Unlike display arrays (such as TV or smartphone displays) that require a controllable brightness of each pixel to produce an image, all devices in a general lighting array work simultaneously.

Manufacturing displays with pixel densities (PPI) in the range of 10 to 600 necessarily requires microLEDs with cross-sections (diameters) less than 150 microns. As described in more detail below, the micro LED dimensions and internal structure are formed by using conventional photolithographic processes by mask design, film thickness and Patterns produced by photoresist exposure control. Using the lithographic pattern as a mask, an etching process selectively removes material to form features of the complete device. For example, in the case of GaN, the etching does not proceed completely uniformly across the entire wafer and between wafers, therefore, creating a pads, electrodes that connect p+ semiconductors) can vary widely in the amount of buildup required for the structure. The deposition of the build-up metal is carried out by evaporation or sputtering, and the precision of the thickness control is not even as good as that of the photolithographic steps. If the N-pad and P-pad electrodes of the micro LED are not coplanar, the electrical connection of the micro LED to the display substrate may be incomplete, resulting in failure or high series resistance.

For the purpose of minimizing failures in the manufacture of display substrates using SM-LEDs, it would be advantageous if the substrate interface of the LED electrodes could be maximally flat.

Described herein are miniature light-emitting diode (LED) structures with diameters between 10 and 150 μm that are suitable for fluidic assembly of large-area arrays to fabricate high-resolution red-green-blue (RGB) displays. The fabrication process of micro LEDs is similar to that of gallium nitride (GaN) based blue/green LEDs and aluminum gallium indium phosphide (AlGaInP) based red LEDs produced by conventional metal-organic chemical vapor deposition (MOCVD) growth techniques. Allow. The resulting micro-LEDs have electrode structures that, after fluid assembly, can electrically and physically combine the array contact points in the display substrate to form an active or passive matrix display. The disclosed micro-LED structure can change pixel brightness within a range that meets different display requirements without changing the structure of the micro-LED, thereby not affecting the yield and reliability of the fluid assembly process.

Accordingly, a method for fabricating surface mount (SM) micro LEDs (μLEDs) is provided. The method provides a MOCVD-LED structure on a growth substrate. A stack covers a growth substrate including a first doped semiconductor having a top surface in a first plane, a multiple quantum well (MQW) overlying the first doped semiconductor having a top surface in a second plane layer with and a second doped semiconductor overlying the MQW layer and having a top surface in a third plane, wherein the first and second doped semiconductors are oppositely doped with n and p dopants, see Figures 1A and 2A. In the case of gallium nitride micro-LEDs, the first and second doped semiconductors are doped GaN. In the case of gallium arsenide (GaAs) micro-LEDs, the first and second doped semiconductors may be doped gallium phosphide (p-GaP) or doped indium gallium phosphide (n-GaInP).

The method etches the MOCVD stack to form a plurality of individual wafers on a growth substrate. A μLED is fabricated from each wafer by first selectively etching the above stack. An electrical insulator is conformally deposited to form a top surface in a fourth plane overlying the etch stack and then selectively etched to expose the second doped semiconductor to create the first via. A selective etch is also performed to expose the first doped semiconductor, thereby forming a second via. The first electrode is formed to cover the first via hole and connect to the second doped semiconductor through the first via hole, and has a substrate interface surface in the fifth plane. The second electrode is formed to cover the second via hole and connect to the first doped semiconductor through the second via hole, and has a substrate interface surface in the fifth plane. Finally, the fabricated μLEDs are separated from the growth substrate. Due to the use of conventional MOCVD wafers, the LEDs have a maximum cross-section of 150 microns coplanar with the first, second and third planes, and the mesa stack height orthogonal to the first, second and third planes is less than 2 microns, the average flatness tolerance of the fifth plane is less than 10 nm.

More specifically, the method enables the formation of a central mesa stack surrounded by trenches exposing the first doped semiconductor and a peripheral stack divided by peripheral trench valleys exposing the first doped semiconductor by selectively etching the stacks layer, thereby fabricating an SM center-emitting μLED. Then, conformally depositing an electrical insulator on the etch stack includes forming a fourth plane overlying the center mesa stack and the perimeter stack. The step of selectively etching to expose the second doped semiconductor includes etching a portion of the electrical insulator overlying the central mesa stack to form a first via, and the step of selectively etching to expose the first doped semiconductor includes etching Electrical insulator covering the perimeter trench valley to form a second via. As a result, the first electrode covers the central mesa stack and is connected by the first via to the second doped semiconductor, which has a substrate interface surface in the fifth plane. The second electrode has a The first portion on the side trench valley is connected to the first doped semiconductor through the second via hole. The second electrode has a second portion (connected to the first portion) that covers the electrical insulator formed on the perimeter stack and has a substrate interface surface in a fifth plane.

The SM peripheral emitting μLEDs are formed by selectively etching the stack to form a central mesa stack separated from the peripheral stack by trenches exposing the first doped semiconductor. A conformally deposited electrical insulator covers the central mesa stack and the peripheral stack. The step of selectively etching to expose the second doped semiconductor includes etching a portion of the electrical insulator overlying the perimeter stack to expose the second doped semiconductor, and the step of selectively etching to expose the first doped semiconductor includes etching the electrical insulator and a lower portion of the second doped semiconductor and MQW layers in the center mesa stack to expose the first doped semiconductor. As a result, the second electrode is formed to cover the central mesa stack and connect to the first doped semiconductor through the second via. The first electrode is formed overlying the electrical insulator formed on the perimeter stack and is connected to the second doped semiconductor through the first via.

The SM-μLED full area light emitting μLED is fabricated by selectively etching the stack to form a mesa stack and a peripheral trench valley in the mesa stack and exposing the first doped semiconductor. The step of selectively etching to expose the second doped semiconductor includes etching a portion of the electrically insulating layer overlying the mesa stack to expose the second doped semiconductor. The step of selectively etching to expose the first doped semiconductor includes etching an electrical insulator covering the perimeter trench valley. The first electrode covers the mesa stack and is connected to the second doped semiconductor through the first via hole. The second electrode includes a first portion covering the peripheral trench via, and is connected to the first doped semiconductor through the second via. A second portion of the second electrode (connected to the first portion) covers the electrical insulator formed on the perimeter of the platform stack and has a substrate interface surface in a fifth plane.

Also provided is a light emitting display substrate having a non-planar substrate electrode interface surface. The display consists of a support substrate having a planar top surface and a control matrix of LED intersections forming an array of column and row conductors. The first thin film layer covers the top surface of the support substrate and includes a plurality of wells. Each well has a convex bottom surface, a first substrate electrode connecting the corresponding column line and a first substrate electrode connecting the corresponding row line the second substrate electrode. The second thin film layer is interposed between the top surface of the support substrate and the first thin film layer. The convex surfaces of the well bottoms are formed by spacers interposed between the top surface of the support substrate and the second thin film layer below each well bottom.

Additional details of the above methods are provided below, as well as center, perimeter, full area light emitting SM micro LED devices and light emitting substrates with convex well bottom surfaces.

300:SM-LED

306: First electrical contact

308: Second electrical contact

402: the second semiconductor layer

404: first semiconductor layer

406, 1106, 1306: MQW layer

408, 1314: Electrical insulators

802: line

804: Column Line

1000: Light-emitting display substrate

1001: Support substrate

1002: Support substrate top surface

1008: First Film Layer

1010: Well

1012: Convex Bottom Surface

1014: First substrate electrode

1016: Second substrate electrode

1018: Second Film Layer

1018a: TFT Layer

1018b: first oxide layer

1018c: Second oxide layer

1020: Gasket

1022: Diameter

1024:width

1026: Top Surface

1028: First Dielectric Surface

1030: Second Dielectric Surface

1032: Via

1100: Center-emitting μLED

1102, 1302, 1402: first doped semiconductor

1102a, 1302a: Center Platform

1102b, 1302b: Peripheral

1110, 1310, 1410: second doped semiconductor

1114a, 1414a: Electrical insulator first part

1114b, 1414b: Electrical insulator second part

1118, 1418: Peripheral trench valley

1120, 1318, 1420: first electrode

1124, 1320: Center via

1126a, 1424a: second electrode first part

1126b, 1424b: second electrode second part

1128, 1326, 1426: Peripheral vias

1130, 1328: Groove

1134, 1332, 1430: Etch stack height

1104, 1304, 1404: first plane

1108, 1308, 1408: Second plane

1112, 1312, 1412: third plane

1116, 1316, 1416: Fourth plane

1122, 1322, 1422: Fifth plane

1132, 1330, 1428: sixth plane

1136, 1432: Navigation keel or column

1300, 1400: Micro LED

1324: Second Electrode

1336, 1434: the bottom surface of the first doped semiconductor substrate

1423: Platform Via

1A to 1C are diagrams depicting GaN-LED wafers (prior art) used for general lighting purposes.

2A and 2B are diagrams illustrating a gallium arsenide (GaAs) LED wafer (conventional art) used to fabricate a red light emitting indicator.

3A and 3B depict partial cross-sectional views of conventionally packaged blue and red LEDs (prior art), respectively.

4A and 4B are a partial cross-sectional view and a plan view, respectively, of a light emitting element that can be used as a surface mount (SM) LED.

FIG. 5 is a partial cross-sectional view depicting an alternative to the LED of FIG. 4 .

6A-6J depict the steps of fabricating a micro LED as described in US Pat. No. 9,825,202.

Figures 7A-7C depict a suspension medium applying torque to a micro LED with a navigation keel (strut).

8A and 8B are a plan view and a partial cross-sectional view, respectively, of a micro-LED sub-pixel layout.

9A-9E are partial cross-sectional views depicting micro-LED versus bit cells in exemplary well variations.

10A-10C are partial cross-sectional views of substrate wells and mated micro LEDs showing well bottom surface spacers.

11A to 11D are a plan view, two partial cross-sectional views, and a perspective view of a planar SM center-emitting μLED, respectively.

Figure 12 is a graph showing the relationship between flux and efficiency as a function of current density.

13A and 13B are a plan view and a partial cross-sectional view, respectively, depicting a planar SM peripheral light-emitting μLED.

14A and 14B are a plan view and a partial cross-sectional view, respectively, of a planar SM full-area light-emitting μLED.

15A to 15C are plan views comparing the light emitting surface areas of microLEDs with center emission (FIG. 11A), peripheral emission (FIG. 13A), and full area emission (FIG. 14A).

FIG. 16 is a flowchart illustrating a method for fabricating SM μLEDs.

17 is a flowchart illustrating a method for fabricating a display substrate having a well bottom surface spacer.

A general method for fabricating micro light emitting diode (μLED) displays using inorganic LEDs and fluidic assembly on a display backplane is disclosed in a prior family patent application (US Patent No. 9,825,202, Application No. 15/412,73) by Incorporated herein by reference. In particular, the description of FIG. 17 in US Pat. No. 9,825,202 describes a process flow for making a suitable display backplane. The geometrical requirements for the fluid assembly are presented in the description of FIG. 16 . The devices described herein are an improvement over the surface mount micro LED structures discussed in the prior family patent applications cited above, simplifying device fabrication while increasing the yield and versatility of micro LED displays.

US Patent No. 9,825,202 describes two types of gallium nitride (GaN) micro LEDs. A structure with a light emitting region at the center of the device is shown in FIGS. 4A and 4B, and a structure with the light emitters in the outer ring is shown in FIG. 5, as described below.

4A and 4B are a partial cross-sectional view and a plan view, respectively, of a light emitting element that can be used as a surface mount (SM) LED. SM-LED 300 includes a first semiconductor layer 404 having an n-type dopant or a p-type dopant. The second semiconductor layer 402 uses a dopant type not used in the first semiconductor layer 404 . A multiple quantum well (MQW) layer 406 is interposed between the first semiconductor layer 404 and the second semiconductor layer 402 . The MQW layer 406 may typically be a series of quantum well layers not shown (typically 5 layers, eg, 5 nm of indium gallium nitride (InGaN) alternating with 9 nm of n-doped GaN (n-GaN)). There may also be an aluminum gallium nitride (AlGaN) electron blocking layer (not shown) between the MQW layer and the p-doped semiconductor layer. The outer semiconductor layer may be about 200 nm thick p-doped GaN (Mg-doped). If a higher indium content is used in the MQW, high brightness blue LEDs or green LEDs can be formed. The most practical first and second semiconductor layer materials are GaN, which can emit blue or green light, or aluminum gallium indium phosphide (AlGaInP), which can emit red light.

The second electrical contacts 308 are configured in a ring shape, and the first semiconductor layer 404 has a disk shape with a perimeter below the second electrical contact ring. The first electrical contact 306 is formed within the perimeter of the second electrical contact 308, and the second semiconductor layer 402 and the MQW layer 406 are stacks underlying the first electrical contact. A trench may be formed between the ring of second electrical contacts 308 and the first electrical contacts 306 and filled with electrical insulator 408 .

Conventional LED processes, such as LEDs for lighting, only take place on one surface prior to separation from the sapphire substrate. Some of these processes use laser lift-off (LLO) to separate the LEDs from the sapphire substrate as a final step. Other processes do not use LLO, but cut out the sapphire substrate to singulate the LEDs. However, the SM-LED architecture requires electrodes on the surface opposite the posts (navigation keels) so that the posts can be fabricated after the μLEDs are removed from the growth substrate. Conventional processes do not provide a way to maintain a known position of each LED when removing the LEDs from the sapphire, so photolithography can be performed on the bottom of the LED. Precise x-y positions are required to position the post exactly at the desired location on the top surface of the LED (eg in the center). Precise z (vertical) positions are required to establish focal planes for lithography to be aligned with dimensional control (e.g., surface orientation) required for fluid assembly. Imaging of column structures. That is, the LLO of SM-LEDs requires that the SM-LEDs be placed on a transfer substrate in a controlled manner to form their pillars, and then released from the transfer substrate to make a suspension for fluid assembly.

Figure 5 is a partial cross-sectional view depicting an alternative to the LED of Figure 4A. In this aspect, the first electrical contact (electrode) 306 is configured as a ring, and the second semiconductor layer 402 and the MQW layer 406 are a ring-shaped stack under the first electrical contact. The second electrical contact 308 is formed within the circumference of the first electrical contact 306 . The first semiconductor layer 404 has a disk shape with a central portion positioned below the second electrical contact point. As shown, a trench is formed between the ring of first electrical contact 306 and second electrical contact 308 . Electrical insulator 408 fills the trench.

6A-6J depict the steps of fabricating a micro LED as described in US Pat. No. 9,825,202. For consistency of description, the top and bottom surfaces of the microLEDs are defined relative to the growth substrate, the last layer grown in the MOCVD process, with electrodes, and the bottom surface with optional pillars. Therefore, the surface mount configuration for connecting the substrates is bottom side up. For simplicity, it is assumed that the bottom layer in the MOCVD stack is n-GaN and the top layer is p-GaN, but of course the opposite structure is also possible, with appropriate choice of doping and electrode work function. The exemplary fabrication process flow schematically illustrated in Figures 6A to 6J is substantially the same for the GaN and GaAs variants, as follows.

1) As described above, the LED stack was deposited on a sapphire wafer by MOCVD. Other substrates such as silicon carbide (SiC) or silicon can be used, but the sapphire substrate allows the removal of the μLED from the growth substrate by laser lift-off (LLO), thereby decomposing the GaN on the bottom device surface adjacent to the sapphire substrate. The MQW structure was tuned to produce the desired emission color, and the thickness of the resulting structure was between 2 and 7 μm. See also FIG. 1A for examples of various layers.

2) A current spreading layer is deposited on the p-GaN surface. Component is generally thin NiO _x layer plus the interface a transparent conductive oxide such as indium tin oxide (ITO), which may be of a thickness of 100 to 500 nanometers (nm).

3) The light emitting region is defined by photolithography, and the MOCVD stack is etched to a depth extending into the n-doped GaN layer. Depending on the MOCVD structure, the etch depth (Z _MESA ) can range from 300 nm to 2 micrometers (μm). Usually less than 1 micron.

4) The μLED regions are defined by photolithography, and then the entire stack is etched down to the sapphire substrate. Typically, the pattern is an array of closely spaced micro LEDs to maximize the yield of micro LEDs on a single MOCVD wafer. The dimensions of the micro LEDs are chosen to match the width of the trapping sites on the display substrate, and are typically in the range of 15 to 150 μm in diameter.

5) An insulating layer, which can be SU8 or photo-patternable polyimide, is deposited and patterned to prevent current leakage between the N-pad and P-pad.

6) A lithographic pattern is formed to prevent metal deposition outside the N-pad area, and a metal layer is deposited to create electrodes to match the height of the P-pad. The first layer is chosen to match the work function of n-doped GaN, which can be 10 to 50 nm thick Ti or Cr. The stacking is accomplished by depositing an appropriate thickness of gold to match the height of the active area splines.

7) The metal and photoresist are removed by lift-off, leaving a buildup on the n-GaN contact area.

8) Photolithography is performed to prevent deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μLED contact holes.

a. The first metal is chosen as the conductive layer between the buildup and the solder material, which can be chromium/gold (Cr/Au) or titanium/nickel (Ti/Ni) with a total thickness of 100-200 nm.

b. The top layer is a low melting point solder that can be bonded to the substrate electrodes. One system is tin (Sn) alloys such as tin-indium (Sn-In), tin-indium-silver (Sn-In-Ag), and tin-silver-antimony (Sn-Ag-Sb), where the selected solder The metal is similar to conventional low melting point solder materials. Another metal solder system is gold/germanium (Au/Ge).

9) The excess metal is removed by a lift-off process.

10) Adhere the top surface side of the completed wafer to a temporary carrier with an adhesive layer, and remove the sapphire growth wafer by LLO (laser liftoff, laser liftoff).

11) The μLEDs are now bottom-up on a temporary carrier in a planar array suitable for further processing. For clarity, the convention to identify the top and bottom surfaces of microLEDs based on the original growth orientation is maintained.

12) Optionally, the n-GaN can be etched to reduce the thickness of the micro LED.

13) A post structure for fluid assembly, also called a navigation keel, can be fabricated on the bottom near the center of the micro LED. The posts may be cylindrical, conical, or concave in shape, with the height and diameter of the posts selected to facilitate bottom-side-up orientation of the μLEDs during fluidic assembly, as explained in more detail below.

14) Finally, intact μLEDs are collected into suspension by dissolving the binder using a suitable solvent.

The microLEDs produced by the manufacturing process all have critical dimensions such as diameter, thickness, and column height, as well as the size and arrangement of electrodes, which are configured to match the geometry of the wells and electrodes on the display substrate, so that the microLEDs can be compared with The P-pad and N-pad electrodes are assembled and bonded together, and the P-pad and N-pad electrodes are connected to the row and column interfaces of the display substrate, respectively. As shown in Figures 8A and 8B, each sub-pixel has two electrodes on the substrate centered on a trap structure with vertical walls (also called wells). Disk-shaped microLEDs and matching circular wells and electrodes are shown simply, but other shapes such as squares or triangles can be used, as long as the shape is designed to match the complementary shape in the substrate so that both microLED electrodes are electrically Connect the correct substrate electrodes without shorting.

The fluidic assembly of micro-LEDs is performed by dispensing the micro-LEDs in a liquid suspension over a display substrate. Some examples of suspension components include water, alcohols, ketones, alkanes and organic acids. The fluid can be disturbed in some way, such as a brush or blade, or a flow of solvent or gas, to create a flow of liquid across the substrate. Precisely position the contact of its surface mount electrodes with electrical interfaces (substrate electrodes) in the substrate well as the micro LEDs are moved across the substrate as the micro LEDs are captured and fixed in the substrate well structure to create a self-assembled array of micro LEDs , many capture attempts are made. When the fluid assembly is complete, as determined by an on-site monitoring system that can use cameras and machine vision algorithms to determine assembly yield, the suspension is removed and the display is completed by annealing to form a solder bond between the micro LEDs and the substrate electrodes . Fluid assembly is an inherently stochastic process, therefore, the size of the device and traps and the parameters of the assembly process are selected based on statistical analysis of trapping efficiency.

Figures 7A-7C depict a suspension medium applying torque to a micro LED with a navigation keel (strut). It is known that the fluid velocity increases parabolically from zero at the enclosed surface, so the force on the micro-LED increases with distance from the top surface of the substrate. When the suspension is first distributed on the substrate, the micro-LEDs can be dispensed relatively quickly before settling on the surface of the substrate. After reaching the substrate, the micro-LEDs continue to move under the influence of the fluid flow, so, as shown in Figure 1, a device with the posts down as shown in Figure 7A experiences torque that tends to flip the direction so that the electrodes face down and the posts up. Similarly, if the micro-LED enters the well with the post down (Figure 7B), the post will prevent the disc from being trapped, and the force on the disc tends to push the micro-LED out of the well and flip the electrode down. If the micro-LED is trapped in a trap, as shown in Figure 7C, the resultant force from the fluid flow is much smaller due to the smaller cross-section of the column, so the probability of escape is low. Successful fluidic assembly requires proper handling of the microLED so that its most stable configuration is also bonded to the substrate in the correct position and orientation.

8A and 8B are a plan view and a partial cross-sectional view, respectively, of a micro-LED sub-pixel layout. Each micro-LED sub-pixel in the display array is driven by a voltage applied to two electrodes arranged in a matrix of intersections of row lines 802 and column lines 804, respectively. In typical flat panel display fabrication, row and column interconnects are thin films of aluminum or copper between 200 and 1500 nm thick. The amount of light emitted by a given micro LED is controlled by the amount of current supplied by the external driver die and the resistance of the TFT control circuit (not shown) that is part of the sub-pixel. The key point for making micro LEDs is that the two electrodes on the SM micro LED must be combined with low resistance substrate electrodes to allow the correct amount of current to flow through the micro LED. The substrate electrodes were chosen for low resistance and compatibility with the solder layer on the micro LEDs. Allow. In one case, the substrate electrodes are 200 to 1000 nm thick copper to form a copper-tin intermetallic compound with the tin-based solder layer. Of course, the opposite arrangement, with solder on the substrate electrodes and gold electrodes on the micro-LEDs, is also possible. As can be seen in Figure 8B, successful fluidic assembly requires that the diameter of the micro-LEDs is smaller than the diameter of the wells so that the micro-LEDs can be trapped and bonded to the substrate electrodes.

9A-9E are partial cross-sectional views depicting micro-LED versus bit cells in exemplary well variations. Figure 9A depicts that the well diameter is slightly larger than the micro LED diameter, which facilitates alignment and bonding. In Figure 9B, the wells are too small resulting in unfavorable alignment and bonding, preventing electrical contact between the micro LEDs and the substrate. In Figure 9C, the well diameter is too large to allow the LED electrodes to cause shorts between the row and column substrate electrodes.

All of these dimensions are the result of dimension control through reticle design, film thickness and photoresist exposure using relatively conventional photolithographic processes. The deposition thickness for the buildup is chosen to match the depth of the shovel etch (see Figure 6B), which defines the central active (light emitting) region, so the target thickness must be determined by measuring the etch depth. GaN etch is performed in a single wafer etch chamber, so etch rates can vary by 10-20% between successive wafers. Additionally, the etch rate is not completely uniform across the wafer, with as much as 10-15% variation from center to edge. As a result, for an etch with a nominal target of 1 micron, _{the height difference of the central spline (Z MESA} ) can be as high as 400 nm. The deposition of build-up metal is usually accomplished by evaporation or sputtering, and often many wafers are processed together in a batch process, so individual deposition thicknesses for each wafer are not feasible. For this case, the target thickness for the build-up deposition was chosen to be the Z _MESA average for all wafers, regardless of the aforementioned etch differences, and the result was that the build-up thickness was too large for some wafers and too thick for others. too thin. Due to variations in GaN etching and buildup metal deposition, the final structure N-pad (electrode connecting the n+ semiconductor) and P-pad (electrode connecting the p+ semiconductor) may not be on the same plane. This difference can vary from one micro-LED to another, and can be as much as 600nm, which can have a noticeable impact on the yield and reliability of the electrical connection between the micro-LED and the substrate contact points Negative impact.

In FIG. 9D, the N-pads of the peripheral micro-LEDs are too thick, so the center electrodes (P-pads) of the micro-LEDs do not contact the substrate dielectric surface because the heights of the N-pads and P-pads are not coplanar. The result is pixel darkening due to poor control of electrode planarity. Conversely, in Figure 9E, the N-pad on the perimeter is too "low" relative to the center electrode, resulting in incomplete contact between the electrode and the mating substrate's dielectric surface. The slanted micro-LEDs result in the contact between the N-pad and substrate electrodes being restricted to a small area rather than the entire perimeter. Small area contacts can increase series resistance and reduce the reliability of electrical connections. To prevent the described alignment and bonding failure mechanisms, it would be advantageous to fabricate the microLEDs in such a way that the P-pad and N-pad electrodes are always at the correct relative coplanar heights to achieve optimal contact with the substrate electrodes.

10A-10C are partial cross-sectional views of substrate wells and mated micro LEDs showing well bottom surface spacers. The light emitting display substrate 1000 includes a support substrate 1001 having a flat top surface 1002 and an LED intersection control matrix including an array of column and row conductors. Since only one LED is shown, there is only one pair of column and row lines, shown at 804 and 802, respectively, in Figure 8A. Active and passive matrix systems are explained in detail in prior family application US Pat. No. 9,825,202, which is incorporated herein by reference. As mentioned in the background section above, light emitting display substrates typically include millions of LEDs. A first thin film layer 1008 overlies the top surface 1002 of the support substrate. Again, only a single well 1010 is shown. Each well 1010 has a convex bottom surface denoted by reference numeral 1012, wherein the bottom surface has a first substrate electrode 1014 connecting the corresponding column line (804, see Fig. 8A) and connecting the corresponding row line (802, Fig. 8A) the second substrate electrode 1016.

The second thin film layer 1018 is interposed between the support substrate top surface 1002 and the first thin film layer 1008 . As shown in Figures 10B and 10C, the second thin film layer 1018 may consist of a TFT layer 1018a containing thin film transistors (TFTs), not shown, and interconnected to row and column conductors in order to enable LED operation. The second thin film layer 1018 can also be composed of some oxide or insulating layers, so as to An oxide layer 1018b and a second oxide layer 1018c are exemplified. A spacer 1020 is interposed between the support substrate top surface 1002 and the second thin film layer 1018, below the bottom of each well. The spacer 1020 may be an insulating material, as shown in Figure 10A, or an electrical conductor, as shown in Figures 10B and 10C. The first thin film layer wells 1010 each have a diameter 1022 or cross section (in the case of a non-circular LED). The spacer 1020 has a width 1024 and a top surface 1026 that is less than the diameter 1022 . The convex bottom surface 1012 of the well is due to the difference in height between the top surface 1026 of the spacer and the top surface 1002 of the support substrate.

As shown in all examples, the first substrate electrode 1014 is a central substrate electrode having a first electrical interface surface 1028 for electrically connecting the micro LEDs, and the second substrate electrode 1016 is a peripheral substrate having a second electrical interface surface 1030 The electrodes, which are lower than the first dielectric surface, which is defined relative to the support substrate top surface 1002, are also used to electrically connect the micro-LEDs. Column interconnect pads 1020 are formed by forming pads directly on the column lines, as explicitly shown in FIGS. 10B and 10C . The first substrate electrode 1014 is the center substrate electrode that covers the vias 1032 and connects the column interconnect pads 1020 .

Several methods can be used to match the micro LED electrodes to the electrical interface structure on the display substrate to facilitate solder bonding. As shown, additional spacer structures can be added to the substrate below the central substrate electrode to raise it above the outer ring substrate electrodes by the thickness of the spacer layer. The pads can be made of metal films used elsewhere for interconnection, such as aluminum or copper, or of insulating layers, and can be 50 to 500 nm thick. If the pad is conductive, it is isolated from the center substrate electrode by an interlayer dielectric as shown. Alternatively, the center and edge substrate electrodes may be fabricated separately with layers having different thicknesses. The result is that the center and edge electrodes are no longer coplanar, and the height difference is D _sub = Z _{C -} Z _E ( FIG. 10A ). It can be seen that when the electrode height D _LED = Z _{P -} Z _N equals D _SUB , the substrate electrode structure is best matched to the micro LED. Therefore, this configuration can compensate for the "low" P-pad (center) electrode in any case where _{D LED} < D _{SUB, but at the expense of added complexity and variability.} Of course, for micro-LEDs with "high" P-pad electrodes (D _LED > 0), this structure will have lower performance and result in a reduced contact area, as shown in Figure 9E.

Spacers can be fabricated in various ways as long as the height of the substrate electrodes is typically 50 to 500 nm and the height difference is suitable for interfacing with the micro LEDs. In the case of an active matrix display (eg, FIG. 10B ), the micro LED wiring is constructed on the layer used to fabricate the TFT (not shown). Micro LED wiring consists of metal interconnects arranged in rows and columns that connect the substrate interface electrodes. For low resistance row and column interconnect lines are typically copper or aluminum, and the line thickness is 100 to 900 nm. Therefore, since the metal layers are separated by an insulating layer (usually silicon oxide), the electrode connections can pass through each other without short-circuiting. In Figure 10B, a first oxide layer 1018b separates the column and row interconnect lines (804 and 802, see Figure 8A), while a second oxide layer 1018c separates the column interconnect and the first substrate electrode, and between the layers The connections are made through appropriately placed vias. In FIG. 10B, the spacer under the center substrate electrode is made of the same metal as the metal film used to make the column interconnects, so the center substrate electrode is lifted by the thickness of the film. In Figure 10C, an alternative strategy is used in which the height of the central substrate electrode is increased by the thickness of the first oxide layer and the column interconnect layer.

Using the spacers described above, micro LEDs with "high" peripheral electrodes, as shown in Figure 9D, can be successfully matched to the convex well bottom structures shown in Figures 10A, 10B and 10C. However, even if the center and peripheral electrodes of the micro-LED are planar, as shown in Figure 9A, or the micro-LED center electrode is "higher" than the peripheral electrodes, as shown in Figure 9E, the micro-LED electrodes will be able to connect with the substrate electrodes, But at the cost of higher current resistance and reduced contact area.

A simpler and more efficient method to fabricate micro-LED electrodes with equal (coplanar) substrate interface surfaces is disclosed in more detail herein. To avoid the tolerance issues associated with etching portions of the MOCVD stack first and then depositing and patterning the thin film, the inherently coplanar MOCVD stack is advantageously used as a mechanical element to elevate the N-pad electrode to the same level as the P-pad height, make sure D _LED =0. MOCVD growth of GaN and AlGaInP is a heteroepitaxial process in which the crystal structure is built layer by layer from the base structure as a template. Unlike the physical deposition process described above, which typically results in topological changes due to grain growth, heteroepitaxy successfully results in its surface being locally (less than or equal to the micro-LED diameter) flat (planar) within at most a few atomic layers. Similarly, the insulating layer, typically silicon dioxide deposited by plasma enhanced chemical vapor deposition, is smooth and locally (as defined above) planar. Therefore, the fourth plane used as a substrate for surface mount electrodes has substantially lower variability, typically less than 10 nm. The surface mount electrodes with low melting point solder as described above are deposited on the fourth plane, and the final electrode interface surface is located on the same fifth plane. The overall variability in electrode deposition thickness results in microLEDs of different thicknesses, but when considered locally, both surface mount electrode interface surfaces of all microLEDs are on the same (fifth) plane. Unlike CVD processes, physical vapor deposition (PVD) of metals results in a certain roughness of the solder surface due to agglomeration and grain growth. Therefore, the surface roughness of the final surface may be around 10 to 100 nm. Considering this potential surface roughness, it can be said that the micro LED electrode interface surface has an average fifth plane tolerance of 10 nm. Since the fabrication of micro LEDs makes D _LED always zero, there is no advantage to the spacer structure of FIG. 10 , and referring to FIG. 10 , the display substrate can be fabricated _{with D SUB=0.}

11A to 11D are a plan view, two partial cross-sectional views, and a perspective view of a planar SM center-emitting μLED, respectively. The center emitting μLED 1100 includes a first doped semiconductor 1102 formed as a substrate and doped with n or p dopants. As shown in Figures 11A and 11C, the first doped semiconductor 1102 substrate has a circular perimeter in this example, but is not limited to any particular shape. The first doped semiconductor 1102 has a top surface formed in a first plane 1104 that includes a central mesa 1102a (distinguished by a dashed line) separated from a perimeter 1102b (distinguished by a separate dashed line). The MQW layer 1106 (typically formed as several sub-layers) has a top surface formed in the second plane 1108 that covers the first doped semiconductor central mesa 1102a and the perimeter 1102b. A second doped semiconductor 1110 doped with a dopant opposite to that used in the first doped semiconductor 1102 is formed as a layer having a top surface in a third plane 1112 above the MQW layer 1106 .

The electrical insulator has a first portion 1114a formed with a layer covering the top surface in the fourth surface 1116 of the second doped semiconductor 1110, and a second portion 1114b covering the perimeter trench valley 1118 dividing the perimeter 1102b. The key function of the insulator is to prevent the first and second doping of the semiconductor current leakage between the bodies. The first electrode 1120 covers the central platform, is connected to the second doped semiconductor 1110 through the central via 1124 , and has a substrate interface surface in the fifth plane 1122 . The second electrode has a first portion 1126a formed on the peripheral trench valley 1118 and is connected to the first doped semiconductor 1102 through peripheral vias 1128 . The second electrode has a second portion 1126b overlying the perimeter of the electrical insulator first portion 1114a and is connected to the second electrode first portion and has a substrate interface surface in the fifth plane 1122.

The SM center emitting μLED 1100 also includes a trench 1130 formed in the first doped semiconductor 1102 that separates the center mesa 1102a from the perimeter 1102b. The trenches 1130 and the perimeter trench valleys 1118 have top surfaces formed in a sixth plane 1132 below the first plane 1104 .

In one aspect, the first doped semiconductor 1102 and the second doped semiconductor 1110 are doped GaN. Alternatively, the first doped semiconductor 1102 and the second doped semiconductor 1110 are p-doped gallium phosphide (p-GaP) or n-doped gallium indium phosphide (n-GaInP). Technically, the doped semiconductors can also be n-GaP and p-GaInP, but they are less practical.

Although not explicitly shown, GaN devices may optionally include electron and hole injection and blocking layers, as is known in the art. In the case of GaAs devices, optional p and n cladding layers may be used, which are also well known in the art. Generally, for both red and blue micro-LEDs, it is desirable to maximize the residence time of electrons and holes in the MQW layer. Considering only the anode side, for example, it is desirable to prevent electrons from leaving, so the electron blocking layer (AlGaN) has a high barrier to electrons in the conduction band. Ease of hole entry is also desired, so a separate hole injection layer can be added on top of the electron blocking layer to eliminate small discontinuities in the valence band. In the case of AlGaInP, the n and p cladding layers serve the same purpose, but for historical reasons they are called windows and cladding layers. As shown, the SM center-emitting μLED 1100 may include a plurality of first doped semiconductor peripheral segments 1102b separated by a plurality of peripheral trench valleys 1118 . In that case, the MQW layer 1106, the second doped semiconductor 1110 and the electrical insulator first portion 1114a cover each of the first doped semiconductor peripheral segments 1102b. The second electrode first portion 1126a is formed on each peripheral trench valley 1118 and via the corresponding peripheral via 1128 The first doped semiconductor 1102 is connected. The second electrode second portion 1126b covers the perimeter of the segment of the electrical insulator first portion 1114a and has a substrate interface surface in the fifth plane 1122.

The first doped semiconductor 1102, the MQW layer 1106 and the second doped semiconductor 1110 form an etch stack having a height 1134 orthogonal to the first plane 1104, the second plane 1108 and the third plane 1112 of less than 2 microns, And the flatness tolerance of the first, second, third and fourth planes is less than 10 nm. As mentioned above, the electrode interface surface in the fifth plane has an average flatness tolerance of less than 10 nm. Rather than relying on the greater tolerances inherent in the use of thin film deposition processes to form planar electrode surfaces, as shown in Figures 6A-6J, the devices described herein use MOCVD stacks of pre-existing planar surfaces. Thus, the MOCVD plane can be used to maintain flatness between the substrate interfaces of the final formed electrode even if there are differences in the wafer-to-wafer or wafer-to-wafer stack-up etch. Briefly, micro LED 1100, and micro LEDs 1300 and 1400 presented below, can be described as a device in which electrodes are formed on an etched MOCVD wafer (ie, an etch stack) without subsequently deposited intervening semiconductor layers.

In an aspect not shown, the solder layer forms part of the first and second electrode interface surfaces and is made of an alloy such as indium/tin (In/Sn) or gold/germanium (Au/Ge). Alternatively, the substrate interface surfaces of the first and second electrodes are gold. Optionally, as shown, a navigation keel or post 1136 is attached to the first doped semiconductor substrate bottom surface 1138.

As shown in FIG. 11A, the exemplary center emitter design uses four equally spaced island-like structural support segments of an annular N-pad electrode. A key factor in the design is that the N-pad and P-pad electrodes are coplanar. Note also that the island (peripheral) structure is not electrically active and is isolated from the N-pad electrode by an insulator, so the connection to the N-pad electrode is made through 4 contact points spaced between the islands. The number of islands usually depends on the size of the micro LED, from one to six or more, but there is at least one opening in the island-like structure for contact with the N-doped region. Fewer contacts allow a larger area for solder to contact the substrate electrodes, but increase the diffusion resistance in the n-doped layer. Conversely, the more openings between the islands, the final area for contact between the micro LEDs and the substrate electrodes smaller. On the one hand, three or four islands/contacts have been found to be preferred to obtain the best compromise between series resistance and bond strength.

The process flow of the present invention is similar to the prior art flow presented above, in which the photo, deposition and lift-off steps associated with N-pad stacking (steps 6 and 7 above) are removed, thus producing surface mount electrodes with perfectly coplanar Miniature LEDs reduce cost and complexity. An exemplary process flow for fabricating the current design of GaN-based micro LEDs is as follows:

1) As described above, the LED stack was deposited on a sapphire wafer by MOCVD. Other substrates such as SiC or silicon can be used, but the sapphire substrate allows removal of the μLEDs from the growth substrate by laser lift off (LLO). The MQW structure is tuned to produce the desired emission color and the thickness of the resulting structure is between 2 and 7 μm, see also Figure 1A.

2) A current spreading layer is deposited on the p-GaN surface. This component is generally thin (10nm or less) NiO _x plus the thickness of the interface layer may be a transparent conductive oxide 100 to 500nm, for example, ITO.

3) The light emitting region is defined by photolithography, and the MOCVD stack is etched to a depth extending into the n-doped GaN layer, forming a structure referred to herein as an "etched stack".

4) Define the μLED region by photolithography and etching the entire stack down to the sapphire substrate.

5) An insulating layer, typically plasma-enhanced CVD (PECVD) silicon dioxide (SiO2) with a thickness of 100 to 400 nm, is deposited to prevent current leakage on the device.

6) Contact points corresponding to the p-GaN and n-GaN regions are opened in the insulating layer.

7) A lithographic pattern is formed to prevent metal deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μLED contact holes.

a. The first metal layer is chosen to bond to the oxide and to match the work function to n-doped GaN. A typical material is Cr 10 to 50 nm thick.

b. The next metal is chosen as a conductive barrier between the adhesion layer and the solder material, which can be Cr/Au or Ti/Ni with a total thickness of 100-200 nm.

c. The top layer is a low melting point solder that can bond the substrate electrodes. One system is a tin alloy for the melting temperature of the solder. Another metal system is Au/Ge.

d. Alternatively, the micro LEDs may only receive the metal from steps 7a and 7b, and the low melting point solder may be formed on the display substrate electrodes.

8) The excess metal is removed by a lift-off process.

9) The top surface of the completed wafer is bonded to the temporary carrier by an adhesive layer, and the sapphire growth wafer is removed by LLO.

10) The μLEDs are now bottom-up on the carrier wafer in a planar array suitable for further processing.

11) Optionally, the n-GaN can be etched to reduce the thickness of the μLED.

12) A post (navigation keel) structure for fluid assembly is optionally fabricated on the bottom surface near the center of the μLED. The posts can be cylindrical, conical, or concave in shape, with the height and diameter of the posts selected to facilitate bottom-side-up orientation of the μLEDs during fluidic assembly.

13) Finally, intact μLEDs are collected into suspension by dissolving the binder using a suitable solvent.

Since the red LEDs were fabricated in a different MOCVD process, the process flow was modified for GaAs-based devices. The shape of the device and the placement of electrodes and pillars are similar to those of the GaN device, but the thickness of the device may vary. An exemplary processing flow proceeds as follows:

1) As described above, the LED stack is deposited on a GaAs wafer by MOCVD. The MQW structures were tuned to produce the desired luminescence color, and the thickness of the resulting structures was between 5 and 10 μm. See also Figure 2A.

2) Optionally, p-GaP can be etched to reduce the thickness of the stack.

3) The top surface of the completed wafer is bonded to a glass or sapphire temporary substrate by an adhesive layer, and the GaAs growth wafer is removed by wet etching.

4) The μLED regions are defined by photolithography and the entire stack is etched.

5) The light emitting region is defined by photolithography, and the MOCVD stack is etched to a depth extending into the p-doped GaP layer, thereby forming the etch stack.

6) A metal layer such as Cr/Au is deposited on the p-GaP region matching the work function of the layer.

7) A metal layer such as Ti/Au is deposited on the n-GaP region matching the work function of the layer.

8) depositing a layer of the insulating layer, typically 100 to 400nm thickness of PECVD SiO ₂ is deposited to prevent current leakage in the device.

9) Opening contacts corresponding to the p-GaP and n-GaP regions in the insulating layer.

10) A lithographic pattern is formed to prevent metal deposition outside the N-pad and P-pad contact areas, and a metal stack is deposited to connect the μLED contact holes.

a. The first metal is selected as the conductive barrier layer between the adhesion layer and the solder material, which can be Cr/Au or Ti/Ni with a total thickness of 100-200 nm.

b. The top layer is a low melting point solder to which the substrate electrodes can be bonded. One system is a tin alloy used to lower the melting temperature of solder. Another suitable low melting point metal system is Au/Ge. Alternatively, the solder layer may be formed on the substrate electrode.

11) The excess metal is removed by a lift-off process.

12) Adhere the top surface of the finished wafer to the temporary wafer with an adhesive layer and remove the first temporary substrate by dissolving the first adhesive.

13) The μLEDs are now bottom-up on a temporary wafer in a planar array suitable for further processing.

14) Optionally, the n-GaP can be etched to reduce the thickness of the micro LED.

15) The column structure for fluid assembly is optionally fabricated at the bottom near the center of the micro LED. The posts may be cylindrical, conical, or concave in shape, with the height and diameter of the posts selected to facilitate bottom-up orientation of the micro-LEDs during fluid assembly.

16) The finished micro-LEDs are collected in suspension by dissolving the second binder using a suitable solvent.

Figure 12 is a graph showing the relationship between flux and efficiency as a function of current density. One of the most important advantages of micro LED displays is that inorganic LEDs can achieve very high brightness, which allows flexibility to match the display's luminous performance to the product's specific resolution and brightness requirements. A small wearable display might only need 150-200 nits (candela per square meter) of brightness, while a TV might be 500-1500 nits, and an outdoor public information display (PID) might be 2000-4000 nits. A small display for a cell phone or tablet may have a resolution of over 600 pixels per inch (ppi), while a large PID display may have a resolution of only 20 to 60ppi, so the usable area of each microLED varies widely. For GaN microLEDs emitting at 440 nm (blue light), as shown in Figure 12, the luminous flux from the microLEDs is an approximately linear function of current density over a relatively wide range. Thus, micro LED displays adjust grayscale intensity by controlling the current supplied to each sub-pixel.

The electro-optical conversion efficiency (light output/electrical power) of microLEDs peaks at a relatively low flux and then gradually decreases (drops) over a wide range of applied currents. For display operation, it is desirable to operate around the peak efficiency to minimize waste heat dissipated in the display. However, very low currents are difficult to adjust, so the optimal current density for a given display depends on a variety of factors. General lighting LEDs operate at high current densities of about 70 amps per square centimeter (A/cm ² ) to maximize light output per device, thereby minimizing cost per bulb. Micro LED displays typically at lower current densities to achieve higher reliability and lower heat dissipation, and therefore the operating range could be between 1 to 30A / cm ^2. Other factors that influence the choice of micro-LED configuration include the efficiency of each colored micro-LED, color gamut requirements, and the sensitivity of the green-centric human visual system. Therefore, it would be advantageous to have a structure that allows adjustment of the micro-LED light emitting area to balance performance requirements while maintaining fixed micro-LED characteristics such as pillar height, thickness and diameter, which are critical for high-throughput fluidic assembly of.

13A and 13B are a plan view and a partial cross-sectional view, respectively, depicting a planar SM peripheral light-emitting μLED. The peripheral emitting μLED 1300 includes a first doped semiconductor 1302 formed as a substrate and doped with n or p dopants. The first doped semiconductor 1302 has a top surface formed in a first plane 1304 including a central mesa 1302a separated from the perimeter 1302b. As shown in Figure 13A, the first doped semiconductor substrate is circular, but other well-known geometries are possible. An MQW layer 1306 having a top surface is formed in a second plane 1308 overlying the first doped semiconductor central mesa 1302a and the perimeter 1302b. The second doped semiconductor 1310 , doped with the opposite dopant for the first doped semiconductor 1302 , has a top surface in the third plane 1312 overlying the MQW layer 1306 .

Electrical insulator 1314 is formed as a layer having a top surface in fourth plane 1316 overlying second doped semiconductor 1310 . The first electrode 1318 covers the central platform 1302a and is connected to the first doped semiconductor 1302 through the central via 1320 . The first electrode 1318 has a substrate interface surface in the fifth plane 1322 . The second electrode 1324 covers the periphery of the electrical insulator 1314 and is connected to the second doped semiconductor 1310 by the peripheral via 1326 . The second electrode 1324 has a substrate interface surface in the fifth plane 1322 . A trench 1328 is formed in the first doped semiconductor 1302, the trench 1328 separating the central mesa 1302a from the perimeter 1302b. The trench has a top surface formed in a sixth plane 1330 below the first plane 1302 . In one aspect, the first doped semiconductor 1302 and the second doped semiconductor 1310 are doped GaN. Alternatively, the first doped semiconductor 1302 and the second doped semiconductor 1310 are p-doped p-GaP or n-doped n-GaInP. The first doped semiconductor central mesa 1302a, the MQW layer 1306, and the second doped semiconductor 1310 form an etched stack having a height 1332 perpendicular to the first plane 1304, the second plane 1308, and the third plane 1312 of less than 2 micrometers, and the flatness tolerance for the first, second, third and fourth planes is less than 10 nanometers. The average flatness tolerance of the electrode interface surface in the fifth plane is also less than 10 nm.

In one aspect, not shown, the solder layer forms part of the first and second electrode interface surfaces and is made of alloys such as In/Sn or Au/Ge. Alternatively, the substrate interface surfaces of the first electrode and the second electrode are gold. Optionally, as shown, a navigation keel or post 1334 is attached to the first doped semiconductor substrate bottom surface 1336 .

The central emitter described above and shown in Figures 11A and 11C includes a light emitting area of 10% to 15% of the total surface area of the disk-shaped micro-LEDs, wherein the surface areas of the micro-LEDs are parallel to the first, second, and third flat. As shown in Figures 13A-13B, the structure can be changed so that the light emitting area is an outer ring structure covered by the P-pad, and the central island (platform) is the mechanical support for the N-pad electrode. In this regard, the light emitting area may be about 50% of the surface area of the micro LED disk. The advantage of this structure is that the continuous P-pad electrodes are not interrupted by the contact holes, so a complete 360-degree ring of electrical contacts with the substrate interface can be achieved. In this configuration, there is a trade-off between the diffusion resistance, which is reduced by increasing the center contact area, and the reduction in the area of the mesa, which keeps the solder in contact with the substrate electrodes.

14A and 14B are a plan view and a partial cross-sectional view, respectively, of a planar SM full-area light-emitting μLED. The full area light emitting μLED 1400 includes a first doped semiconductor 1402 formed as a substrate and doped with n or p dopants. Although the first doped semiconductor substrate is depicted as being circular, it is not limited to any particular geometry. The first doped semiconductor 1402 has a top surface formed in a first plane 1404 that includes a mesa. The MQW layer 1406 has a top surface formed in a second plane 1408 overlying the first doped semiconductor mesa. A second doped semiconductor 1410 doped with a dopant opposite to that used in the first doped semiconductor is formed as a layer having a top surface in a third plane 1412 overlying the MQW layer 1406 . The electrical insulator with the first portion 1414a is formed as a layer with a top surface in the fourth plane 1416 overlying the second doped semiconductor 1410 . The second insulator 1414b covers the first doped semiconductor peripheral trench valley 1418 .

The first electrode 1420 covers the platform and is connected to the second doped semiconductor 1410 through the platform via 1423 . The first electrode 1420 has a substrate interface surface in the fifth plane 1422 . second electrode There is a first portion 1424a that covers the perimeter trench valley 1418. The second electrode has a first portion 1424a covering the peripheral trench valley 1418 and is connected to the first doped semiconductor 1402 through peripheral vias 1426 . The second electrode second portion 1424b is formed to cover the perimeter of the electrical insulator first portion 1414a having the substrate interface surface in the fifth plane 1422. The first doped semiconductor peripheral trench valley 1418 has a top surface formed in a sixth plane 1428 below the first plane 1408 .

In one aspect, the first doped semiconductor 1402 and the second doped semiconductor 1410 are doped GaN. Alternatively, the first doped semiconductor 1402 and the second doped semiconductor 1410 are p-doped p-GaP or n-doped n-GaInP. As shown, the SM full area light emitting μLED may include a plurality of first doped semiconductor peripheral trench valleys 1418 . In that case, a second electrode first portion 1424a is formed on each peripheral trench valley 1418 and is connected to the first doped semiconductor 1402 by a corresponding peripheral via 1426 . The second electrode second portion 1424b covers the peripheral portion of the electrical insulator first portion 1414a having the substrate interface surface in the fifth plane 1422.

The first doped semiconductor 1402, the MQW layer 1406 and the second doped semiconductor 1410 form an etch stack having a height 1430 orthogonal to the first plane 1404, the second plane 1408 and the third plane 1412 of less than 2 microns , with a flatness tolerance of less than 10 nm for the first, second, third and fourth planes. The average flatness tolerance of the electrode interface surface in the fifth plane is also less than 10 nm.

In one aspect, not shown, the solder layer forms part of the first and second electrode interface surfaces and is made of an alloy such as indium/tin (In/Sn) or gold/germanium (Au/Ge). Alternatively, the substrate interface surfaces of the first and second electrodes are gold. Optionally, as shown, a navigation keel or post 1432 is attached to the first doped semiconductor substrate bottom surface 1434 .

15A to 15C are plan views comparing the light emitting surface areas of microLEDs with center emission (FIG. 11A), peripheral emission (FIG. 13A), and full area emission (FIG. 14A). If a large light emitting area is required, the all-emitter design of Figure 14A can be employed. The active light-emitting region is also a mechanical support island for the P-pad electrode, so that openings (3 shown) in the active island (platform) are formed to contact n-GaN region. In this case, the light-emitting area is about 75% of the diameter of the micro-LED disk. For GaAs-based devices, the three-contact geometry is generally more advantageous compared to the four-contact variant because there is only one thin area on any split plane, making the microLEDs more mechanically robust. Another advantage of the all-emissive structure is that etch damage to the device periphery has less effect on efficiency. This is especially important for AlGaInP devices, where surface reorganization due to etch damage results in reduced luminescence around the perimeter of the LED, limiting the emission of small micro LEDs.

The micro LED design described herein is compatible with conventional MOCVD fabrication and facilitates fluidic assembly and integration with surface mount electrodes formed on the same plane. Another benefit of the described structure is the flexibility to change the light emitting area from 10% to 75% of the micro-LED area without changing the physical properties (diameter, thickness, sidewall angles, and studs) that are critical for successful fluidic assembly. size).

FIG. 16 is a flowchart illustrating a method for fabricating SM μLEDs. Although the method is described as a series of numbered steps for clarity, the numbering does not necessarily indicate the order of the steps. It should be understood that some of these steps may be skipped and performed concurrently or without maintaining a strict order. Generally, however, the method follows the numerical order of the steps depicted. The method begins at step 1600.

Step 1602 provides a MOCVD LED structure including a growth substrate, a stack overlying the growth substrate including a first doped semiconductor having a top surface in a first plane, overlying a second plane having a top surface. A surface MQW layer of a first doped semiconductor, and a second doped semiconductor overlying the MQW layer and having a top surface in a third plane, see Figures 1A and 2A. The first and second doped semiconductors are oppositely doped with n and p dopants. The specific semiconductor materials that can be used are mentioned above.

Step 1604 etches the MOCVD stack to form a plurality of individual wafers on the growth substrate. Step 1606 fabricates μLEDs from each wafer as follows. Step 1606a selectively etches the stack. Step 1606b conformally deposit an electrical insulator to form a top surface on the fourth plane overlying the etch stack noodle. Step 1606c selectively etches to expose the second doped semiconductor, thereby forming the first via. Step 1606d selectively etches to expose the first doped semiconductor, thereby forming a second via. Note: In some cases step 1606d may be performed prior to step 1606c, or may be performed concurrently with appropriate lithography and patterning. Step 1606e forms a first electrode covering the first via, connecting the second doped semiconductor through the first via, and having a substrate interface surface in the fifth plane. Step 1606f forms a second electrode covering the second via, connecting the first doped semiconductor through the second via, and having a substrate interface surface in the fifth plane. In some aspects, steps 1606e and 1606f may be performed in reverse order or concurrently with appropriate lithography and patterning. Step 1608 separates the fabricated μLED from the growth substrate.

In one aspect, the method fabricates a center-emitting μLED, in which case selectively etching the stack (step 1606a) includes creating a center mesa stack surrounded by trenches exposing the first doped semiconductor, and by exposing the first doped semiconductor A perimeter stack of doped semiconductors with perimeter trench valley segmentation. Conformally depositing an electrical insulator on the etched stack in step 1606b includes forming a fourth plane overlying the central mesa stack and the perimeter stack. Selectively etching to expose the second doped semiconductor in step 1606c includes etching a portion of the electrical insulator overlying the center mesa stack to create a first via, and selectively etching to expose the first doped semiconductor in step 1606d This includes etching an electrical insulator covering the perimeter trench valley to create a second via. Then, forming the first electrode in step 1606e includes forming the first electrode overlying the central mesa stack, connecting the second doped semiconductor via the first via. Forming the second electrode in step 1606f includes forming a second electrode having a first portion formed on the peripheral trench valley, the first portion being connected to the first doped semiconductor through a second via, and forming a second electrode Two parts, the second part covering the electrical insulator formed on the perimeter stack, having the substrate interface surface in the fifth plane.

On the other hand, the method fabricates a peripherally emitting μLED by selectively etching the MOCVD stack (step 1606a) to create a central mesa stack separated from the peripheral stack by exposing trenches of the first doped semiconductor. Conformally depositing the electrical insulator in step 1606b includes forming A fourth plane covering the center platform stack and the perimeter stack. Selectively etching to expose the second doped semiconductor in step 1606c includes etching a portion of the electrical insulator covering the perimeter stack to expose the second doped semiconductor. Selectively etching to expose the first doped semiconductor in step 1606d includes etching a portion of the electrical insulator and an underlying portion of the second doped semiconductor and the MQW layer in the center mesa stack to expose the first doped semiconductor. Forming the first electrode in step 1606e includes forming the first electrode overlying the electrical insulator formed on the perimeter stack and connecting the second doped semiconductor through the first via. Forming the second electrode in step 1606f includes forming a second electrode overlying the central mesa stack and connecting the first doped semiconductor via a second via.

In another variation, the method fabricates full-area light emission by selectively etching the MOCVD stack (step 1606a) to form a mesa stack and in the mesa stack to expose peripheral trench valleys of the first doped semiconductor μLEDs. Selectively etching to expose the second doped semiconductor in step 1606c includes etching a portion of the electrical insulator covering the mesa stack to expose the second doped semiconductor. Selectively etching to expose the first doped semiconductor in step 1606d includes etching an electrical insulator overlying the perimeter trench valley. Forming the first electrode in step 1606e includes forming a first electrode overlying the mesa stack and connecting to the second doped semiconductor through a first via. Forming the second electrode in step 1606f includes: forming a first portion of the second electrode, the first portion covering the peripheral trench vias connected to the first doped semiconductor by the second vias; and forming a second portion, the second portion An electrical insulator formed on the perimeter of the platform stack is covered and has a substrate interface surface in a fifth plane.

As described above, step 1608 produces a μLED having a maximum cross-section of 150 microns coplanar with the first, second and third planes, a mesa stack ( etch stack) height is less than 2 microns, and the average fifth plane flatness tolerance is less than 10 nanometers.

17 is a flowchart illustrating a method for fabricating a display substrate having a well bottom surface spacer. Although the method is described as a series of numbered steps for clarity, the numbering does not necessarily represent the order of the steps. It should be understood that some of these steps may be skipped and executed concurrently line or execute without requiring strict ordering. Generally, however, the method is as described above, and generally follows the numerical order of the steps presented below.

The method begins at step 1700. Step 1702 provides a support substrate with a flat top surface and an LED intersection control matrix including an array of column and row wires. Step 1704 forms an array of convex well bottom structures overlying the top surface of the support substrate. Step 1706 forms a first thin film layer overlying the top surface of the support substrate and the convex well bottom structure. Step 1708 forms wells in the first thin film layer and exposes the raised well bottom structure. Step 1710 fluidly deposits surface mount micro LEDs in the wells.

In one aspect, forming the array of convex well bottom structures in step 1704 includes, for each convex well bottom structure, forming a first substrate electrode electrically connecting the corresponding column line and a second substrate electrode electrically connecting the corresponding row line. On the other hand, before forming the first thin film layer, step 1704a forms an array of spacers covering the top surface of the support substrate. Gaskets can be conductive or insulating materials. Step 1704b forms a second thin film layer overlying the pad array.

In one aspect, forming the array of spacers in step 1704a includes forming spacers having a width and a top surface. Then, forming the wells in the first thin film layer in step 1708 includes forming the wells having a diameter (cross-section) greater than the width of the spacer. The shape of the convex bottom surface of the well responds to the difference in height between the top surface of the pad and the top surface of the support substrate.

On the other hand, forming the array of convex well bottom structures in step 1704 includes additional sub-steps. Step 1704c forms a central first substrate electrode having a first dielectric surface for electrically connecting the micro LEDs. Step 1704d forms a peripheral second substrate electrode having a second electrical interface surface defined below the first electrical interface surface relative to the top surface of the support substrate for electrically connecting the micro LEDs.

In yet another aspect, forming the array of pads in step 1704a includes forming each pad directly overlying (in electrical contact with) the column lines, forming column interconnect pads. Then, forming a second thin film layer in step 1704b includes forming vias in the second thin film layer overlying each column interconnect pad, and forming a second thin film layer in step 1704b Forming the central first substrate electrode in 1704c includes forming the central first substrate electrode overlying the via and electrically connecting the column interconnect pads.

Deposition of surface mount micro-LEDs in step 1710 typically involves filling the well with a micro-LED having a top surface having a central first electrode and a peripheral second electrode and a substrate interface surface, the substrate interface surfaces respectively connecting the first a substrate electrode and a second substrate electrode. In one aspect, a microLED has a central first electrode and a peripheral second electrode with coplanar substrate interface surfaces, such as the center-emitting, peripheral-emitting, and full-area-emitting microLEDs described in detail above. Alternatively, the micro LED may have non-coplanar central first electrode and peripheral second electrode substrate interface surfaces, as shown in Figures 9D and 9E.

Planar surface mount micro-LEDs and associated fabrication processes have been shown. Examples of specific semiconductor materials, geometries, and explicit process steps have been shown to illustrate the invention. However, the present invention is not limited only to these examples. Other modifications and embodiments of the invention will occur to those skilled in the art.

300:SM-LED

306: First electrical contact

308: Second electrical contact

402: the second semiconductor layer

404: first semiconductor layer

406:MQW layer

408: Electrical Insulator

Claims (19)

A light emitting display substrate improved by comprising: a support substrate having a planar top surface and a light emitting diode (LED) cross point control matrix including an array of column and row wires; a first thin film layer covering the support substrate and includes a plurality of wells; wherein each well has a convex bottom surface, a first substrate electrode connected to a corresponding column conductor, and a second substrate electrode connected to a corresponding row conductor; wherein the light-emitting The display substrate further includes: a second thin film layer located between the top surface of the support substrate and the first thin film layer; a pad located between the top surface of the support substrate and the second thin film layer and below the bottom of each well piece. The light-emitting display substrate of claim 1, wherein each well of the first thin film layer has a first diameter; wherein the spacer has a width smaller than the first diameter and a top surface; wherein the The convex bottom surface of the well is due to the height difference between the top surface of the spacer and the top surface of the support substrate. The light-emitting display substrate of claim 1, wherein the spacer is selected from conductive materials and electrically insulating materials. The light-emitting display substrate of claim 1, wherein the first substrate electrode is a center substrate electrode having a first electrical interface surface for electrically connecting the micro LED, and the second substrate electrode is a second electrical interface Peripheral substrate electrodes of the interface surface, defined relative to the top surface of the support substrate, the second electrical interface surface is lower than the first electrical interface surface and is used to electrically connect the micro LEDs. The light-emitting display substrate according to claim 1, wherein the pads directly cover the column wires to form a column of interconnect pads; wherein the second thin film layer comprises a pad covering the column interconnect pads holes; and Wherein, the first substrate electrode is a central substrate electrode covering the via hole and connecting the column interconnect pad. The light-emitting display substrate of claim 4, wherein the light-emitting display substrate further comprises: a plurality of surface mount micro-LEDs filling the plurality of wells, each micro-LED having a center first electrode and a peripheral first electrode The top surfaces of the two electrodes and the substrate interface surfaces respectively connecting the first substrate electrodes and the second substrate electrodes. The light-emitting display substrate of claim 6, wherein the central first electrode and the peripheral second electrode of the micro LED have coplanar substrate interface surfaces. The light-emitting display substrate of claim 7, wherein the surface-mounted micro-LEDs are selected from the group consisting of central-emitting, peripheral-emitting, and full-area-emitting micro-LEDs. The light-emitting display substrate of claim 6, wherein the substrate interface surfaces of the central first electrode of the micro LED and the peripheral second electrode substrate are not coplanar. A method of making a light emitting display substrate, the improvement comprising: providing a support substrate having a planar top surface and a light emitting diode (LED) cross point control matrix including an array of column and row conductors; forming a cover overlying the support an array of convex well bottom structures of a top surface of a substrate; forming a first thin film layer overlying the top surface of the support substrate and the convex well bottom structures; and forming a plurality of wells in the first thin film layer exposing A protruding well bottom structure; wherein forming the array of the protruding well bottom structures includes: for each convex well bottom structure, forming a first substrate electrode electrically connected to the corresponding column conductor and an electrode electrically connected to the corresponding row conductor a second substrate electrode; forming the array of convex well bottom structures comprising: Before forming the first thin film layer, forming an array of spacers covering the top surface of the support substrate; and forming a second film layer covering the array of spacers. The method of claim 10, wherein forming the array of shims includes forming shims having a width and a top surface; wherein forming a plurality of wells in the first thin film layer includes forming a larger diameter than the shims a plurality of wells of sheet width; and wherein a convex bottom surface of the wells is shaped in response to a height difference between a top surface of the shim and a top surface of the support substrate. The method of claim 10, wherein forming the array of spacers comprises forming spacers from a material selected from conductive and electrically insulating materials. The method of claim 10, wherein forming the array of raised well bottom structures comprises: forming a central first substrate electrode having a first electrical interface surface for electrically connecting the micro-LEDs; and forming a second electrical A peripheral second substrate electrode of the interface surface, defined relative to the top surface of the support substrate, the second electrical interface surface is lower than the first electrical interface surface and is used to electrically connect the micro LEDs. The method of claim 13, wherein forming the array of pads comprises: forming each pad directly overlying the column conductors, forming column interconnect pads; wherein forming the second thin film layer comprises forming vias in the second thin film layer overlying each column interconnect pad; and wherein forming the central first substrate electrode includes forming a via overlying and electrically connecting the column interconnect pads The center first substrate electrode. The method of claim 10, wherein the method further comprises: fluidly depositing a plurality of surface mount micro LEDs in the plurality of wells. The method of claim 15, wherein depositing the plurality of surface mount micro-LEDs comprises filling the plurality of wells with a plurality of micro-LEDs having a central first electrode and a peripheral second electrode and a substrate interface surface respectively connecting the first substrate electrode and the second substrate electrode. The method of claim 16, wherein depositing the plurality of surface mount micro LEDs comprises depositing micro LEDs having a central first electrode and a peripheral second electrode coplanar substrate interface surfaces. The method of claim 17, wherein depositing the plurality of surface mount micro LEDs comprises depositing micro LEDs selected from the group consisting of center emission, peripheral emission, and full area emission. The method of claim 16, wherein depositing the plurality of surface mount micro LEDs comprises depositing micro LEDs having non-coplanar central first electrode and peripheral second electrode substrate interface surfaces.

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