TWI750004B - Power drive circuit and method of controlling the same - Google Patents

Abstract

A power drive circuit includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weighting unit, and a comparator. Each gate driver includes a drive resistance setting value. The waveform processing unit outputs an absolute current waveform of an AC power. The weighting unit generates a trigger voltage. When the comparator determines that the absolute current waveform is greater than the trigger voltage, the comparator outputs a slew-rate control signal to each of the gate drivers. When the gate driver receives the slew-rate control signal, the gate driver decreases the drive resistance setting value of the gate driver.

Description

Power drive circuit and its control method

The present invention relates to a power circuit and its control method, in particular to a power circuit and its control method with dynamic adjustment of the drive resistance setting value.

Power switching elements, such as MosFET, IGBT, SiC-MosFET and GaN, are widely used in power electronic systems, such as front-end converters, car charging systems or drive inverters. These power switching elements will cause damage during the energy conversion process. Switching loss. In response to the trend of low loss and high efficiency, the gate drive resistance of the power switching element will be adjusted and the resistance value will be gradually reduced, so that the overlap area of the power switching element during the switching process is reduced, and the loss is further reduced. to raise efficiency. But blindly reducing the drive resistance, the slope of the voltage change (dv/dt) and current change (di/dt) during the switching process will gradually increase, causing the parasitic inductance and coupling capacitance in the line to oscillate and exceed the operating limit of the EMI specification . Therefore, how to achieve the best operating characteristics requires a trade-off between two aspects.

Figure 1A and Figure 1B show the performance verification of the manufacturer's Fuji model 2MBI1400VXB-IGBT module using the dual pulse test platform. Among them, Figure 1A shows the turn _-on voltage slope dv/dt of the drive resistance R _G-On from 0Ω to 4.8Ω, and Figure 1B shows the result of the _{switching loss E ON of the drive resistance R G-On from 0Ω to 4.8Ω.}

Restricted specifications or circuit configuration restrictions. If the turn-on voltage slope dv/dt is designed to be lower than 9kV/s, it can be observed from the result of Fig. 1A that a driver equal to or higher than 2.4Ω is required when using 2MBI1400VXB-IGBT module resistance. The selection of the drive resistance value also determines the operating behavior of the turn-on _{voltage slope dv/dt and the switching loss E ON . As the current I CE of the} power switching element gradually increases, the E _ON loss also increases, and the turn-on voltage slope dv/dt But it started to decrease. If the driving resistance can be switched from 2.4Ω to 0Ω when the current I _{CE is} higher than 800A, not only can the design requirement of 9kV/s slope upper limit be maintained, but the E _ON loss can also be greatly reduced. Based on this idea, the slew-rate control (SRC) drive method is gradually replacing the traditional circuit architecture.

The traditional SRC function activation method uses the current and temperature information of the power switching element as the judgment condition. The information obtained is controlled by hardware or firmware. The advantages and disadvantages of these two methods will be described below.

Using hardware circuit to detect current and temperature information to control EN _SRC signal example circuit is shown in Figure 2. The load current feedback information is compared with the preset current level through the signal processing circuit. When the load current is higher than the current level, the EN _SRC signal is set to the start state, and vice versa. In addition, temperature information can also be used for startup judgment. When the temperature exceeds the judgment point at which the SRC function needs to be activated, the EN _SRC signal is set to the startup state to reduce switching loss and lower the operating temperature of the power switching element. Figure 2 is an example of single-phase output operation. If the line is a three-phase system, the same signal and comparison configuration need to be added to three groups. The added components will affect the volume and size of the circuit board, and the temperature and current judgment circuit can be selected according to actual needs.

Using the firmware program to determine the startup of the SRC function is shown in Figure 3. Compared with the hardware configuration, which requires complicated circuit components and increased circuit board production space, the microprocessor (control unit) itself will obtain such results. With the characteristics of current and temperature information, and by writing a highly flexible program, the SRC driving method can be realized.

However, the use of hardware or firmware for judgment and control has its disadvantages. As shown in Figure 4, although the hardware circuit implementation requires additional components, it not only reduces the layout efficiency of the circuit board, but also because the comparison level of the SRC cannot be modified at will after the components are selected. However, its fast response can robustly reflect the rapid changes of the comparative signal, and achieve the use of the SRC function with high accuracy; while the firmware program improves the problem of circuit board layout and comparative level control, but it is limited by the microprocessor The problem of sampling the sensing signal will occur in the rapid change of the sensing signal, and may cause the use of the SRC function to malfunction.

As shown in Figure 5, using current information as a reference for SRC comparison level, in actual circuit operation, due to the problem of microprocessor signal sampling, the operating characteristics of current ripple will be ignored in the firmware implementation of the SRC method. , So that the start signal EN _SRC is not correct, so that the power switching element cannot act according to the expected result.

For this reason, how to design a power drive circuit and its operation method, by adopting the characteristics of high response action of the hardware circuit to the sensing signal, and using the weight circuit combined with the firmware program to flexibly adjust the setting value of the drive resistance of the gate driver to achieve It is an important subject studied by the inventor of the present invention to dynamically adjust the setting value of the drive resistance of the gate driver according to the optimization program in different use occasions to have the ability to activate the SRC function with high accuracy.

The purpose of the present invention is to provide a power drive circuit to solve the problems of the prior art.

In order to achieve the aforementioned purpose, the power driving circuit proposed by the present invention includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weighting unit, and a comparator. The power conversion module includes a plurality of switches, and the power conversion module receives DC power to output AC power. Each gate driver is respectively connected to the control terminal of each switch, and each gate driver includes a drive resistance setting value. The waveform processing unit is coupled to the AC current signal of the AC power to output the current absolute value waveform of the AC current signal. The control unit adjusts the duty cycle of the first pulse width modulation signal according to the AC voltage signal of the DC power supply and the AC power to output the second pulse width modulation signal. The weight unit obtains the average voltage of the second pulse width modulation signal, and superimposes the average voltage and the trigger level signal to generate the trigger voltage. When the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each gate driver. When each gate driver receives the slew rate control signal, the drive resistance setting value of each gate driver is reduced.

In one embodiment, when the comparator determines that the current absolute value waveform is not greater than the trigger voltage, the comparator stops outputting the slew rate control signal to restore the drive resistance setting value of each gate driver.

In one embodiment, the control unit is further used to detect the operating temperature of the power conversion module; when the control unit determines that the operating temperature is higher than the temperature threshold, the control unit adjusts the duty cycle of the first pulse width modulation signal to zero .

In one embodiment, the control unit controls the multiple gate drivers according to the current absolute value waveform to adjust the multiple switches to be selectively turned on or off respectively.

In an embodiment, the waveform processing unit includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit receives the reference voltage, wherein the first arithmetic unit inverts the alternating current signal to generate a first processing waveform, and the first arithmetic unit reserves a portion of the first processing waveform lower than the reference voltage to form a second processing waveform. The second arithmetic unit amplifies the second processed waveform to generate a third processed waveform, wherein the second arithmetic unit superimposes the third processed waveform and the alternating current signal to form a fourth processed waveform, and the second arithmetic unit inverts the fourth processed waveform to Absolute value waveform of output current.

In an embodiment, the first arithmetic unit includes a first operational amplifier, a first resistor, a second resistor, a third resistor, a first diode, and a second diode. The first operational amplifier includes a negative input terminal, a positive input terminal and an output terminal. The first end of the first resistor is coupled to the AC current signal, and the second end of the first resistor is connected to the negative input end of the first operational amplifier. The first end of the second resistor is coupled to the reference voltage, and the second end of the second resistor is connected to the positive input end of the first operational amplifier. The first end of the third resistor is connected to the second end of the first resistor. The anode of the first diode is connected to the second end of the third resistor. The negative electrode of the second diode is connected to the second end of the first resistor, and the positive electrode of the second diode is connected to the negative electrode of the first diode and the output terminal of the first operational amplifier to generate the second processing waveform.

In an embodiment, the second arithmetic unit includes a fourth resistor, a fifth resistor, a sixth resistor, a second operational amplifier, and a seventh resistor. The first end of the fourth resistor is connected to the second end of the third resistor. The first end of the fifth resistor is connected to the first end of the first resistor, and the second end of the fifth resistor is connected to the second end of the fourth resistor. The first end of the sixth resistor is connected to the second end of the fifth resistor and the second end of the fourth resistor. The second operational amplifier includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal of the second operational amplifier is connected to the first terminal of the sixth resistor, and the output terminal of the second operational amplifier is connected to the second terminal of the sixth resistor. . The first end of the seventh resistor is connected to the first end of the second resistor, and the second end of the seventh resistor is connected to the positive input end of the second operational amplifier.

In one embodiment, the size of the fourth resistor is half the size of the sixth resistor.

In an embodiment, the weight unit includes a low-pass filter, an eighth resistor, and a ninth resistor. The low-pass filter receives the second pulse width modulation signal to output the average voltage of the second pulse width modulation signal. The first terminal of the eighth resistor receives the average voltage. The first end of the ninth resistor is coupled to contact the level signal, and the second end of the ninth resistor is connected to the second end of the eighth resistor to generate a trigger voltage.

In one embodiment, the relationship between the trigger voltage, the average voltage, and the trigger level signal is: Vx=(V1×R9)/(R8+R9)+(V2×R8)/(R8+R9).

With the proposed power drive circuit, it is possible to adopt the characteristics of high response action of the hardware circuit to the sensing signal, and use the weight circuit combined with the firmware program to flexibly adjust the SRC comparison level, so that it can be used in different occasions according to the most Optimized program to dynamically adjust the setting value of the drive resistance of the gate driver to have a high accuracy SRC function start-up capability.

Another object of the present invention is to provide an operating method of a power drive circuit to solve the problems of the prior art.

In order to achieve the purpose of the foregoing disclosure, the operating method of the power drive circuit proposed by the present invention is used to control the power conversion module. The operating method includes: converting DC power into AC power through the power conversion module; The current absolute value waveform of the AC current signal of the AC power; adjust the duty cycle of the first pulse width modulation signal according to the DC power supply and the AC voltage signal of the AC power to form the second pulse width modulation signal; obtain the second pulse wave Width modulates the average voltage of the signal; superimposes the average voltage and the trigger level signal to generate the trigger voltage; and compares the absolute value waveform of the current with the trigger voltage. When the absolute value of the current waveform is greater than the trigger voltage, the slew rate control signal is output to each gate driver. When each gate driver receives the slew rate control signal, the setting value of the driving resistance of each gate driver is reduced.

In one embodiment, when the absolute value of the current waveform is not greater than the trigger voltage, the output of the slew rate control signal is stopped to restore the setting value of the driving resistance of each gate driver.

In one embodiment, the operation method further includes: detecting the operating temperature of the power conversion module. When the operating temperature is higher than the temperature threshold, the duty cycle for adjusting the first pulse width modulation signal is zero.

In one embodiment, the operation method further includes: controlling a plurality of gate drivers according to the waveform of the absolute value of the current to respectively adjust the plurality of switches to be selectively turned on or off.

In one embodiment, the absolute value calculation procedure includes: inverting the alternating current signal to generate the first processing waveform; retaining the portion of the first processing waveform lower than the reference voltage to form the second processing waveform; amplifying the second processing waveform to generate The third processing waveform; the third processing waveform and the alternating current signal are superimposed to form the fourth processing waveform; and the fourth processing waveform is inverted to output the current absolute value waveform.

With the proposed operation method of the power drive circuit, it is possible to adopt the characteristics of high response action of the hardware circuit to the sensing signal, and use the weight circuit combined with the firmware program to flexibly adjust the SRC comparison level, so that it can be used in different applications. , According to the optimization program to dynamically adjust the drive resistance setting value of the gate driver to have a high accuracy SRC function start-up capability.

In order to further understand the technology, means and effects of the present invention to achieve the intended purpose, please refer to the following detailed description and drawings of the present invention. I believe that the purpose, features and characteristics of the present invention can be obtained from this in depth and For specific understanding, however, the accompanying drawings are only provided for reference and illustration, and are not intended to limit the present invention.

The technical content and detailed description of the present invention are described as follows in conjunction with the drawings.

Please refer to FIG. 6, which is a circuit block diagram of the power driving circuit of the present invention. The power driving circuit includes a power conversion module 20, a plurality of gate drivers 31, 32, a waveform processing unit 10, a control unit 12, a weighting unit, and a comparator 16. The power conversion module 20 includes a plurality of switches. In one embodiment, each on-state relationship is an insulated gate bipolar transistor (IGBT), but this is not a limitation for the power conversion module 20 to receive DC Power supply DC+, DC- to output AC power (including AC voltage signal Vo and AC current signal iload).

Each gate driver 31, 32 is respectively connected to the control terminal of each switch (take IGBT as an example, the control terminal is a gate terminal), and each gate driver 31, 32 includes a drive resistance set value R _{G -On1, R G-Off1, R} G-On2, R G-Off2, be detailed below.

The waveform processing unit 10 is coupled to the AC current signal iload of the AC power to output the current absolute value waveform |Vc| of the AC current signal iload. Please refer to FIG. 7 and FIG. 8, which are divided into the circuit diagram of the waveform processing unit of the present invention and the waveform diagram of the operation of the waveform processing unit. The waveform processing unit 10 includes a first arithmetic unit and a second arithmetic unit. The first arithmetic unit receives the reference voltage Vos, wherein the first arithmetic unit inverts the alternating current signal iload to generate the first processing waveform, and the first arithmetic unit retains the portion of the first processed waveform lower than the reference voltage Vos to form the second processing Waveform Va (with Figure 8 (b) shown). The second arithmetic unit amplifies the second processed waveform Va to generate a third processed waveform, wherein the second arithmetic unit superimposes the third processed waveform and the alternating current signal iload to form a fourth processed waveform (as shown in FIG. 8(c)), The second arithmetic unit inverts the fourth processing waveform to output the current absolute value waveform |Vc| (coordinated with the one shown in FIG. 8(d)).

In some embodiments, according to the magnitude of the current absolute value waveform |Vc| output by the waveform processing unit 10, the control unit 12 respectively adjusts the duty cycles of the control signals e-PWM-N and ePWM-U to control multiple gate drivers 31, 32 to adjust the multiple switches 21, 22 to selectively turn on or off.

In some embodiments, a current sensor (not shown) is usually provided in the waveform processing unit 10, such as a Hall sensor. Therefore, the waveform processing unit 10 can detect and receive the AC current signal iload in the AC power signal. Of course, the present invention is not limited to this.

Specifically, the first operation unit includes a first operational amplifier OPA1, a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1, and a second diode D2. The first operational amplifier OPA1 includes a negative input terminal, a positive input terminal and an output terminal. The first end of the first resistor R1 is coupled to the AC current signal iload, and the second end of the first resistor R1 is connected to the negative input end of the first operational amplifier OPA1. The first end of the second resistor R2 is coupled to the reference voltage Vos, and the second end of the second resistor R2 is connected to the positive input end of the first operational amplifier OPA1. The first end of the third resistor R3 is connected to the second end of the first resistor R1. The anode of the first diode D1 is connected to the second end of the third resistor R3. The negative electrode of the second diode D2 is connected to the second end of the first resistor R1, and the positive electrode of the second diode D2 is connected to the negative electrode of the first diode D1 and the output terminal of the first operational amplifier OPA1 to generate the second process Waveform Va. In some embodiments, the first end of the first resistor R1 is connected to a current sensor (not shown) provided in the waveform processing unit 10 to receive the AC current signal iload, but the invention is not limited to this.

The second operation unit includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second operational amplifier OPA2, and a seventh resistor R7. The first end of the fourth resistor R4 is connected to the second end of the third resistor R3. The first end of the fifth resistor R5 is connected to the first end of the first resistor R1, and the second end of the fifth resistor R5 is connected to the second end of the fourth resistor R4. The first end of the sixth resistor R6 is connected to the second end of the fifth resistor R5 and the second end of the fourth resistor R4. The second operational amplifier OPA2 includes a negative input terminal, a positive input terminal, and an output terminal. The negative input terminal of the second operational amplifier OPA2 is connected to the first terminal of the sixth resistor R6, and the output terminal of the second operational amplifier OPA2 is connected to the second terminal of the sixth resistor R6. The first end of the seventh resistor R7 is connected to the first end of the second resistor R2, and the second end of the seventh resistor R7 is connected to the positive input end of the second operational amplifier OPA2. The waveform processing unit 10 shown in FIG. 7 is one of the circuits that can be implemented. However, the implementation circuit does not limit the present invention. Any circuit that can be used as a signal absolute operation can be used as the waveform processing unit of the present invention.

In some embodiments, the size of the fourth resistor R4 is half of the size of the sixth resistor R6, so the second arithmetic unit amplifies the second processing waveform Va twice the original second processing waveform Va to generate the third processing waveform 2Va, but the present invention is not limited to this.

The control unit 12 receives the AC voltage signal Vo of the DC power supply DC+, DC- and the AC power, and adjusts the duty cycle of the first pulse width modulation signal (not shown) according to the DC power supply DC+, DC- and the AC voltage signal Vo ( duty cycle) to output the second pulse width modulation signal ePWM. Among them, the second pulse width modulation signal ePWM is a signal after the duty cycle is adjusted compared to the first pulse width modulation signal (not shown in the figure). In this embodiment, the control unit 12 may be a digital controller, that is, it has the functions of digital signal processing, calculation, and control. It may be, but is not limited to, a microcontroller (MCU), a digital signal processor (digital signal processor, DSP), field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC).

In some other embodiments, the first pulse width modulation signal (not shown) is a signal provided in the control unit 12, and the control unit 12 usually depends on the direct current power DC+, DC received by the power conversion module 20 -And/or output AC power (including AC voltage signal Vo and/or AC current signal iload) to adjust the duty cycle of the first pulse width modulation signal (not shown) to output the second pulse Width modulation signal ePWM. Generally, the AC power includes an AC current signal iload and/or an AC voltage signal Vo, but the present invention is not limited thereto.

The weighting unit 14 obtains the average voltage V1 of the second pulse width modulation signal ePWM, and superimposes the average voltage V1 and the trigger level signal iload-level to generate the trigger voltage Vx. Details will be explained later. The comparator 16 is coupled to the weighting unit 14 and the waveform processing unit 10, receives the trigger voltage Vx and the current absolute value waveform |Vc|, and compares the trigger voltage Vx and the current absolute value waveform |Vc|. Details will be explained later. Wherein, when the comparator 16 determines that the current absolute value waveform |Vc| is greater than the trigger voltage Vx, the comparator 16 outputs the slew rate control signal EN _SRC to each gate driver 31, 32.

When each gate driver 31, 32 does not receive the slew rate control signal EN _SRC , and the control signal ePWM-U output by the control unit 12 turns on the upper switch 21 of the power conversion module 20, and the control signal output by the control unit 12 Close ePWM-N power conversion module 22 at switch 20, the gate driver drives the resistance value R _G-On1 set the gate driver 31 R _G-Off2 32 for parallel operation. Conversely, when the control signal ePWM-U output by the control unit 12 turns off the upper switch 21 and the output control signal ePWM-N turns on the lower switch 22, the drive resistance setting value R _G-Off1 of the gate driver 31 and the R _{G of the gate driver 32 -On2} is parallel operation.

When each gate driver 31, 32 receives the slew rate control signal EN _SRC , more resistors are connected in parallel to reduce the drive resistance setting value R _G-On1 , R of each gate driver 31, 32 respectively _G-Off1 , R _G-On2 , R _G-Off2 . When each gate driver 31, 32 receives the slew rate control signal EN _SRC , the drive resistance setting value of each gate driver 31, 32 is set by all the drive resistance setting values R _G-On1 , R _G-On2 It is determined in parallel with the drive resistance setting values R _G-Off1 and R _G-Off2. Thus, when all the driving resistance setting value _{R G-On1, R G-} Off1, R G-On2, when R _G-Off2 parallel, each gate driver drives a set value of the resistance 31 and 32 will be cut.

For example, when each gate driver 31, 32 receives the slew rate control signal EN _SRC , if the control signals ePWM-U and ePWM-N output by the control unit 12 respectively turn on the upper switch 21 and turn off the lower switch 22, then The drive resistance setting values R _G-On1 and R _G-On2 of the gate driver 31 are parallel operation, and the drive resistance setting values R _G-Off1 and R _G- Off2 of the gate driver 32 are parallel operation. Similarly, when each gate driver 31, 32 receives the slew rate control signal EN _SRC , if the control signals ePWM-U and ePWM-N output by the control unit 12 respectively close the upper switch 21 and turn on the lower switch 22, the gate driver drives the resistance setting value R _G-Off1 and R _G-Off2 31 are operated in parallel, and driving the gate resistance R _G-On1 set value R _G-On2 and 32 operate in _parallel. In this way, when each gate driver 31, 32 receives the slew rate control signal EN _SRC , the drive resistance values connected to the upper switch 21 and the lower switch 22 will be reduced, so that the upper switch 21 and the lower switch 22 The switching loss is also reduced, as shown in Figure 1B.

Please refer to FIG. 9 and FIG. 10, which are divided into the circuit diagram of the weight unit of the present invention and the circuit block diagram of the weight unit applied to the power driving circuit. As shown in FIG. 9, the weight unit 14 mainly has three terminals, including a first input terminal for receiving a first input voltage V1, a second input terminal for receiving a second input voltage V2, and a trigger voltage Vx. The output terminal. Specifically, as shown in FIG. 10, the weight unit 14 includes a low-pass filter 141, an eighth resistor R8, and a ninth resistor R9. The low-pass filter 141 receives the second pulse width modulation signal ePWM to output the average voltage V1 of the second pulse width modulation signal ePWM. The first end of the eighth resistor R8 receives the average voltage V1. The first end of the ninth resistor R9 is coupled to the level signal iload-level (ie voltage V2), and the second end of the ninth resistor R9 is connected to the second end of the eighth resistor R8 to generate the trigger voltage Vx.

The weight unit 14 includes an eighth resistor R8, a ninth resistor R9, and a capacitor Cw. One end of the eighth resistor R8, one end of the ninth resistor R9, and one end of the capacitor Cw are commonly connected to the output end, and the other end of the eighth resistor R8 is the first input end, and the other end of the ninth resistor R9 is the second input end And the other end of the capacitor Cw is connected to the ground terminal. Therefore, for the weighting unit 14 as shown in the figure, the relationship between the output trigger voltage Vx and the input first input voltage V1 and the second input voltage V2 is:

Vx=(V1×R9)/(R8＋R9)+(V2×R8)/(R8＋R9)

In the present invention, the first input voltage V1 is the average voltage V1 of the second pulse width modulation signal ePWM, and the second input voltage V2 is the trigger level signal iload-level.

It can be seen from the above formula that when the eighth resistor R8 and the ninth resistor R9 are fixed, the trigger voltage Vx is controlled by the first input voltage V1 and the second input voltage V2. When the first input voltage V1 and the second input voltage V2 increase at the same time, the trigger voltage Vx increases. When the first input voltage V1 and the second input voltage V2 decrease at the same time, the trigger voltage Vx decreases. If the first input voltage V1 and the second input voltage V2 are rising and falling respectively, the trigger voltage Vx will respond according to the distribution (ratio) of the first input voltage V1 and the second input voltage V2, so it is called For the weight circuit.

When implemented in combination with a microcontroller (ie, the control unit 12) and hardware circuits, the weight unit 14 further includes a low-pass filter 141 and a voltage stabilizing circuit 142. The low-pass filter 141 is coupled to the eighth resistor R8, and receives the second pulse width modulation signal ePWM provided by the control unit 12 to convert the square wave high-frequency signal into a DC signal, which is obtained by the low-pass filter 141 The average voltage of the second pulse width modulation signal ePWM is used as the first input voltage V1. The voltage stabilizing circuit 142 is coupled to the ninth resistor R9 and receives the trigger level signal iload-level to perform a voltage stabilization operation on the trigger level signal iload-level. Therefore, the voltage V2 can also be described as the regulated trigger level Signal iload-level. Among them, the voltage stabilizing circuit 142 may be implemented in the form of a capacitor or a voltage follower circuit.

It is worth mentioning that when using the hardware circuit for the SRC function, it has the correct trigger level signal (such as current trigger level signal or temperature trigger level signal), but because of the trigger level of the trigger signal on the hardware circuit Usually an external fixed voltage signal is generated, and the correction of this trigger signal needs to be achieved by replacing the components on the hardware circuit. In adjusting the trigger level, the hardware circuit is less flexible. However, when the firmware program is used with a microcontroller for the SRC function, the trigger level can be read by reading the input voltage, output voltage, load command or the selected model of the power switching element. In the completed process, it is easy The trigger level is adjusted, but the input information of the firmware program is limited by the sampling speed of the microcontroller, so the response speed of the _{correct slew rate control signal EN SRC is slow.} And Figure 10 is the result of combining the correct slew rate control signal EN _SRC action of the hardware and the adjustable trigger voltage Vx of the firmware program, each based on its advantages.

Please refer to FIG. 11A to FIG. 11C, which are schematic diagrams of the waveforms of the trigger voltage generated in the present invention. According to different duty cycles of the second pulse width modulation signal ePWM, an example of different trigger voltages Vx can be obtained under a fixed trigger level signal iload-level (for convenience only, not to limit the present invention) instruction. The average voltage of the second pulse width modulation signal ePWM is used as the first input voltage V1 of the weighting unit 14, and the trigger level signal iload-level is used as the second input voltage V2 of the weighting unit 14. In addition, it will be described in conjunction with the aforementioned output trigger voltage Vx and the input first input voltage V1 and the second input voltage V2.

Taking FIG. 11A as an example, the second pulse width modulation signal ePWM is output by the control unit 12, which is a square wave signal with a duty cycle of 50%, and the magnitude is 0 to 3.3 volts. The trigger level signal iload-level is generated by the hardware circuit and is a fixed 1.65 volt. Furthermore, it is assumed that the eighth resistor R8 is the same as the ninth resistor R9. Therefore, according to the aforementioned relationship, the trigger voltage Vx can be calculated:

Vx=(3.3×50%×R9)/(R8＋R9)+(1.65×R8)/(R8＋R9)=1.65 volts.

Taking FIG. 11B as an example, the duty cycle of the second pulse width modulation signal ePWM is a 25% square wave signal with a magnitude of 0 to 3.3 volts. The trigger level signal iload-level is a fixed 1.65 volts. Furthermore, it is assumed that the eighth resistor R8 is the same as the ninth resistor R9. Therefore, according to the aforementioned relationship, the trigger voltage Vx can be calculated:

Vx=(3.3×25%×R9)/(R8＋R9)+(1.65×R8)/(R8＋R9)=1.2375 volts.

Taking FIG. 11C as an example, the duty cycle of the second pulse width modulation signal ePWM is an 80% square wave signal with a magnitude of 0 to 3.3 volts. The trigger level signal iload-level is a fixed 1.65 volts. Furthermore, it is assumed that the eighth resistor R8 is the same as the ninth resistor R9. Therefore, according to the aforementioned relationship, the trigger voltage Vx can be calculated:

Vx=(3.3×80%×R9)/(R8＋R9)+(1.65×R8)/(R8＋R9)=2.145 volts.

Therefore, according to the three examples shown in FIGS. 11A to 11C, the second pulse width modulation can still be adjusted by the firmware program and the control unit 12 without changing the voltage of the trigger level signal iload-level. The magnitude of the signal ePWM controls the level of the trigger voltage Vx to achieve a more flexible trigger level correction.

Please refer to FIG. 12, which is a schematic diagram of the waveform of the slew rate control signal generated by the present invention. The trigger voltage Vx obtained by weighting the second pulse width modulation signal ePWM and the trigger level signal iload-level through the weighting unit 14 is compared with the current absolute value waveform |Vc| (via the comparator 16). Refer to Figure 6 for cooperation. When the current absolute value waveform |Vc| is greater than the trigger voltage Vx (but not as a limitation, it can be a judgment of greater than or equal to), the slew rate control signal EN _SRC output by the comparator 16 is the high level, the control gate driver to drive the resistance value R _G-On1 parallel with the _G-On2 R 31, and R _G-Off1 and R _G-Off2 parallel Similarly, the gate driver 32 is also true, so that the gate The setting values of the driving resistance of the driver 31 and the gate driver 32 will be adjusted down. Conversely, if the current absolute value waveform |Vc| is less than or equal to the trigger voltage Vx (but not as a limitation, it can be judged as less than), the slew rate control signal EN _SRC output by the comparator 16 is low level Therefore, the drive resistance setting value of the gate driver 31 is restored, depending on the on or off state of the upper switch 21, it is only the drive resistance setting value R _G-On1 operation or only the drive resistance setting value R _G-Off1 operation, or the next The on or off state of the switch 22 determines whether only the drive resistance set value R _{G-On2 is} operated or only the drive resistance set value R _{G-Off2 is} operated. In the same way, the drive resistance setting value of the gate driver 32 is also restored, depending on the on or off state of the upper switch 21, it is determined that only the drive resistance setting value R _{G-On1 is} operated or only the drive resistance setting value R _{G-Off1 is} operated, or When viewed from the perspective, the state of the switch 22 being turned on or off determines whether only the drive resistance set value R _{G-On2 is} operated or only the drive resistance set value R _{G-Off2 is} operated.

Please refer to FIG. 6 again. The power conversion module 20 further includes a temperature sensor 23 for detecting the operating temperature V _{T of the} power conversion module 20. And the information of the working temperature V _T is sent to the control unit 12. Therefore, when the control unit 12 determines that the operating temperature V _{T is} higher than the temperature threshold, the control unit 12 adjusts the duty cycle of the first pulse width modulation signal to zero. In this way, in accordance with the relationship between the trigger voltage Vx and the input first input voltage V1 and the second input voltage V2, it can be known that once the duty cycle of the first pulse width modulation signal is zero, the trigger voltage calculated according to the relationship Vx will be significantly smaller, so that the absolute value of the current waveform |Vc| is easily greater than the trigger voltage Vx, which can realize that when the working temperature V _{T of the} power conversion module 20 is too high, the value R _{G- can be set through the drive resistance. On1 is} connected in parallel with R _{G-On2 , and R G-Off1} is connected in parallel with R _G-Off 2 to reduce the setting value of the driving resistance of each gate driver 31, 32.

Please refer to FIG. 13, which is a flowchart of the operation method of the power driving circuit of the present invention. The operation method of the power drive circuit is used for the power drive circuit. The operation method includes the steps: first, the DC power supply DC+, DC- is converted into AC power Vo by the power conversion module 20 (S11). Then, the absolute value calculation program is executed to obtain the current absolute value waveform |Vc| of the AC current signal of the AC power (S12). Then, the duty cycle of the first pulse width modulation signal is adjusted according to the AC voltage signals of the DC power supply DC+, DC- and the AC power to form a second pulse width modulation signal ePWM (S13). Then, the average voltage V1 of the second pulse width modulation signal ePWM is obtained (S14). Then, the average voltage V1 and the trigger level signal iload-level are superimposed to generate the trigger voltage Vx (S15). Then, the current absolute value waveform |Vc| is compared with the trigger voltage Vx (S16). When the current absolute value waveform |Vc| is greater than the trigger voltage Vx, the slew rate control signal EN _{SRC is} output to each gate driver 31, 32 (S17). When each gate driver 31, 32 receives the slew rate control signal EN _SRC , the driving resistance setting value of each gate driver 31, 32 is reduced (S18), for example: driving resistance setting R _G-On1 and R _G-On2 parallel, and R _G-Off1 parallel with the _G-Off2 R.

In summary, the present invention has the following features and advantages: the hardware circuit has the characteristics of high response action to the sensing signal, and the weight circuit combined with the firmware program is used to flexibly adjust the drive resistance setting value of the gate driver to achieve In different application situations, the drive resistance setting value of the gate driver is dynamically adjusted according to the optimization program to have a high-accuracy SRC function start-up capability. Moreover, the user can also customize the operation through the man-machine interface or communication method to improve the flexibility and diversity of use.

The above are only detailed descriptions and drawings of the preferred embodiments of the present invention. However, the features of the present invention are not limited to these, and are not intended to limit the present invention. The full scope of the present invention should be covered by the following patent application scope As the standard, all embodiments that conform to the spirit of the patent application of the present invention and similar changes should be included in the scope of the present invention. Anyone familiar with the art in the field of the present invention can easily think of changes or Modifications can be covered in the following patent scope of this case.

10: Waveform processing unit

12: Control unit

14: Weight unit

16: comparator

20: Power conversion module

21: Up switch

22: Down switch

23: Temperature sensor

31: Gate driver

32: Gate driver

141: Low-pass filter

142: Voltage stabilizing circuit

R1~R9: resistance

D1~D2: Diode

OPA1: The first operational amplifier

OPA2: second operational amplifier

V _Drive : Drive voltage

R _G-On ,R _G-On1 ,R _G-On2 ,R _G-Off : drive resistance setting value

ePWM: second pulse width modulation signal

EN _SRC : Slew rate control signal

Vo: AC voltage signal

iload: AC current signal

|Vc|: Absolute current waveform

V _T : Working temperature

iload-level: trigger level signal

Vx: trigger voltage

ePWM-U: Control signal

ePWM-N: Control signal

V1: first input voltage

V2: second input voltage

DC+, DC-: DC power supply

S11~S18: steps

Figure 1A: is a graph of the turn-on voltage slope performance of the existing dual-pulse test platform.

Figure 1B: It is a graph of the switching loss performance of the existing dual-pulse test platform.

Figure 2: It is a block diagram of the circuit that generates the slew rate control signal for the existing hardware circuit.

Figure 3: It is a block diagram of a circuit that generates a slew rate control signal for the existing firmware.

Figure 4: This is a schematic diagram of the waveform of misjudgment caused by the use of existing hardware circuits.

Figure 5: This is a schematic diagram of the waveform of misjudgment caused by the use of existing firmware.

Fig. 6 is a circuit block diagram of the power driving circuit of the present invention.

Fig. 7 is a circuit diagram of the waveform processing unit of the present invention.

Fig. 8 is a schematic diagram of waveforms of the operation of the waveform processing unit of the present invention.

Fig. 9 is a circuit diagram of the weight unit of the present invention.

Fig. 10 is a circuit block diagram of the weight unit of the present invention applied to a power drive circuit.

11A to 11C are schematic diagrams showing the waveforms of the trigger voltage generated by the present invention.

Fig. 12 is a schematic diagram of the waveform of the slew rate control signal generated by the present invention.

Fig. 13 is a flowchart of the operation method of the power drive circuit of the present invention.

10: Waveform processing unit

12: Control unit

14: Weight unit

16: comparator

20: Power conversion module

21: Up switch

22: Down switch

23: Temperature sensor

31: Gate driver

32: Gate driver

R _G-On1 ,R _G-Off1 ,R _G-On2 ,R _G-Off2 : drive resistance setting value

ePWM: second pulse width modulation signal

EN _SRC : Slew rate control signal

V _O : AC voltage signal

iload: AC current signal

|Vc|: Absolute current waveform

V _T : Working temperature

iload-level: trigger level signal

V _X : Trigger voltage

ePWM-U: Control signal

ePWM-N: Control signal

DC+, DC-: DC power supply

Claims (15)

A power drive circuit, including: A power conversion module includes a plurality of switches, wherein the power conversion module receives a DC power source to output an AC power; A plurality of gate drivers, wherein each of the plurality of gate drivers is respectively connected to a control terminal of each of the plurality of switches, and each of the plurality of gate drivers includes a driving resistance setting value; A waveform processing unit coupled to an alternating current signal of the alternating current power to output a current absolute value waveform of the alternating current signal; A control unit that adjusts a duty cycle of a first pulse width modulation signal according to the DC power supply and an AC voltage signal of the AC power to output a second pulse width modulation signal; A weighting unit that obtains an average voltage of the second pulse width modulation signal, and superimposes the average voltage and a trigger level signal to generate a trigger voltage; and A comparator, wherein when the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each of the plurality of gate drivers; Wherein, when each of the plurality of gate drivers receives the slew rate control signal, the setting value of the driving resistance of each of the plurality of gate drivers is reduced respectively. The power driving circuit according to claim 1, wherein when the comparator determines that the current absolute value waveform is not greater than the trigger voltage, the comparator stops outputting the slew rate control signal to restore each of the plurality of gates respectively The drive resistance setting value of the drive. The power driving circuit according to claim 1, wherein the control unit is further used to detect an operating temperature of the power conversion module; when the control unit determines that the operating temperature is higher than a temperature threshold, the control unit adjusts The duty cycle of the first pulse width modulation signal is zero. The power drive circuit according to claim 1, wherein the control unit controls the plurality of gate drivers according to the current absolute value waveform to adjust the plurality of switches to be selectively turned on or off respectively. The power drive circuit according to claim 1, wherein the waveform processing unit includes: A first arithmetic unit receives a reference voltage, wherein the first arithmetic unit inverts the alternating current signal to generate a first processing waveform, and the first arithmetic unit retains a portion of the first processing waveform lower than the reference voltage Part to form a second processing waveform; and A second arithmetic unit amplifies the second processed waveform to generate a third processed waveform, wherein the second arithmetic unit superimposes the third processed waveform and the alternating current signal to form a fourth processed waveform, wherein the second The arithmetic unit inverts the fourth processed waveform to output the current absolute value waveform. The power driving circuit according to claim 5, wherein the first arithmetic unit includes: A first operational amplifier including a negative input terminal, a positive input terminal and an output terminal; A first resistor, wherein a first end of the first resistor is coupled to the AC current signal, and a second end of the first resistor is connected to the negative input terminal of the first operational amplifier; A second resistor, wherein a first terminal of the second resistor is coupled to the reference voltage, and a second terminal of the second resistor is connected to the positive input terminal of the first operational amplifier; A third resistor, wherein a first end of the third resistor is connected to the second end of the first resistor; A first diode, wherein an anode of the first diode is connected to a second end of the third resistor; and A second diode, wherein a negative electrode of the second diode is connected to the second end of the first resistor, and a positive electrode of the second diode is connected to a negative electrode of the first diode and the The output terminal of the first operational amplifier generates the second processing waveform. The power driving circuit according to claim 6, wherein the second arithmetic unit includes: A fourth resistor, wherein a first end of the fourth resistor is connected to the second end of the third resistor; A fifth resistor, wherein a first end of the fifth resistor is connected to the first end of the first resistor, and a second end of the fifth resistor is connected to a second end of the fourth resistor; A sixth resistor, wherein a first end of the sixth resistor is connected to the second end of the fifth resistor and the second end of the fourth resistor; A second operational amplifier includes a negative input terminal, a positive input terminal, and an output terminal, wherein the negative input terminal of the second operational amplifier is connected to the first terminal of the sixth resistor, and the second operational amplifier The output terminal is connected to a second terminal of the sixth resistor; and A seventh resistor, wherein a first end of the seventh resistor is connected to the first end of the second resistor, and a second end of the seventh resistor is connected to the positive input end of the second operational amplifier. The power driving circuit according to claim 7, wherein the size of the fourth resistor is half of the size of the sixth resistor. The power drive circuit according to claim 1, wherein the weight unit includes: A low-pass filter receiving the second pulse width modulation signal to output the average voltage of the second pulse width modulation signal; An eighth resistor, wherein a first end of the eighth resistor receives the average voltage; and A ninth resistor, wherein a first end of the ninth resistor is coupled to the trigger level signal, and a second end of the ninth resistor is connected to a second end of the eighth resistor to generate the trigger voltage. The power drive circuit according to claim 9, wherein the relationship between the trigger voltage, the average voltage, and the trigger level signal is:

. A control method for a power drive circuit, wherein the power drive circuit includes a power conversion module and a plurality of gate drivers, and each of the plurality of gate drivers is respectively connected to each of the power conversion modules Switches, and each of the plurality of gate drivers includes a drive resistance setting value, wherein the control method includes: Convert the DC power into an AC power through the power conversion module; Execute an absolute value calculation program to obtain a current absolute value waveform of an alternating current signal of the alternating current power; Adjusting a duty cycle of a first pulse width modulation signal according to the DC power supply and an AC voltage signal of the AC power to form a second pulse width modulation signal; Obtaining an average voltage of the second pulse width modulation signal; Superimpose the average voltage and a trigger level signal to generate a trigger voltage; and Compare the absolute value waveform of the current with the trigger voltage; When the absolute value waveform of the current is greater than the trigger voltage, output a slew rate control signal to each of the plurality of gate drivers; When each of the plurality of gate drivers receives the slew rate control signal, the setting value of the driving resistance of each of the plurality of gate drivers is reduced respectively. The control method according to claim 11, wherein when the current absolute value waveform is not greater than the trigger voltage, the output of the slew rate control signal is stopped to restore the setting value of the driving resistance of each of the plurality of gate drivers. The control method described in claim 11 further includes: Detecting a working temperature of the power conversion module; When the operating temperature is higher than a temperature threshold, the duty cycle for adjusting the first pulse width modulation signal is zero. The control method according to claim 11, further comprising: controlling the plurality of gate drivers according to the current absolute value waveform to respectively adjust the plurality of switches to be selectively turned on or off. The control method according to claim 11, wherein the absolute value operation program includes: Inverting the alternating current signal to generate a first processing waveform; Retaining a portion of the first processing waveform lower than a reference voltage to form a second processing waveform; Amplify the second processing waveform to generate a third processing waveform; Superimposing the third processing waveform and the alternating current signal to form a fourth processing waveform; and The fourth processed waveform is inverted to output the current absolute value waveform.

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