TWI749010B - Co-integration of gan and self-aligned thin body group iv transistors - Google Patents

Abstract

Techniques are disclosed for forming integrated circuits configured with co-integrated group III-N transistors and group IV transistors. The diverse transistors can be formed in a neighboring fashion or otherwise adjacent to one another on a common substrate. The substrate is a semiconductor-on-insulator configuration. According to an embodiment, structural features of neighboring III-N transistors are used to define structural features of an intervening group IV transistor. So, for example, features of the III-N transistor structures are initially used as a mask to pattern the intervening group IV transistor structure and subsequently are later used as part of the III-N transistor structures, in some cases. In other cases, the III-N transistor structures are sacrificial in nature, in that they are removed after formation of the IV transistor feature. The self-aligned co-location techniques can be used to significantly reduce integration processing needed to form mixed transistor technology (e.g., silicon-containing transistors between GaN transistors).

Description

Co-integration technology of GaN and self-aligned thin-body group IV transistors

This disclosure relates to the co-integration technology of gallium nitride and self-aligned thin-body group IV transistors.

BACKGROUND OF THE INVENTION In the field of wireless communication and power management, various components can be implemented using semiconductor devices such as transistors. For example, in radio frequency (RF) communications, the RF front-end may include multiple transistor-based components, such as switches and power amplifiers. The RF front-end is a general term for the circuit between the antenna and the digital baseband system. Due in part to its large band gap and high mobility, gallium nitride (GaN) and other Group III-N semiconductor materials are suitable for integrated circuits for applications such as high frequency and high power. In contrast, silicon and other Group IV semiconductor materials are suitable for integrated circuits for applications such as low power.

In one aspect of the present disclosure, an integrated circuit is specifically proposed, which includes: a semiconductor-on-insulator substrate, the substrate including an embedded insulator layer sandwiched between an upper portion of a group IV material and a lower semiconductor layer; And a first transistor between two adjacent second transistors, wherein the first transistor has a channel region included in the upper semiconductor layer, and the second transistors include a group III -N semiconductor structure, the semiconductor structure being one of the following: on the upper semiconductor layer, or through the upper semiconductor layer and the embedded insulator layer and on the lower semiconductor layer.

The detailed description of the preferred embodiment discloses a technique for forming an integrated circuit using a co-integrated group III-V transistor and a group IV transistor. Different transistors can be formed adjacent to each other on a common substrate or in other ways adjacent to each other. The substrate is a semiconductor-on-insulator configuration (for example, silicon-on-insulator). According to one embodiment, the structural features of adjacent III-V transistors are used during the manufacturing process to define the structural features of the intervening group IV transistors. Therefore, in some embodiments, the features of the III-V transistor structure are initially used as a mask for patterning the intervening group IV transistor structure, and then later used as part of the III-V transistor structure. In other embodiments, the III-V transistor structure originally used as a mask for patterning the intervening group IV transistor structure is erosive in nature because it forms a certain characteristic after the formation of the group IV transistor structure. Time to be removed. It should be understood that the co-located self-alignment technology can be used to significantly reduce the integration processing required to form a hybrid transistor technology on a common substrate. General overview

Currently, GaN PMOS has low efficiency. Therefore, silicon PMOS is a more suitable choice for CMOS operation in combination with GaN NMOS. However, due to the different properties of GaN and silicon, the co-integration of devices based on III-N materials (such as GaN NMOS transistors) and silicon substrates is a significant problem. For example, GaN has a large lattice mismatch with silicon. Specifically, the lattice mismatch between the GaN material along the <111> crystal orientation and the silicon wafer is about 17%. This larger lattice mismatch usually results in a higher defect density in III-N materials grown on silicon. In addition, there is also a large thermal expansion coefficient mismatch. For example, the thermal expansion coefficient mismatch between GaN and silicon is about 116%, and this usually causes surface cracks on III-N materials grown on silicon. These defects significantly reduce the mobility of carriers (for example, electrons, holes, or both) in III-N materials and can also lead to poor yield and reliability issues. For this purpose, the prior art does not provide an effective way to co-integrate Group III-N transistors and Group IV transistors in CMOS circuits. In some cases, co-integration is handled by using two different substrates and a forming process performed independently, and then a subsequent bonding process connects the separately formed substrates. Therefore, for applications such as RF front-ends, voltage regulator circuits, and other applications that require system integration of different materials, there is a need for an integration solution that enables Group III-N and Group IV components to be co-integrated on a common substrate.

A technique for forming an integrated circuit that uses a co-integrated group III-V transistor and a group IV transistor to be assembled is disclosed. Different transistors can be formed adjacent to each other on a common substrate or in other ways adjacent to each other. According to some embodiments, the substrate is a semiconductor-on-insulator configuration. The substrate can be, for example, a relatively thin silicon layer on a buried oxide, which in turn is provided on a silicon processing wafer or other suitable silicon platform. The top semiconductor layer on the insulator or the underlying semiconductor layer (for example, a process wafer) can be used to form any of the III-V and IV transistors. Therefore, for example, two transistor types can be formed using the top semiconductor layer, or a III-V transistor can be formed using a bottom semiconductor layer and an IV transistor can be formed using a top semiconductor layer. An exemplary integrated circuit configured according to an embodiment has a Group III-N transistor configured for high power and/or high frequency (eg, RF amplifier, RF switch, RF filter) and for relatively Low-power applications (e.g., memory devices, logic) are used to assemble Group IV transistors, but it should be understood that many applications can benefit from these technologies. The group III-N transistor may be, for example, an n-type metal oxide semiconductor (NMOS) and the group IV transistor may be a p-type metal oxide semiconductor (PMOS), thereby providing a complementary metal oxide semiconductor (CMOS) integrated circuit .

According to one embodiment, the structural features of adjacent III-N (or III-V) transistors are used during the manufacturing process to define the structural features of the intervening group IV transistors. In one such exemplary case, GaN lateral epitaxial growth technology is used to provide GaN islands, and GaN transistor channels can be formed in the islands. These islands have a well-controlled size, depending on the growth process used and other factors such as the orientation of the underlying crystal surface on which GaN is grown. In any case, the interval between adjacent GaN islands can be tightly controlled (for example, in the range of 100 nm or less, or even up to 10 nm or less). Therefore, two adjacent GaN islands can be spaced apart from each other as needed to define, for example, the gate length of the Group IV transistor to be formed between them. Then, the islands spaced in this way are actually used as masks for etching the gate trenches of the group IV transistors. Note that the trenches are self-aligned to adjacent GaN islands without any further masking or alignment process. Therefore, in some embodiments, the GaN island is initially used as a mask for patterning the intervening group IV transistor structure, and then later used as part of the III-N transistor structure. In other embodiments, the GaN islands are erosive in nature because they are removed some time after the formation of the group IV transistor features. Many other exemplary embodiments are obvious.

As further understood in view of the present disclosure, the self-aligned co-location technology as provided herein can be used to significantly reduce the integration processing required to form a hybrid transistor technology on a common substrate. Furthermore, in some embodiments, the IV transistor structure, especially the gate length, can become extremely small (for example, 10 nm or less), so that it is difficult to use current processes and technologies to be consistent on a given substrate. To produce. In contrast, the island-forming GaN growth system is highly predictable and controllable. Therefore, the patterning steps are reduced, and the need for masking and additional alignment and planarization steps is also reduced, thereby greatly simplifying the overall process, reducing cost and processing time.

As used herein, Group IV semiconductor materials include, for example, silicon, germanium, carbon, tin, lead and alloys thereof such as silicon germanium (SiGe), silicon carbide (SiC), and germanium-tin (Ge-Sn), to name a few . In addition, the III-N semiconductor material (or III-N material or III-N for short) includes a compound of one or more III elements (for example, aluminum, gallium, indium, boron, and thallium) and nitrogen. Therefore, III-N materials as used herein include, but are not limited to, gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN) , Indium Gallium Nitride (InGaN) and Aluminum Indium Gallium Nitride (AlInGaN), just to cite a few examples of III-N materials. In a more inclusive manner, note that the III-V group material as used herein includes at least one group III element (e.g., aluminum, gallium, indium, boron, thallium) and at least one group V element (e.g., nitrogen, Phosphorus, arsenic, antimony, bismuth), such as gallium nitride (GaN), gallium arsenide (GaAs), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs), to name a few. Many Group IV and III-V material systems can be used in various embodiments of this disclosure.

The use of the techniques and structures provided herein can be detected in the cross-section of an integrated circuit using tools such as scanning electron microscopy (SEM) or transmission electron microscopy (TEM), which can show the device Various layers and structures. Other methods, such as composition mapping, x-ray crystallography or diffraction (XRD), secondary ion mass spectrometry (SIMS), time-of-flight SIMS (ToF-SIMS), atom probe imaging, local electrode atom probe (LEAP) technology , 3D tomography, high-resolution physical or chemical analysis, just to name some suitable example analysis tools. In some embodiments, for example, SEM can indicate adjacent group IV structures and III-V structures (such as silicon PMOS and GaN NMOS) in a cross section, where each group IV structure has two adjacent group III-V structures. The group V structure, such that the group IV structure and the III-V structure alternate, and further, each group IV structure has a thin metal gate including adjacent gate spacers, wherein the metal gates and the spacers are located On the gate dielectric layer. The gate length can be, for example, 50 nm or less, or 40 nm or less, or 30 nm or less, or 20 nm or less, or 15 nm or less, or 10 nm or less, or 8.5 nm Or smaller, or 7 nm or smaller. In view of this disclosure, many configurations and changes are obvious and easy to know. Structure and method

FIG. 1 is a cross-sectional view of an integrated circuit structure assembled using a co-integrated group III-V NMOS transistor and a group IV PMOS transistor on a common substrate according to an embodiment of the present disclosure. Note that this structure is shown in a cross-sectional view taken along the direction perpendicular to the gate, as is the corresponding structure shown in Figures 2-10. As shown, the integrated circuit 100 includes a semiconductor-on-insulator (SOI) substrate having a plurality of group IV transistors (101A, 101B) and a plurality of III-N transistors (102A, 102B) formed thereon. As can be further discovered, transistor 101A is between transistors 102A and 102B, and transistor 101B is between transistors 102B and 102C. Although four transistors are shown, it should be understood that many transistors can be used in many alternating patterns. In addition, it should be noted that dummy transistor bodies can also be used (for example, the characteristics of one or more dummy group III-V transistors can be used to form intervening group IV transistors). For this purpose, the techniques provided herein can be implemented using functional and dummy (non-functional) transistor configurations.

In the specific exemplary embodiment shown in FIG. 1, the transistor 101A is a silicon (Si) transistor (for example, PMOS), which is positioned between the GaN transistors 102A and 102B (for example, NMOS). Similarly, the transistor 101B is a Si transistor (for example, PMOS), which is positioned between the GaN transistors 102B and 102C (for example, NMOS). As further shown, GaN transistor 102B is also between Si transistors 101A and 101B. Although in some embodiments, GaN transistors alternate with Si transistors, other configurations can also be implemented, as understood in view of this disclosure. For example, in other embodiments, the integrated circuit structure 100 may include multiple groups of first transistors between adjacent second transistors, such as InGaN transistors alternating with SiGe transistors, or with Ge AlGaN transistors with alternating transistors, to name just a few other exemplary configurations.

The substrate can have many semiconductor-on-insulator (SOI) configurations, and can be implemented, for example, using a prefabricated SOI substrate or a monolithic substrate with insulator and semiconductor layers formed thereon. In this exemplary case, the SOI substrate includes a thin layer of Si on an insulator (for example, silicon dioxide or other silicon compatible insulator), which in turn is provided on a Si-processed substrate (for example, a monolithic silicon substrate). In other embodiments, the substrates can be assembled in different ways. For example, an SOI substrate may have a thin SiGe semiconductor layer on a monolithic silicon wafer or a silicon dioxide layer on the substrate, where the Ge concentration of the SiGe layer may vary from about, for example, 5% to 40%. In other such embodiments with a higher concentration of Ge (40% to 90%), the substrate may include a graded buffer layer between the insulator layer and the top SiGe layer, which buffer layer changes the Ge concentration from compatible with the insulator layer The level gradually increases to the target Ge level. In other cases, note that the target level of Ge can be 100% in order to provide an SOI substrate configuration of Ge/graded Ge-Si buffer/Si-compatible insulator/Si substrate. In other cases, the SOI substrate configuration can be a Ge/Ge-compatible insulator/Ge substrate. In a more general sense, the SOI substrate can include any combination of Group IV materials such as Si, Ge, SiGe, or SiC. As further understood in view of the present disclosure, the substrate can have a specific surface crystal orientation, which can be described by the Miller index. For example, the substrate may have a crystal orientation of <100>, <110> or <111>, depending on the specific material used.

Generally, in the specific embodiment shown in FIG. 1, the group III-N transistors 102A-C each include a source S, a drain D, and a gate G, and two of the GaN channel layer and the induced channel. The polarization layer P of the dimensional electron gas (2DEG). It should also be noted that in this exemplary case, the GaN channel layer is grown directly on the underlying silicon substrate. Each of the source S, the drain D, and the gate G may include a multilayer structure including source/drain region materials, work function adjusting materials, resistance reducing materials, and metal contact materials. In addition, a gate spacer is provided to separate the gate G from the source S and drain D. The group IV transistors 101A-B also include a source S, a drain D, and a gate G, respectively. Provide source and drain contacts C. The contacts may include a multilayer structure including work function adjusting materials, resistance reducing materials, and metal contact materials. A silicon (Si) channel area is provided between the source S and the drain D and under the gate G. A gate dielectric GD is provided between the underlying Si channel and the gate G. Also note that in this exemplary embodiment, a gate dielectric GD is provided under the gate G and the corresponding adjacent gate spacer. Therefore, in some embodiments, an integrated circuit including a first transistor such as a group IV transistor and a second transistor such as a III-N transistor (or other III-V transistor) is disclosed, and the first A transistor includes a gate and adjacent gate spacers, each of which is positioned above the gate dielectric layer, and in some embodiments is positioned on the gate dielectric layer.

As further understood, the gate transistor 101 can be centrally positioned between adjacent transistors 102 in a self-aligned manner, as further shown in FIG. 1. In some such embodiments, the distance between two adjacent group IV transistors 102 can be set to the nominal distance of X (for example, in the range of 50 nm to 500 nm). Given the controlled growth rate of the III-N material used during the formation of the transistor 102, as explained further in turn, the distance Y from each of the adjacent transistors 102 can also be controlled. Therefore, the III-N material can be grown by a specific distance Y, and then used as a mask to form the characteristics of the transistor 101. It is further concluded that the distance W corresponding to the gate length of the transistor 101 can also be controlled. Therefore, for example, the gate center of the transistor 101 is at half the distance X from any adjacent transistor 102, and Y is equal to half of the distance X minus 0.5W. Given the self-alignment nature of the manufacturing process, these spatial relationships can be uniformly repeated throughout the substrate, so that the gate center of the transistor 101 is approximately half of the distance X from any adjacent transistor 102 Place. Note that the center of the gate may not be accurately positioned at half the distance X from the adjacent transistor 102, but may actually be within a reasonable tolerance of this position. For example, the gate center can be at 10% of this position, or 7.5% of this position, or 5% of this position, or 3% of this position, or 2% of this position, or 1% of this position, Or within 0.5% of this position. In some specific exemplary embodiments, the gate center is positioned at half of the distance X from the adjacent transistor 102, +/- 3 nm, or +/- 2 nm, or +/- 1 nm. Also note that the tolerance can be asymmetric, such as +2/-1nm. Without the self-aligned co-location technology provided in this article, it is difficult to achieve uniformity of the gate position in the case of a hybrid electro-crystalline bulk circuit on a given wafer and on a common substrate.

Fig. 1'shows another exemplary embodiment similar to the embodiment shown in Fig. 1 with one change. Specifically, the integrated circuit 100' includes all the features of the integrated circuit 100, but further includes a nucleation layer between the substrate and the GaN channel layer. The nucleation layer can be used to assist in starting the growth of the GaN transistor 102. In one such embodiment, for example, the nucleation layer may include, for example, an aluminum nitride (AlN) layer, or other suitable starting materials. In other embodiments, in addition to nucleation, this layer can be further configured to have buffering properties.

2 to 9 illustrate methods of forming exemplary integrated circuits according to various embodiments of the present invention, and various resulting structures thereof. As can be found, the substrate 200 of the integrated circuit has a semiconductor-on-insulator (SOI) configuration, which generally includes a processing substrate or wafer 205, an insulator layer 210, and a semiconductor layer 215. In a specific exemplary embodiment, the substrate 200 includes a monolithic silicon substrate 205, a silicon dioxide layer 210 (sometimes referred to as a buried oxide layer or a BOX layer), and a thin silicon layer 215. SOI 200 can be prefabricated or prepared. For example, a monolithic silicon wafer can be processed using an oxygen ion implantation process to form an implanted oxygen layer, and then annealed to form a buried oxide layer that integrates a thin top silicon layer with a thicker bottom The silicon layer is separated. For this process, the thin silicon layer 215 and the silicon substrate 205 have the same crystal orientation. Therefore, in a specific embodiment, the silicon substrate 205 and the thin silicon layer 215 have the same crystal orientation, for example, a <100> orientation. In another exemplary embodiment, the monolithic silicon wafer is surface-oxidized and processed through the oxidized surface by a hydrogen ion implantation process to form a hydrogen-embedded layer. A processing substrate such as a second silicon substrate can be connected to an oxidized surface, and the composite structure is heated to cause peeling along the hydrogen layer, thereby leaving a thin silicon layer 215 and an oxide layer 210 connected to the processing silicon substrate 205. In this process, the silicon substrate (process) 205 can have a different crystal orientation than the top thin silicon layer 215, so that it can be used in different ways in various component construction processes, such as the component construction process described herein. For example, in a specific embodiment, the silicon substrate 205 has one crystal orientation, such as a <111> orientation, and the thin silicon layer 215 has a second different crystal orientation, such as a <100> orientation. As understood, the insulating layer 210 may be an oxide or nitride layer disposed between the thin silicon layer 215 and the silicon substrate 205. In other embodiments, each of the layers 210, 215, 220, and 230 may be provided using a capping layer deposition process to form a multilayer stack. In addition, note that the semiconductor layer 215 is not necessarily limited to silicon, but may also be other Group IV semiconductors, such as Ge, SiGe, and SiC. In any of these embodiments, the insulator layer 210 has a thickness in the range of, for example, 10 nm to 2 micrometers (eg, 200 nm to 1 micrometer), or any other suitable thickness. As understood in view of the present disclosure, the thickness of the insulator layer 210 can be used to electrically separate the transistor formed in the semiconductor layer 215 from the underlying substrate 205. This isolation is useful, for example, in reducing leakage of sub-channels (or sub-wings). The thickness of the semiconductor layer 215 can also vary between various embodiments, but in some cases is in the range of 5 nm to 500 nm (for example, 10 nm to 200 nm). The thickness of the semiconductor layer 215 can be set based on the configuration of the transistor device formed therein, especially based on the required channel layer thickness and possible source/drain region thickness.

As further shown in FIG. 2, the dielectric layer 220 is also provided on the semiconductor layer 215 of the SOI 200, and a shallow trench isolation (STI) layer 230 is provided on the dielectric layer 220. In some embodiments, one or both of the layers 220 and 230 may include multiple material layers or stacked configurations. In addition, one or more intervening layers may also be provided in some embodiments, as understood in view of the present disclosure. The dielectric layer 220 may have any suitable dielectric constant, but in some embodiments is a high-k dielectric material, such as a high-k gate dielectric suitable for group IV transistor configurations. Dielectric materials. Generally, high-k dielectric materials include materials having a dielectric constant (a k-value greater than 3.9) greater than that of silicon dioxide. Exemplary high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, titanium oxide, barium strontium titanium, barium titanium oxide, Strontium titanium, yttrium oxide, aluminum oxide, silicon oxide, lead scandium tantalum oxide, and lead zinc niobate, to name a few. In some embodiments, an annealing process may be performed on the dielectric layer 220 to improve its quality. The thickness of the dielectric layer 220 can vary between various embodiments, but in some cases is in the range of 1 nm to 20 nm (for example, 5 nm to 10 nm), depending on the end use or target application.

The STI layer 230 may include any suitable insulator or isolation material, such as oxide (for example, silicon dioxide or aluminum oxide) and/or nitride (for example, silicon nitride or silicon oxynitride), to name a few. In some embodiments, the STI layer 230 may include multiple material layers or stacked configurations. The STI layer 230 may have any suitable dielectric constant, but in some embodiments is a low-k dielectric material, such as a low-k dielectric material suitable for providing electrical isolation between adjacent transistors. Generally, low-k dielectric materials include materials having a dielectric constant (k less than 3.9) less than that of silicon dioxide. Exemplary low-k dielectric materials include, for example, porous silicon dioxide, porous silicon nitride, carbon or fluorine doped silicon dioxide, porous carbon doped silicon dioxide, spin-on polymer dielectrics, to name a few example. The thickness of the STI layer 230 can vary between various embodiments, but in some cases is in the range of 50 nm to 2 micrometers (eg, 200 nm to 1 micrometer), depending on the end use or target application and as understood.

As further understood in view of the present disclosure, each of these layers 205, 210, 215, 220, and 230 can be used to form various features and components of the integrated circuit 100, as described in turn. Also note that in some embodiments, each of these layers 210, 215, 220, and 230 may be sequentially provided on the substrate 205 in a cover layer manner using standard processing, such as chemical vapor deposition (CVD ), atomic layer deposition (ALD), physical vapor deposition (PVD), oxidation and implantation processes, to name a few. After forming a multilayer structure in Figure 2, the method can continue to form various devices. Note that in some embodiments, this structure may be completed in advance or otherwise obtained for subsequent use with respect to the methods shown in FIGS. 3 to 10.

FIG. 3 shows the resulting structure after forming trenches for the growth of group III-V transistors according to an embodiment. As can be found in this exemplary case, parts of the STI layer 230, the dielectric layer 220, the semiconductor layer 215, and the insulator layer 210 are removed, thereby forming a trench 335 on the underlying substrate 205 and exposing the underlying substrate 205. In one such case, the substrate 205 may have a crystal orientation 111 relative to the trench direction. This 111 orientation is completely suitable for the growth of III-N materials such as GaN. In other embodiments, the trenches 335 can terminate on different layers of the structure, such as the semiconductor layer 215, so as to also provide a specific orientation suitable for growing transistor materials. Although a variety of etching schemes can be used to form trenches, one embodiment uses a combination of wet and/or dry etching processes. For example, if the STI layer 230 is silicon nitride and the dielectric layer 220 is silicon dioxide, a wet etching process including hot phosphoric acid can be used to etch through the STI layer 230 to expose the underlying dielectric layer 220. Then, after this wet etching, dilute hydrogen fluorine (HF) acid or ternary mixed gas acid immersion may be performed to pattern-etch the dielectric layer 220, thereby exposing the underlying semiconductor layer 215. If the trench 335 is terminated on the lower substrate 205, further etching can be used to remove the semiconductor layer 215 and the insulator layer 210. The etchant for this layer can be selected, for example, based on its selectivity for crystal orientation, so as to provide anisotropic etching. For example, if the semiconductor layer 215 is silicon and the trenches are oriented in the 100 crystal direction, an etchant such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) can be used much faster than in the 111 direction. This layer 215 is etched in the 100 crystal direction. Other such selective or so-called anisotropic etching schemes may also be used, depending on factors such as the composition of the layer 215 and the orientation of the trench 335 relative to the crystal orientation. Directional dry etching can also be used. The size of the trenches 335 can vary between various embodiments, but in some cases, each trench 335 has a cross-sectional opening in the range of 50 nm to about 50 µm.

After the trench 335 is formed, the method continues to fill the trench with III-V material, resulting in the formation of the III-V group transistor of the circuit. Exemplary embodiments are shown in Figures 4A, 4B, and 4C. As can be found, the structure of this exemplary embodiment generally includes a III-V semiconductor body 440, a III-V polarization layer 445 that induces 2DEG in the channel of the semiconductor body 440, and the growth of a III-V semiconductor material 450 (450A , 450B or 450C, in the corresponding embodiment shown in Figures 4A-C). Other embodiments may include other layers because there are many configurations of group III-V transistors, and any of these configurations can be implemented according to the embodiments of the present disclosure, as understood. For example, and as previously explained with reference to FIG. 1', the first layer formed in the trench 335 may optionally be a nucleation layer, for example, having a value in the range of about 10 nm to 400 nm (for example, ~50 nm) Thickness of AlN layer. In an exemplary embodiment, the III-V semiconductor body 440 is a III-N material such as GaN or InGaN. These III-N materials are particularly suitable for high-power applications, partly due to their relatively wide band gap, relatively High critical breakdown electric field and higher electron saturation. The polarization layer 445 may be, for example, AlN, AlInN, AlGaN, or AlInGaN. The grown III-V semiconductor material 445 may be GaN, for example, or other III-V materials that can be grown in a predictable or otherwise consistent manner, as understood in view of this disclosure. As further understood in view of the present disclosure, given this predictable growth mode, the distance W between the growth regions of adjacent group III-V transistors can be reliably determined. Also note that the grown III-V semiconductor materials can have different shapes.

The formation of III-N features 440, 445, and 450 (and any other layers, such as nucleation layers) can be performed using many deposition techniques, including, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD). As discussed above, GaN has a larger lattice mismatch with Si and a larger thermal expansion coefficient mismatch, which generally results in a higher defect density in GaN materials grown on Si. Therefore, in some embodiments, high-quality GaN on Si is grown using lateral epitaxial growth (LEO) conditions. This LEO process may include, for example, growing a GaN body 440 on the Si substrate 205 within the patterned trench 335, and then allowing the material to grow over the trench 335, thereby forming lateral growth regions 450A, 450B, or 450C. In this way, when the material is formed on the STI layer 230, the defects that may exist in the grown material can be bent or otherwise reduced, thereby leaving the rest of the GaN material 440 suitable for use in the transistor channel.

In an exemplary process flow, the growth of the III-V semiconductor body 440 such as GaN may be interrupted or modified to form the polarization layer 445. For example, in some such exemplary embodiments, the GaN body 440 is grown just below the surface of the STI layer 230, and then the deposition process parameters are modified to transition from growing GaN to growing the polarization layer 445 material. After the relatively thin polarization layer 445 is formed, the deposition process parameters can be modified again to change from growing the polarization layer 445 to growing GaN, thereby allowing continuous lateral epitaxial growth of GaN 450. The polarization layer 445 may include any suitable material, such as one or more III-V materials, and more specifically in some embodiments, for example, one or more III-N materials. In some embodiments with a GaN body 440, the polarization layer 445 includes aluminum such that the layer includes at least one of AlN, AlGaN, InAlN, and InAlGaN. The polarization layer 445 effectively increases the carrier mobility in the transistor channel region in the GaN body 440 so as to induce 2DEG. In these cases, the polarization layer 445 generally includes a material having a higher band gap than the material of the III-N body 440 in order to form a 2DEG. For example, in some embodiments, the semiconductor body 440 is GaN and the polarization layer 445 is AlN and/or AlGaN. In some embodiments, the polarization layer 445 may have a multilayer structure including a variety of III-V materials, where one layer of the multilayer structure may be present to further increase the carrier mobility in the transistor channel region and/or improve the polarity. Compatibility between the chemical layer 445 and the overlying layer (for example, the density of the interface traps). In some embodiments, the polarization layer 445 may or may not include grading (eg, increasing and/or decreasing) the content of one or more materials in at least a portion of the layer. Note that the thickness of the polarization layer 445 may also vary between embodiments, and may be, for example, in the range of 1 nm to 20 nm (for example, 5 nm to 10 nm).

The conditions for growing the III-V semiconductor material 450 can be used to change the properties of the resulting epitaxial growth structure. In some embodiments, the facet or cover of the III-V growth area is controlled by, for example, the V/III ratio used to deposit the material and the growth temperature and pressure. Generally, increasing the V/III ratio facilitates the formation of rectangular end faces, such as the cover 450B shown in FIG. 4B and the cover 450C shown in FIG. 4C, as well as increasing the deposition temperature and reducing the pressure. In general, a lower V/III ratio, lower temperature and higher pressure facilitate the formation of triangular end faces, such as the cover 450A shown in FIG. 4A. In addition, the orientation of the trench 335 used for the growth of the III-V body 440 can result in different end faces of the resulting growth area 450A-C. In a specific embodiment, for example, for the <100> Si substrate 205 and the GaN 450, the orientation of the trench 335 along the <110> direction facilitates the triangular end face (FIG. 4A). In another exemplary embodiment, for the <100> Si substrate 205 and GaN 450, the orientation of the trench 335 along the <100> direction facilitates the rectangular end face (FIG. 4B or 4C). In another exemplary embodiment, for the <111> Si substrate 205 and GaN 450, the orientation of the trench 335 along the <112> direction is favorable for the triangular end face (FIG. 4A).

As understood in view of this disclosure, lateral epitaxial growth technology can be used to form III-V transistor characteristics, which can be used to accurately determine various characteristics of transistors positioned between their III-V transistors, such as gates Length, Lg. For example, as shown in FIGS. 4A-C, the formation of lateral growth regions 450A, 450B, and 450C on the STI layer 230 results in the formation of a gap 460 having a width W between adjacent covers. The lateral growth can be continued as needed, increasing the size of the cover 450, thereby correspondingly reducing the width of the gap 460 therebetween, until the specified or target gap width is reached. The growth can then be stopped, such as by ending the supply of reagents required for continued growth, or otherwise adjusting the process to stop the growth, such as by reducing the temperature or increasing the pressure beyond a given growth threshold. In this way, the width of the gap can be controlled in a relatively precise manner, and in some embodiments of the present disclosure, the extremely small gap 460 can be uniformly generated by controlling the processing conditions of the lateral epitaxial growth. For example, the method described herein can be used to achieve a gap having a width of less than about 100 nm, such as less than about 75 nm, or less than about 50 nm, or less than 25 nm, or less than 15 nm, or less than 10 nm (e.g. , 1 nm to 9 nm gap).

The gap 460 can then be used to form the gate of an intervening transistor, such as Si PMOS or other group IV transistors. Therefore, if the gate of a first transistor, such as a Si transistor, is positioned between adjacent second transistors, and in some embodiments is positioned at the center, the gate is substantially between the second transistors. Equidistant. After the gate is formed, the III-V growth region 450 can be removed, and the underlying body 440 and polarization layer 445 can be used to form a III-V transistor, such as a GaN NMOS transistor. Therefore, in fact, the lateral epitaxial growth region 450 serves as a temporary mask during the formation of the gates or other features of the transistors positioned therebetween. The resulting integrated circuit includes the first material system device between two adjacent devices of the second material system, and the second adjacent device actually defines the location and size of at least one feature of the first device.

Further details of the exemplary embodiment are shown in Figures 5-7. As shown in FIG. 5, the adjacent cover 450 is a lateral epitaxial growth region formed on the polarization layer 445 on the III-V semiconductor body 440 and extends on the STI layer 230 to form a gap having a width W. Although cap 450A is shown, the same method can be used for caps 450B and 450C, as understood in light of this disclosure. Therefore, the following reference to the cover or area 450A, 450B or 450C is referred to as the cover or area 450 for short. The exposed portion of the STI layer 230 can be removed by various etching processes to form the gate trench 570, which in this embodiment exposes the cavity in the STI layer 230 of a portion of the dielectric layer 220. Therefore, in some embodiments, etching occurs through the STI layer and stops at the dielectric layer 220. Many etching processes can be used to selectively remove the STI layer 230 without removing the dielectric layer 220 or the area 450, including various selective wet or dry isotropic etching (providing anisotropic or directional etching through the STI layer) . During etching, for a given etching chemistry, the III-V cap 450 maintains or otherwise has an etch rate that is substantially less than that of the STI 230 material. Therefore, the lateral epitaxial growth region basically serves as a mask for forming gate features. For example, according to one embodiment, if the STI layer 230 is silicon nitride, the growth region 450 is GaN, and the dielectric layer 220 is silicon dioxide or a high-k dielectric such as hafnium oxide, it includes hot phosphoric acid. The wet etching process can be used to etch the STI layer 230, expose the underlying dielectric layer 220, and relatively minimally remove the GaN region 450 and the dielectric layer 220.

As further shown in FIG. 5, pay attention to the spatial relationship of the trench 570 with respect to the adjacent III-V semiconductor body 440. Specifically, the inner-facing edges of each adjacent III-V semiconductor body 440 define a distance X between the edges. Each growth area 450 extends a distance Y from the edge of its corresponding body 440. Assuming the predictable growth mode of the adjacent growth area 450, the distance Y is also predictable, and the same as the width W. It is further concluded that the center of the trench 570 is at a distance of X/2 from any edge of the adjacent growth area 450. As previously explained, for the actual center of the trench 570 relative to the adjacent growth area 450, a reasonable tolerance may be allowed, depending on factors such as the value of X (the larger the value X, the larger the allowable tolerance). For example, in some cases, in either direction, the center of trench 570 (as seen in the cross section) can deviate from the position of X/2 by as much as 10% of X/2, while other embodiments have 5% or less , Or a tighter tolerance of 2.5% or less. As understood in view of the present disclosure, it is difficult to use standard processes to achieve this consistent trench layout, especially for relatively narrow trenches 570 (for example, <20 nm).

As shown in the exemplary embodiment shown in FIG. 6, the trench 570 formed in the STI layer 230 may be filled with metal to form a gate 680 between adjacent caps 450. In some embodiments, any suitable gate metal deposition process (eg, CVD, PVD, MBE) can be used, and then various etching, polishing, planarization, and cleaning processes can be performed. The gate electrode 680 may be, for example, polysilicon, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), ruthenium (Ru), nickel (Ni), palladium (Pd) ), platinum (Pt) and titanium nitride (TiN), just to name a few. In this exemplary embodiment, note that the cap 450 defines the gate length, Lg, of the gate 680 formed in the STI layer 230. Therefore, according to some embodiments, as described herein, the extent to which the cover 450 extends on the STI layer 230 can be controlled as needed to provide a gap having a width required for the target Lg value of the gate of the intervening transistor.

According to an embodiment, as shown in FIG. 7, once the trench-based features (transistor gates, in the exemplary embodiment shown) are formed, the process can continue to remove the growth area 450. The growth area 450 can be removed using many suitable processes, such as planarization followed by polishing, or selective etching of the material of the area 450. It can also include various intervention processes. In other embodiments, note that the growth area 450 may not be removed, or may be only partially removed or otherwise further shaped and customized for subsequent use in a III-V device.

According to some embodiments, after the growth area 450 is removed, various other features and/or layers may be provided. For example, as shown in FIG. 8A, the directional etching of the STI layer 230 and the dielectric layer 220 can be used to form or otherwise shape the gate spacer 891 beside the gate 680 and in the polarization layer 445 and III-V body The remaining STI material 892 next to 440. Note that 891 and 892 can be the same material as STI 230. Many etching processes can be used, such as _{dry etching in CF 4} , CF ₄ /O ₂ /Ar, Cl ₂ /O ₂ or HBr/CF ₃ , which is especially suitable for highly directional etching removal of STI layer, so as to In some embodiments, parallel or nearly parallel sidewalls and gate spacers are provided. In addition, in some embodiments, etching the polarization layer 445 and the GaN body 440 (or other suitable III-V body 440) is avoided. The mask can be used to promote the selectivity of the spacer etching process as required.

The depth of the spacer etch can vary from embodiment to embodiment, depending on the source/drain configuration. In the exemplary case shown in FIG. 8A, the etching stops at the semiconductor layer 215. In this case, the method may further include ion implantation to dope the layer 215 to form source and drain regions on either side of the gate 680. For example, in one such embodiment where layer 215 is silicon, the exposed portion of layer 215 can be p-doped (eg, boron, gallium, aluminum) by implantation. In the exemplary case shown in FIG. 8B, the etch stopper continues to penetrate the semiconductor layer 215 (for example, using standard anisotropic or directional etching) and terminates at the underlying insulator layer 210. In these cases, the method may further include epitaxial regrowth of the source and drain regions. For example, epitaxial silicon or SiGe or germanium, or some other alternative source/drain materials can be grown in the source-drain region. In these embodiments, note that alternative S/D materials can be grown, for example, from the sidewalls of the exposed semiconductor layer 215 (eg, according to some embodiments, silicon or SiGe can be grown from the Si layer 215, or germanium or SiGe can be grown from the Ge layer 215 Growth). The doping of the epitaxial material can be done in situ (during deposition) or later by implantation. In some embodiments, the source/drain regions may include additional layers, such as a graded buffer layer and/ Or contact resistance reduction layer and/or work function adjustment layer.

Therefore, according to some embodiments, the STI layer 230 may be used to provide the gate spacer 891 and the sidewall spacer 892, and the dielectric layer 220 may be used to provide the gate dielectric layer 220. Note how the gate dielectric 220 is positioned under the gate spacer 891. In a typical Group IV transistor configuration, the gate dielectric material is not under the gate spacers, but actually only between the gate spacers. Therefore, the illustrative indicator of the structure formed according to some embodiments of the present disclosure is the gate spacer on the gate dielectric, which can be further aligned with the gate located centrally between two adjacent transistors. Combinations, which can be further combined with relatively narrow gates.

Continuing with the method, according to one embodiment, once the gate spacers 891 are formed together with the previously explained source/drain trenches reaching the required depth, the source/drain regions and contacts can be formed. In the exemplary embodiment shown in FIG. 9, the source/drain regions 995 (further denoted as S and D) are provided on or above the insulator layer 210. The semiconductor layer 215 undergoes implant doping (as explained with respect to FIG. 8A), or epitaxial growth of alternative source/drain materials on or above the insulator layer 210 (as explained with respect to FIG. 8B). Other embodiments may use other source/drain region 995 formation techniques, as understood. As further understood, the source/drain region 995 may include many materials (eg, silicon, germanium, SiGe) and doping schemes (eg, undoped, n-type doped, or p-type doped). For example, in an embodiment where the structure includes a silicon layer 215 on the oxide layer 210 and the transistor device is assembled as a PMOS device, the source/drain region 995 may include, for example, boron-doped Si or SiGe. In another exemplary embodiment in which the transistor device is assembled as an NMOS device, the source/drain region 995 may include, for example, phosphorus-doped Si. The doping concentration can be set as required (for example, the doping amount per cubic centimeter is about 2E20). As previously explained, the S/D region 995 may have a multilayer structure including multiple material layers. For example, in some embodiments, before depositing the main S/D material, a passivation material may be deposited to help the quality of the interface between the S/D material and the underlying material. In addition, in some embodiments, a contact improving material may be formed on the top of the S/D area to facilitate contact with the S/D contact, for example, as described below. In some embodiments, the S/D region may include grading (for example, increasing and/or decreasing) the content of one or more materials in at least a part of the regions.

As can be further found in FIG. 9, the method continues to provide S/D contacts 996 on the S/D region 995 and may include any suitable material, such as conductive metals or alloys (e.g., aluminum, tungsten, silver, nickel-platinum Or nickel-aluminum). In some embodiments, the S/D contact 996 may include resistance reducing metal and contact plug metal, or only contact plug, depending on the end use or target application. Exemplary contact resistance reducing metals may include silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. The contact plug metal can include, for example, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, but any suitable conductive contact metal or alloy can be used, depending on the end use or target application. In some embodiments, if desired, additional layers may be present in the S/D contact area, such as an adhesion layer (e.g., titanium nitride) and/or a liner or barrier layer (e.g., tantalum nitride). In some embodiments, the metallization of the S/D contact 996 can be performed, for example, using a silicidation or germanium process (e.g., generally, the contact metal is deposited on the S/D region 995 containing silicon or germanium, This is followed by annealing). In view of this disclosure, many S/D configurations are obvious and easy to understand.

As can be found in FIG. 10, according to one embodiment, once the formation of the group IV transistor is completed, the method continues to form the additional features of the group III-V transistor. For example, in the exemplary case shown, source/drain regions 1097 (also denoted as S and D) are provided adjacent to the 2DEG channel induced by the polarization layer 445 in the III-V body 440. In addition, a gate electrode 1099 is provided on the channel. In some embodiments, the S/D region 1097 can be formed using any suitable technique, as is obvious in view of the present disclosure. For example, in some embodiments, the S/D region 1097 can be formed by any combination of optional patterning/masking/lithography/etching and deposition, growth and regrowth of the S/D region 1097 material, Then, for example, a planarization and/or polishing process can be performed. Note that although in FIG. 10, the S/D region 1097 is shown as a continuous part, in some embodiments, the S/D region 1097 may include multiple parts, such as the channel region (which is the top of the III-V layer 440). Part) Adjacent S/D material and S/D contact above the S/D material. However, in some embodiments, the first layer of the interconnect layer above the depicted device layer can be regarded as the S/D contact of the S/D region 1097. Regardless of the configuration, in some embodiments, the S/D material (which is in at least a part of the S/D region 1097) may include any suitable material, such as III-V material, III-N material, and/or any other Appropriate materials are obvious in view of this disclosure. In addition, in some embodiments, the S/D region 1097 material may be doped in an n-type or p-type manner using any suitable doping technique. In an exemplary embodiment, the S/D region 1097 may include indium and nitrogen (for example, InN or InGaN) and may be doped in an n-type manner (for example, using Si, Se, and/or Te, at a rate of about 2E20 per cubic centimeter). Doping amount to doping). In some embodiments, one or both of the S/D regions 1097 may have a multilayer structure including multiple materials. In some embodiments, one or both of the S/D regions 140 may or may not include grading (e.g., increasing And/or decreasing). In addition, in some embodiments, note that the source-gate interval may be different from the drain-gate interval, depending on the required breakdown voltage of the III-V device.

As previously explained, in some embodiments, the S/D area 1097 may include S/D contacts. In some such embodiments, the S/D contact may include any suitable material, such as a conductive metal or alloy (e.g., aluminum, tungsten, silver, nickel-platinum, or nickel-aluminum). In some embodiments, the S/D contact may include resistance reducing metal and contact plug metal, or only contact plug, depending on the end use or target application. Exemplary contact resistance reducing metals include silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys. The contact plug metal can include, for example, aluminum, silver, nickel, platinum, titanium, or tungsten, or alloys thereof, but any suitable conductive contact metal or alloy can be used, depending on the end use or target application. In some embodiments, if desired, additional layers may be present in the S/D contact area 1097, such as an adhesion layer (e.g., titanium nitride) and/or a liner or barrier layer (e.g., tantalum nitride). Note that in some embodiments, the gate stacking process may be performed before forming the S/D region 1097, while in other embodiments, the gate stacking process may be performed after forming the S/D region 1097, for example. The gate stack can be customized as required. Exemplary system

FIG. 11 shows a computing system 1000 implemented with an integrated circuit structure or device as disclosed herein, according to an exemplary embodiment. As can be found, the computing system 1000 accommodates a motherboard 1002. The motherboard 1002 may include multiple components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to the motherboard 1002, or integrated in it in other ways. As understood, the motherboard 1002 can be, for example, any printed circuit board, whether it is a motherboard, a daughter board mounted on the motherboard, or the only board of the system 1000, etc.

Depending on the application of the computing device, the computing device 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, electrical memory (e.g., DRAM), non electrical memory (e.g., ROM), graphics processor, digital signal processor, encryption processor, chipset, antenna, Display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and large capacity Storage devices (such as hard disk drives, compact discs (CD), digital versatile discs (DVD), etc.). Any of the components included in the computing system 1000 may include one or more integrated circuit structures or devices (for example, mixed III-V and IV transistors on a common substrate) assembled according to exemplary embodiments , Which has self-aligning properties). In some embodiments, multiple functions may be integrated into one or more chips (for example, note that the communication chip 1006 may be a part of the processor 1004 or otherwise integrated into the processor 1004).

The communication chip 1006 enables wireless communication for data transfer to and from the computing device 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can communicate data through the use of modulated electromagnetic radiation through non-solid media. The term does not imply that the associated devices do not contain any leads, but in some embodiments the associated devices may not contain any leads. The communication chip 1006 can implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives of the above, and any other wireless protocols designated as 3G, 4G, 5G, and others. The computing device 1000 may include a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1006 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX , LTE, Ev-DO, etc. In some embodiments, the communication chip 1006 may include one or more hybrid transistor structures on a common substrate, as individually described herein.

The processor 1004 of the computing device 1000 includes an integrated circuit die package in the processor 1004. In some embodiments, the integrated circuit die of the processor includes an on-board circuit implemented with one or more integrated circuit structures or devices as individually described herein. The term "processor" can refer to any device or device that processes electronic data, such as from a register and/or memory, to transform the electronic data into other electronic data that can be stored in the register and/or memory. The part of the device.

The communication chip 1006 also includes an integrated circuit die packaged in the communication chip 1006. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices as individually described herein. As understood in view of the present disclosure, note that multi-standard wireless capabilities can be directly integrated into the processor 1004 (for example, the functions of any chip 1006 are integrated into the processor 1004 instead of having an independent communication chip). Also note that the processor 1004 can be a chipset with this wireless capability. In an exemplary embodiment, the processor 1004 and the communication chip 1006 are integrated into a single chip or chipset, such as a system-on-a-chip (as indicated by the dotted lines surrounding their components as a whole). In one such case, using the various hybrid transistor technologies provided herein, the logic circuit of the processor 1004 can be implemented in silicon or SiGe, for example, and the RF circuit of the communication chip 1006 can be implemented in GaN and used for RF and The logic of mixed signal processing can be implemented in GaN NMOS and silicon PMOS. In short, many processors 1004 and/or communication chips 1006 can be used. Similarly, any one chip or chip set can have multiple functions integrated therein.

In various implementation schemes, the computing system 1000 can be a laptop computer, a portable easy-to-net machine, a notebook computer, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer , Server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or process data or use one of the configurations described separately in this article Or any other electronic device with multiple integrated circuit structures or devices. Other exemplary embodiments

The following examples refer to other embodiments, and many arrangements and configurations of these embodiments are obvious and easy to understand.

Example 1 is an integrated circuit, which includes: a semiconductor-on-insulator substrate including an embedded insulator layer disposed between the upper and lower semiconductor layers of group IV materials; and two adjacent second transistors Between a first transistor, wherein the first transistor has a channel region included in the upper semiconductor layer, and each of the second transistors includes a group III-N semiconductor structure, The semiconductor structure is on the upper semiconductor layer, or alternatively, passes through the upper semiconductor layer and the embedded insulator layer and on the lower semiconductor layer.

Example 2 includes the subject of Example 1, wherein the III-N semiconductor structure of each second transistor is in a trench, and the trench has a bottom on the upper semiconductor layer.

Example 3 includes the subject matter of Example 1, wherein the III-N semiconductor structure of each second transistor is in a trench, the trench passes through the upper semiconductor layer and the embedded insulator layer, and has a semiconductor One layer on the bottom.

Example 4 includes the subject matter of Example 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the trench direction, and the crystal orientation of the lower semiconductor layer is the same as the crystal orientation of the upper semiconductor layer .

Example 5 includes the subject matter of Example 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the trench direction, and the crystal orientation of the lower semiconductor layer is different from the crystal orientation of the upper semiconductor layer .

Example 6 includes the subject matter of any of the foregoing examples, wherein the first transistor has a gate that is centrally located between the second transistors so that the second transistors are separated by a distance X, and the center of the gate is at a position between the second transistors, and the position is within half of the distance of X plus or minus 1 nm.

Example 7 includes the subject of Example 6, where the configuration of one of the first transistors between two adjacent second transistors is repeated multiple times, and the corresponding gate position of each configuration is half of the corresponding distance of X Add or subtract within 1 nm. In other examples, this tolerance may be larger (eg, +/- 5 nm) or smaller (+/- 0.5 nm), depending on factors such as the distance between the opposite sides of the second transistors.

Example 8 includes the subject matter of any of the foregoing examples, wherein the first transistor has a gate electrode that is substantially equidistant between the second transistors. Therefore, for example, the center of mass of the gate structure is positioned on an imaginary vertical line that is substantially equidistant between the second transistors. The position of the imaginary vertical line may not be exactly equidistant, but the fact is within its tolerance, such as within X nm of the position, where X is 10% of the total distance between the opposite edges of the second transistor , Where X is 5% of the total distance between the opposite edges of the second transistor, or where X is 2.5% of the total distance between the opposite edges of the second transistor, or where the opposite of X is the second transistor 1% of the total distance between the edges. Also note that the corresponding edge points for measuring the distance between opposite edges are in a common horizontal plane and can be at any position along their opposite edges.

Example 9 includes the subject matter of any of the preceding examples, wherein the lower and upper semiconductor layers are silicon.

Example 10 includes the subject matter of any one of Examples 1 to 8, wherein the upper semiconductor layer is silicon, germanium, or silicon germanium (SiGe), and the lower semiconductor layer is silicon, germanium, or silicon germanium (SiGe).

Example 11 includes the subject matter of Example 10, wherein the upper semiconductor layer is different from the lower semiconductor layer.

Example 12 includes the subject matter of any of the foregoing examples, wherein the first transistor further includes: a gate dielectric on the channel; a gate metal on the gate dielectric; Source and drain regions on either side of the channel; and a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region , Wherein the gate dielectric is between the channel region and the gate spacers.

Example 13 includes the subject of any of the foregoing examples, wherein the first transistor includes a gate metal and adjacent gate spacers on a high-k gate dielectric layer.

Example 14 includes the subject matter of any of the foregoing examples, wherein the first transistor system is a PMOS transistor and the second transistor system is an NMOS transistor.

Example 15 includes the subject matter of any of the preceding examples, wherein the III-N semiconductor structure comprises GaN.

Example 16 includes the subject matter of any of the preceding examples, wherein the III-N semiconductor structure includes a nucleation layer and a channel layer.

Example 17 includes the subject of Example 16, wherein the nucleation layer includes aluminum nitride (AlN) and the channel layer includes GaN.

Example 18 includes the subject matter of any of the preceding examples, wherein the first transistor includes a gate length having a gate length of 20 nm or less.

Example 19 includes the subject matter of any of the foregoing examples, wherein the first transistor includes a gate length having a gate length of 10 nm or less.

Example 20 includes the subject matter of any of the foregoing examples, wherein at least one of the second transistors is included in the III-N semiconductor structure or a polarization layer on the III-N semiconductor structure.

Example 21 includes the subject matter of Example 20, wherein the polarization layer includes aluminum and nitrogen.

Example 22 is a system-on-a-chip (SOC), which includes the integrated circuit of any one of Examples 1-21.

Example 23 is a radio frequency (RF) circuit, which includes the integrated circuit of any one of Examples 1-21.

Example 24 is a mobile computing system, which includes the integrated circuit of any one of Examples 1-21.

Example 25 is an integrated circuit, which includes: a silicon-on-insulator substrate, the substrate including an embedded insulator layer disposed between upper and lower silicon layers; and one between two adjacent second transistors The first transistor. The first transistor includes: a channel region included in the upper silicon layer; a high-k gate dielectric on the channel region; a gate metal on the gate dielectric; Source and drain regions on either side of the channel region; and a gate spacer between the gate and the source region, and a gate between the gate and the drain region Spacers, wherein the gate dielectric is between the channel region and the gate spacers. Each of the second transistors includes: a gallium nitride (GaN) body having a channel region, and the GaN host system is one of the following: on the upper silicon layer, or through the upper silicon layer and the An insulator layer is embedded and on the lower silicon layer; a polarization layer on the GaN body; and source and drain regions on either side of the channel region.

Example 26 includes the subject of Example 25, wherein the III-N semiconductor of each second transistor is in a trench, and the trench has a bottom on the upper silicon layer.

Example 27 includes the subject matter of Example 25, wherein the III-N semiconductor of each second transistor is in a trench, the trench passes through the upper silicon layer and the embedded insulator layer, and has a lower silicon layer On the bottom of one.

Example 28 includes the subject of Example 27, wherein each of the lower and upper silicon layers has a crystal orientation with respect to the trench direction, and the crystal orientation of the lower silicon layer is the same as the crystal orientation of the upper silicon layer .

Example 29 includes the subject of Example 27, wherein each of the lower and upper silicon layers has a crystal orientation with respect to the trench direction, and the crystal orientation of the lower silicon layer is different from the crystal orientation of the upper silicon layer .

Example 30 includes the subject matter of any one of Examples 25 to 29, wherein the first transistor gate is centrally located between the second transistors such that the GaN bodies of the second transistors are separated by a distance X And the center of the gate of the first transistor is at a position between the second transistors, and the position is within half of the distance of X plus or minus 1 nm. Other tolerances should be understood.

Example 31 includes the subject of Example 30, in which the configuration of one of the first transistors between two adjacent second transistors is repeated multiple times, and the gate position of the corresponding first transistor in each configuration is in X. Corresponding to half of the distance plus or minus 1 nm.

Example 32 includes the subject matter of any one of Examples 25 to 31, wherein the gates of the first transistors are substantially equidistant between the GaN bodies of the second transistors.

Example 33 includes the subject matter of any one of Examples 25 to 32, wherein the source and drain regions of the first transistor are silicon, germanium, or silicon germanium (SiGe).

Example 34 includes the subject matter of any one of Examples 25 to 33, wherein the first transistor system is a PMOS transistor and the second transistor system is an NMOS transistor.

Example 35 includes the subject matter of any one of Examples 25 to 34, wherein the first transistor includes a gate length having a gate length of 20 nm or less.

Example 36 includes the subject matter of any one of Examples 25 to 35, wherein the first transistor includes a gate length having a gate length of 10 nm or less.

Example 37 includes the subject matter of any one of Examples 25 to 36, wherein the polarization layer includes aluminum and nitrogen.

Example 38 includes a system-on-chip (SOC) that includes the integrated circuit of any of Examples 25-37.

Example 39 includes a radio frequency (RF) circuit including the integrated circuit of any of Examples 25-37.

Example 40 includes a mobile computing system that includes the integrated circuit of any one of Examples 25 to 37.

Example 41 is a method of forming an integrated circuit, the method comprising: depositing a cover layer of a high-k gate dielectric material on a semiconductor-on-insulator substrate, the substrate including a portion disposed on a group IV material and An embedded insulator layer between the lower semiconductor layers; depositing a covering layer of isolation material on the gate dielectric material; forming trenches by etching through the isolation and gate dielectric materials; The trenches selectively grow a III-N semiconductor to form a lateral epitaxial growth region on the isolation material, thereby defining a gap having a width W between the lateral epitaxial growth regions of adjacent trenches ; And using the lateral epitaxial growth regions as a mask to form a circuit feature between the lateral epitaxial growth regions and in the isolation material.

Example 42 includes the subject matter of Example 41, wherein forming trenches by etching through the isolation and gate dielectric materials further includes etching through the upper semiconductor layer and the embedded insulator layer to expose the lower semiconductor layer.

Example 43 includes the subject matter of Example 41 or 42, wherein selectively growing a Group III-N semiconductor from the trenches includes growing a gallium nitride (GaN) body, followed by a polarization layer, and then more More GaN is used to form the lateral epitaxial growth regions.

Example 44 includes the subject matter of Example 41 or 42, wherein selectively growing a Group III-N semiconductor from the trenches includes growing an aluminum nitride (AlN) nucleation layer, followed by growing a gallium nitride (GaN) nucleation layer. ) The main body, followed by a polarization layer, followed by the growth of more GaN to form the lateral epitaxial growth regions.

Example 45 includes the subject of any one of Examples 41 to 44, wherein using the lateral epitaxial growth regions as a mask to form a circuit feature between the lateral epitaxial growth regions includes forming a transistor gate The method further includes: forming a first transistor including the gate; and forming a second transistor including the III-N semiconductor.

Example 46 includes the subject of Example 45, wherein the first transistor system is a PMOS group IV transistor, the transistor has its channel in the upper semiconductor layer, and the second transistors are each NMOS III-V Group transistors.

Example 47 includes the subject of Example 45, wherein the first transistor system is a PMOS transistor, the transistor has its channel in the upper semiconductor layer, and each of the second transistors is an NMOSGaN transistor, wherein the upper semiconductor The layer is silicon, germanium or silicon germanium (SiGe).

Example 48 includes the subject matter of any one of Examples 41 to 47, wherein the trenches are further etched so that they pass through the upper semiconductor layer and the buried insulator layer, and each trench has an upper semiconductor layer on the lower semiconductor layer. A bottom, and wherein each of the lower and upper semiconductor layers has a crystal orientation relative to the direction of the trench, and the crystal orientation of the lower semiconductor layer is the same as the crystal orientation of the upper semiconductor layer.

Example 49 includes the subject matter of any one of Examples 41 to 47, wherein the trenches are further etched so that they pass through the upper semiconductor layer and the embedded insulator layer, and each trench has an upper semiconductor layer on the lower semiconductor layer. A bottom, and wherein each of the lower and upper semiconductor layers has a crystal orientation relative to the direction of the trench, and the crystal orientation of the lower semiconductor layer is different from the crystal orientation of the upper semiconductor layer.

Example 50 includes the subject matter of any one of Examples 41 to 49, and further includes removing the lateral epitaxial growth regions after forming the circuit feature. However, it should be noted that in other examples, the lateral epitaxial growth regions may remain in the final integrated circuit structure.

The foregoing description of the exemplary embodiments is provided for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise form disclosed. In view of this disclosure, many improvements and changes are possible. It is stipulated that the scope of this disclosure is not limited by this detailed description, but in fact is limited by the scope of the attached patent application. Future filings that claim the priority of this application may claim the disclosed subject matter in different ways, and may generally include any set of one or more limitations as disclosed herein individually or otherwise.

100‧‧‧Integrated Circuit 100'‧‧‧Integrated Circuit 101‧‧‧Gate Transistor 101A, 101B‧‧‧Group IV Transistor 102‧‧‧Transistor 102A, 102B, 102C‧‧‧III- N Transistor 200‧‧‧Substrate 205‧‧‧Processing substrate or wafer 210‧‧‧Insulator layer 215‧‧‧Semiconductor layer 220‧‧‧Dielectric layer 230‧‧‧STI layer 335‧‧‧Trench 440 ‧‧‧III-V semiconductor body 445‧‧‧III-V polarization layer 450, 450A, 450B, 450C‧‧‧III-V semiconductor material 460‧‧‧Gap 570‧‧‧Gate trench 680, 1099, G‧‧‧Gate 89 ‧‧Motherboard 1004‧‧‧Processor 1006‧‧‧Communication chip C‧‧‧Contact D‧‧‧Drain GD‧‧‧Gate dielectric P‧‧‧Polarization layer S‧‧‧Source SOI‧‧‧Semiconductor-on-insulator W, Y‧‧‧Distance X‧‧‧Nominal distance

FIG. 1 is a cross-sectional view of an integrated circuit structure assembled using a co-integrated group III-V NMOS transistor and a group IV PMOS transistor on a common substrate according to an embodiment of the present disclosure.

FIG. 1'is a cross-sectional view of an integrated circuit structure assembled using a co-integrated group III-V NMOS transistor and a group IV PMOS transistor on a common substrate according to another embodiment of the present disclosure.

2 to 10 show an example of an integrated circuit structure for preparing an integrated circuit structure assembled using a co-integrated group III-V NMOS transistor and a group IV PMOS transistor on a common substrate according to an embodiment of the present disclosure Sexual process.

FIG. 11 is an exemplary computing system implemented with one or more of the integrated circuit structures disclosed herein according to some embodiments of the present disclosure.

These and other features of the embodiments of the present invention can be better understood by reading the following detailed description in conjunction with the accompanying drawings described herein. In the drawings, each identical or almost identical component illustrated in each figure may be represented by a similar number. For clarity, not every part is labeled in every figure. In addition, it should be understood that the drawings are not necessarily drawn to scale or are intended to limit the described embodiments to the specific configurations shown. For example, although some figures generally indicate straight lines, right angles and smooth surfaces, given the real-world constraints of the manufacturing process, the actual implementation of the disclosed technology may have imperfect straight lines and right angles, and some features may have Surface topology or otherwise not smooth. In summary, the drawings are provided only to illustrate exemplary structures.

100‧‧‧Integrated Circuit

101A‧‧‧Group IV Transistor

101B‧‧‧Group IV Transistor

102A, 102B, 102C‧‧‧III-N Transistor

C‧‧‧Contact

D‧‧‧Dip pole

G‧‧‧Gate

GD‧‧‧Gate Dielectric

P‧‧‧Polarization layer

S‧‧‧Source

SOI‧‧‧Semiconductor-on-insulator structure

W, Y‧‧‧Distance

X‧‧‧nominal distance

Claims (25)

An integrated circuit, comprising: a semiconductor-on-insulator substrate, the substrate including an embedded insulator layer sandwiched between the upper and lower semiconductor layers of group IV materials; and a first transistor, which is arranged on two Between the second transistors and adjacent to the two second transistors, wherein the first transistor has a channel region included in the upper semiconductor layer, and the second transistors include a group III -N semiconductor structure, the group III-N semiconductor structure is one of the following: on the upper semiconductor layer, or through the upper semiconductor layer and the embedded insulator layer and on the lower semiconductor layer. Such as the integrated circuit of claim 1, wherein the III-N semiconductor structure for each second transistor is in a trench, and the trench has a bottom on the upper semiconductor layer. Such as the integrated circuit of claim 1, wherein the III-N semiconductor structure for each second transistor is in a trench, the trench passes through the upper semiconductor layer and the embedded insulator layer, and has a A bottom on the lower semiconductor layer. Such as the integrated circuit of claim 3, wherein each of the lower and upper semiconductor layers has a crystal orientation relative to the trench direction, and the crystal orientation of the lower semiconductor layer is relative to the upper semiconductor layer The crystal orientation is the same. Such as the integrated circuit of claim 3, wherein each of the lower and upper semiconductor layers has a crystal orientation with respect to the trench direction, and the crystal orientation with respect to the lower semiconductor layer is different from the upper The crystal orientation of the semiconductor layer. Such as the integrated circuit of claim 1, wherein the first transistor has a gate, and the gate is centrally arranged between the second transistors, so that the second transistors are separated by a distance X And the center of the gate is at a position between the second transistors, and the position is within half of the distance of X plus or minus 1 nm. Such as the integrated circuit of claim 6, in which the configuration of one of the first transistors between two adjacent second transistors is repeated multiple times, and the corresponding gate position for each configuration is at X Within half of the corresponding distance plus or minus 1nm. Such as the integrated circuit of claim 1, wherein the upper semiconductor layer is silicon, germanium, or silicon germanium (SiGe), and the lower semiconductor layer is silicon, germanium, or silicon germanium (SiGe). The integrated circuit of claim 1, wherein the first transistor further comprises: a gate dielectric on the channel; a gate metal on the gate dielectric; any one of the channels Side source and drain regions; and a gate spacer between the gate and the source region, and a gate spacer between the gate and the drain region, wherein the gate The polar dielectric is between the channel area and the gate spacers. Such as the integrated circuit of claim 1, wherein the III-N semiconductor structure includes a nucleation layer and a channel layer. Such as the integrated circuit of claim 1, in which the second circuits At least one of the crystals is included in the III-N semiconductor structure or a polarization layer on the III-N semiconductor structure, and wherein the polarization layer includes aluminum and nitrogen. A system-on-a-chip including an integrated circuit as claimed in any one of claims 1 to 11. A radio frequency (RF) circuit, which includes an integrated circuit as claimed in any one of claims 1 to 11. A mobile computing system comprising an integrated circuit as claimed in any one of claims 1 to 11. An integrated circuit comprising: a silicon-on-insulator substrate, which includes an embedded insulator layer sandwiched between upper and lower silicon layers; and a first transistor, which is arranged between two second transistors And adjacent to the two second transistors; wherein the first transistor system is a PMOS transistor and includes: a channel region included in the upper silicon layer; and a high-k gate on the channel region A polar dielectric; a gate metal on the gate dielectric; source and drain regions on each side of the channel region; and a gate between the gate and the source region A pole spacer, and a gate spacer between the gate and the drain region, wherein the gate dielectric is between the channel region and the gate spacers; and the second The transistors are each an NMOS transistor and include: A gallium nitride (GaN) body with a channel region. The GaN host system is one of the following: on the upper silicon layer, or through the upper silicon layer and the embedded insulator layer and on the lower silicon layer On the layer; a polarization layer on the GaN body; and source and drain regions on each side of the channel region. Such as the integrated circuit of claim 15, wherein the III-N semiconductor of each second transistor is in a trench, the trench passes through the upper silicon layer and the embedded insulator layer, and has silicon One layer on the bottom. Such as the integrated circuit of claim 15, wherein the gate of the first transistor is centrally arranged between the second transistors, so that the GaN bodies of the second transistors are separated by a distance X, and the The center of the gate of the first transistor is at a position between the second transistors, and the position is within half the distance of X plus or minus 1 nm. Such as the integrated circuit of claim 17, in which the configuration of one of the first transistors between two adjacent second transistors is repeated multiple times, and the corresponding first transistor gate of each configuration is The position is within half of the corresponding distance of X plus or minus 1nm. Such as the integrated circuit of claim 15, wherein the source and drain regions of the first transistor are silicon, germanium or silicon germanium (SiGe). A system-on-a-chip including an integrated circuit as claimed in any one of claims 15-19. A method of forming an integrated circuit, the method comprising: depositing a cover layer of a high-k gate dielectric material on a semiconductor-on-insulator substrate, the substrate comprising an upper and a lower half of a group IV material Conductor layer and an embedded insulator layer arranged between the upper and lower semiconductor layers; deposit a covering layer of isolation material on the gate dielectric material; pass through the isolation and gate dielectric by etching Dielectric materials are used to form trenches; a Group III-N semiconductor is selectively grown from the trenches to form a lateral epitaxial growth area on the isolation material, so that the lateral epitaxial growth area of adjacent trenches The gap has a width W; and using the lateral epitaxial growth regions as a mask, a circuit feature is formed between the lateral epitaxial growth regions and in the isolation material. The method of claim 21, wherein forming trenches by etching through the isolation and gate dielectric materials further comprises etching through the upper semiconductor layer and the embedded insulator layer to expose the lower semiconductor layer. The method of claim 21, wherein selectively growing a III-N semiconductor from the trenches includes growing a gallium nitride (GaN) body, followed by a polarization layer, followed by more GaN for Form these lateral epitaxial growth regions. The method of claim 21, wherein selectively growing a III-N semiconductor from the trenches includes growing an aluminum nitride (AlN) nucleation layer, followed by growing a gallium nitride (GaN) body, This is followed by a polarization layer, followed by the growth of more GaN to form the lateral epitaxial growth regions. Such as the method of any one of claims 21 to 24, further comprising, after forming the circuit feature, removing the lateral epitaxial growth regions area.

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