TWI748352B - Sample and hold amplifier circuit - Google Patents

Abstract

A sample and hold amplifier circuit is provided that includes a positive and a negative terminal capacitor arrays, a positive and a negative switch arrays and a differential output circuit. A second terminal of each of bit capacitors in the positive and the negative terminal capacitor arrays are respectively coupled to a positive and a negative output terminal. In a sampling time period, according to a first connection relation, each of the connected bit capacitors is controlled to receive a polarity input voltage to perform a gain modification. In a hold time period, according to a second connection relation, each of the connected bit capacitors is controlled to receive an offset modification voltage to perform an offset modification. A positive and a negative output voltages are generated at the positive and the negative output terminal to be outputted as a pair of differential output signals by the differential output circuit.

Description

Sample-and-hold amplifier circuit

The present invention relates to a sample-and-hold amplifying technology, in particular to a sample-and-hold amplifying circuit.

In a signal processing circuit used to process images in the YPrPb format, an AC-coupled signal needs to be received. In order to correctly input the signal to the back-end circuit, such as but not limited to the analog-to-digital conversion circuit, so that the signal can have a full swing output (full swing), the signal needs to be adjusted. If there is no effective adjustment mechanism, the back-end circuit may receive the result that one of the positive and negative signals is compressed and distorted.

In view of the problems of the prior art, one objective of the present invention is to provide a sample-and-hold amplifier circuit to improve the prior art.

The present invention includes a sample and hold amplifier (SHA) circuit, an embodiment of which includes: a positive terminal capacitor array, a negative terminal capacitor array, a positive terminal switching array, a negative terminal switching array, and a differential output circuit. The positive terminal capacitor array and the negative terminal capacitor array each include a plurality of bit capacitors. The bit capacitors each have a first terminal and a second terminal. The second terminal of the bit capacitor of the positive terminal capacitor array is electrically coupled to the positive terminal. The output terminal, the second terminal of the bit capacitor of the negative terminal capacitor array is electrically coupled to the negative output terminal. The positive-end switching array and the negative-end switching array are each configured to enable the bit capacitor to receive the polar input voltage from the first end of the bit capacitor according to the first bit combination connection relationship during the sampling time to adjust the gain relative to the common mode input voltage , And each configuration to make the bit capacitor receive the offset adjustment voltage from the first end of the bit capacitor according to the second bit combination connection relationship during the hold time to adjust the offset relative to the common mode input voltage, and then The positive output terminal and the negative output terminal respectively generate a positive output voltage and a negative output voltage. The differential output circuit is configured to output a positive output voltage and a negative output voltage as a pair of differential output signals.

With regard to the features, implementation and effects of the present invention, preferred embodiments are described in detail as follows in conjunction with the drawings.

An object of the present invention is to provide a sample-and-hold amplifying circuit, which can effectively adjust the gain and offset of the input signal relative to the common mode input voltage to meet the input range of the back-end circuit.

Please refer to Figure 1A. FIG. 1A is a circuit diagram of a sample and hold amplifier (SHA) circuit 100 and an analog-to-digital conversion circuit 160 according to an embodiment of the present invention.

In one embodiment, the sample-and-hold amplifier circuit 100 and the analog-to-digital conversion circuit 160 can be applied to, for example, but not limited to, a signal processing circuit for processing YPrPb format images. Among them, the sample-and-hold amplifier circuit 100 is configured to adjust the gain and offset of the input analog signal to enhance the input analog signal, and adjust the common mode voltage level relative to the input analog signal, which conforms to the analog-to-digital conversion Input requirements for circuit 160.

The sample-and-hold amplifier circuit 100 includes a positive terminal capacitor array 110, a negative terminal capacitor array 120, a positive terminal switching array 130, a negative terminal switching array 140, and a differential output circuit 150.

Please refer to Figure 1B. FIG. 1B is a more detailed schematic diagram of the positive terminal capacitor array 110 and the positive terminal switching array 130 in an embodiment of the present invention.

The positive terminal capacitor array 110 includes a plurality of bit capacitors CL ₀ to CL _n and CM ₀ to CM _n, and a gain adjustment capacitor Cg.

The bit capacitors CL ₀ ˜CL _n and CM ₀ ˜CM _n each have a first terminal and a second terminal. In one embodiment, the bit capacitances CL ₀ to CL _n and CM ₀ to CM _{n are} divided into high bit capacitances CM ₀ to CM _n and low bit capacitances CL ₀ to CL _n . Among them, the bit capacitance CM _n is the capacitance of the highest bit, which has the largest adjustment range for gain and offset. In contrast, the bit capacitance CL ₀ is the lowest bit capacitance, which has the smallest adjustment range for gain and offset.

In one embodiment, the second end phases of the high-bit bit capacitors CM ₀ ~ CM _n are electrically coupled to the positive output terminal PT, and the second end phases of the low-bit bit capacitors CL ₀ ~ CL _n are electrically coupled After connection, it is electrically coupled to the positive output terminal PT through the intermediate capacitor Cb.

The gain adjustment capacitor Cg has a first end and a second end, and the second end of the gain adjustment capacitor Cg is electrically coupled to the positive output terminal PT.

The negative terminal capacitor array 120 has a structure symmetrical to the positive terminal capacitor array 110, except that _{the second ends of the bit capacitors CM 0} ~CM _n and CL ₀ ~CL _{n and} the second end of the gain adjustment capacitor Cg are electrically coupled Connected to the negative output terminal NT. The detailed structure will not be repeated here.

The positive switching array 130 includes a plurality of switching circuits SL ₀ to SL _n and SM ₀ to SM _n . The switching circuits SL ₀ ~SL _n and SM ₀ ~SM _n correspond to bit capacitance CL ₀ ~CL _n and CM ₀ ~CM _{n respectively} .

Please refer to Figure 1C. FIG. 1C is an enlarged schematic diagram of the _{switching circuit SL 0} and the corresponding bit capacitance CL ₀ in an embodiment of the present invention.

The switching circuits SL ₀ ˜SL _n and SM ₀ ˜SM _n each have a first selection unit S1, a second selection unit S2, and a third selection unit S3. In one embodiment, the first selection unit S1 of each switching circuit is controlled by the gain control signals GL ₀ ˜GL _n and GM ₀ ˜GM _n . Taking the switching circuit SL ₀ as an example, the first selection unit S1 is controlled by the gain control signal GL ₀ . The second selection unit S2 is controlled by the offset control signals OL ₀ to OL _n and OM ₀ to OM _n . Taking the switching circuit SL ₀ as an example, the second selection unit S2 is controlled by the offset control signal OL ₀ . The third selection unit S3 is controlled by the mode control signal CKM.

The gain selection unit Sg is set corresponding to the gain adjustment capacitor Cg, and is controlled by the mode control signal CKM.

The negative end switching array 140 has a structure symmetrical to the positive end switching array 130. The detailed structure will not be repeated here.

The first selection unit S1, the second selection unit S2, the third selection unit S3, and the gain selection unit Sg can be interleaved to operate in the operation mode of the sampling time and the holding time. In the following, the positive terminal capacitor array 110 including 10-bit bit capacitors CM ₀ ~ CM ₄ and CL ₀ ~ CL _{4 and the positive end capacitor arrays SM 0} ~ SM ₄ and SL ₀ ~ SL ₄ including the corresponding bit capacitors will be used. The end switching array 130 is described as an example.

Please refer to Figure 2. 2 is a circuit diagram of the positive terminal capacitor array 110 and the positive terminal switching array 130 operating at the sampling time in an embodiment of the present invention.

During the sampling time, the first selection unit S1 is configured to receive the polarity input voltage in the selected state or the common mode input in the unselected state _{according to the control of the gain control signals GL 0} ~GL _n and GM ₀ ~GM _n Voltage Vcmi. Wherein, the polarity input voltage corresponding to the positive terminal switching array 130 is the positive input voltage Vip, and the common mode input voltage Vcmi is the DC voltage.

Third selection means S1 S3 makes a first selection unit electrically according to the mode control signal CKM is coupled to the capacitor corresponding to the (e.g. corresponding to the switching circuits SM ₀ ~ SM ₄ and SL ₀ ~ SL capacitance CM ₄ bits of ₀ ~ CM ₄ and CL ₀ ~CL ₄ ) the first end.

The gain selection unit Sg causes the gain adjustment capacitor Cg to receive the polarity input voltage as the positive input voltage Vip according to the mode control signal CKM.

Therefore, in the operation mode of the sampling time, the sample-and-hold amplifier circuit 100 can switch the first selection unit S1 and the third selection unit S1 and the third selection _{circuit included in each of the switching circuits SM 0} to SM ₄ and SL ₀ to SL _{4 included in the array 130 according to the positive terminal. The unit S3 sets the bit combination connection relationship of the bit capacitances CM 0} to CM ₄ and CL ₀ to CL ₄ of the positive terminal capacitor array 110, and adjusts the gain of the positive input voltage Vip relative to the common mode input voltage Vcmi.

For example, when the connection to be made in relation when represented as bits (1001000100), the switching circuit SM _4, SM ₁ and SL ₂ of the first selection unit S1 will correspond to the first bit and three bits 10,7 The cell capacitors CM ₄ , CM ₁ and CL ₂ become selected to receive the positive input voltage Vip, while other switching circuits make other bit capacitors unselected to receive the common mode input voltage Vcmi.

In one embodiment, when _{the connection relationship of all the bit capacitors CM 0} ~ CM ₄ and CL ₀ ~ CL ₄ is represented by bits as 1 (for example, the 10-bit 11111111111), that is, they all receive the positive input voltage Vip When, the total gain will be 1. And when the connection relationship of all bit capacitances CM ₀ ~ CM ₄ and CL ₀ ~ CL ₄ is expressed in bits as 0 (for example, 0000000000 of 10 bits), that is, when they all receive the common mode input voltage Vcmi, the total The gain will be 0. Therefore, all different bit combinations from high to low can achieve a gain adjustment of ^{2 M+N steps.}

In addition, through the setting of the capacitance value of the gain adjustment capacitor Cg, the gain of the positive input voltage Vip can be more than doubled. Therefore, when the required total gain is a value in the range of one to two times, the capacitance value of the gain adjustment capacitor Cg can generate twice the gain to the positive input voltage Vip, and then the bit capacitor CM ₀ ~CM ₄ and _{the connection relationship of CL 0} ~ CL ₄ is adjusted down to the required value.

Similarly, the sample-and-hold amplifier circuit 100 can set the negative terminal capacitance according to the first selection unit S1 and the third selection unit S3 included in each _{of the switching circuits SM 0} to SM _n and SL ₀ to SL _{n included in the negative terminal switching array 140} The bit combination connection relationship of the bit capacitances CM ₀ to CM _n and CL ₀ to CL _n of the array 120 adjusts the gain of the negative input voltage Vin. I won't repeat it here.

Please refer to Figure 3. FIG. 3 is a circuit diagram of the positive terminal capacitor array 110 and the positive terminal switching array 130 operating in the hold time in an embodiment of the present invention.

In the hold time, the second selection unit S2 is configured to control the signals OL ₀ ~ OL ₄ and OM ₀ ~ OM ₄ according to the offset control, and receive the offset adjustment voltage in the selected state or in the unselected state Receive common mode input voltage Vcmi. Wherein, the offset adjustment voltage is the difference between the first adjustment voltage Vrt and the second adjustment voltage Vrb.

In more detail, in one embodiment, the sample-and-hold amplifier circuit 100 further includes an adjustment selection unit 170 configured to select the first adjustment voltage Vrt and the second adjustment voltage Vrb for input according to different polarities. When it is desired to adjust the positive offset relative to the common mode input voltage Vcmi, the adjustment selection unit 170 enables the second selection unit S2 to receive the first adjustment voltage Vrt minus the second adjustment voltage Vrb to generate the positive adjustment voltage Vrt-Vrb. Adjust the voltage for the offset. When it is desired to adjust the negative offset relative to the common mode input voltage Vcmi, the adjustment selection unit 170 enables the second selection unit S2 to receive the second adjustment voltage Vrb minus the negative adjustment voltage Vrb-Vrt generated by the first adjustment voltage Vrt Adjust the voltage as an offset.

The third selection unit S3 electrically couples the second selection unit S2 to the corresponding capacitors according to the mode control signal CKM (for example, the bit capacitors CM ₀ ~ CM ₄ and _{corresponding switching circuits SM 0} ~ SM ₄ and SL ₀ ~ SL ₄₎ CL ₀ ~CL ₄ ) the first end.

The gain selection unit Sg makes the gain adjustment capacitor Cg receive the common mode input voltage Vcmi according to the mode control signal CKM.

Therefore, in the operation mode of the hold time, the sample-and-hold amplifier circuit 100 can switch the second selection unit S2 and the third selection unit S2 and the third selection in each _{of the switching circuits SM 0} to SM ₄ and SL ₀ to SL _{4 included in the array 130 according to the positive terminal. The unit S3 sets the bit combination connection relationship of the bit capacitances CM 0} to CM ₄ and CL ₀ to CL ₄ of the positive terminal capacitor array 110, and adjusts the offset of the positive input voltage Vip relative to the common mode input voltage Vcmi.

For example, when the connection relationship to be performed is expressed as (0111101111) in bits, _{the first selection unit S1 of the switching circuits SM 3} ~SM ₀ and SL ₃ ~SL ₀ will be corresponding to the 9th to 6th and 4th to respectively. The 1-bit bit capacitors CM ₃ ~ CM ₀ and CL ₃ ~ CL ₀ become the selected state to receive the offset adjustment voltage, while other switching circuits make other bit capacitors unselected. Receive common mode input voltage Vcmi.

In one embodiment, when _{the connection relationship of all the bit capacitances CM 0} ~ CM ₄ and CL ₀ ~ CL ₄ is expressed in bits as 1 (for example, the 10-bit 11111111111), that is, both receive offset adjustment When the voltage is applied, the total adjustment amount will be the value of the offset adjustment voltage (Vrt-Vrb or Vrb-Vrt). And when the connection relationship of all bit capacitances CM ₀ ~ CM ₄ and CL ₀ ~ CL ₄ is expressed in bits as 0 (for example, 0000000000 of 10 bits), that is, when they all receive the common mode input voltage Vcmi, the total The adjustment amount will be 0. Therefore, all different bit combinations from high to low can achieve an offset adjustment of ^{2 M+N steps.}

Similarly, the sample-and-hold amplifier circuit 100 can set the negative terminal capacitance according to the second selection unit S2 and the third selection unit S3 included in each _{of the switching circuits SM 0} to SM _n and SL ₀ to SL _{n included in the negative terminal switching array 140} The bit combination connection relationship of the bit capacitance CM ₀ ~ CM _n and CL ₀ ~ CL _n of the array 120 adjusts the offset of the negative input voltage Vin. I won't repeat it here.

After the gain adjustment of the sampling time and the offset adjustment of the hold time, the positive terminal capacitor array 110 and the negative terminal capacitor array 120 will be electrically coupled to the positive output terminal PT and the negative output terminal of the second terminal of each cell capacitor. NT generates a positive output voltage Vp and a negative output voltage Vn.

The differential output circuit 150 is configured to output the positive output voltage Vp and the negative output voltage Vn as a pair of differential output signals Vop and Von.

In one embodiment, the differential output circuit 150 includes an amplifier 180, a first coupling capacitor CP1, a second coupling capacitor CP2, and first to sixth switches SW1 to SW6.

The amplifier 180 includes the amplifier input positive terminal (indicated by the'+' symbol in Figure 1A), the amplifier input negative terminal (indicated by the'-' symbol in Figure 1A), and the amplifier output positive terminal (indicated by the'+' in Figure 1A). Mark) and the negative terminal of the amplifier output (marked with a'-' mark in Figure 1A).

Wherein, the positive input terminal of the amplifier is electrically coupled to the negative output terminal NT to receive the negative output voltage Vn. The negative input terminal of the amplifier is electrically coupled to the positive output terminal PT to receive the positive output voltage Vp. The amplifier output positive terminal and the amplifier output negative terminal are configured to output the pair of differential output signals Vop and Von according to the positive output voltage Vp and the negative output voltage Vn.

The first coupling capacitor CP1 and the second coupling capacitor CP2 each include a first terminal and a second terminal. The first terminal of the first coupling capacitor CP1 is electrically coupled to the negative input terminal of the amplifier, and the first terminal of the second coupling capacitor CP2 It is electrically coupled to the positive input terminal of the amplifier.

As shown in FIG. 2, during the sampling time, the first switch SW1 and the second switch SW2 are respectively configured to be controlled by the mode control signal CKM so that the amplifier input positive terminal and the amplifier input negative terminal receive the common mode input voltage Vcmi.

The third switch SW3 and the fourth switch SW4 are respectively configured to be controlled by the mode control signal CKM so that the second ends of the first coupling capacitor CP1 and the second coupling capacitor CP2 receive the common mode output voltage Vcmi.

Further, as shown in FIG. 3, during the hold time, the fifth switch SW5 and the sixth switch SW6 are respectively configured to be controlled by the mode control signal CKM so that the second terminal of the first coupling capacitor CP1 and the amplifier output positive terminal are electrically connected The second terminal of the second coupling capacitor CP2 is electrically coupled to the negative output terminal of the amplifier.

In an embodiment, the positive terminal capacitor array 130 and the negative terminal capacitor array 140 have the first equivalent capacitance value under the bit combination connection relationship in the sampling time. The first coupling capacitor and the second coupling capacitor each have a coupling capacitance value. The gain generated by the positive-end capacitor array 130 and the negative-end capacitor array 140 is the ratio of the first equivalent capacitance value to the coupling capacitance value.

In addition, the positive terminal capacitor array 130 and the negative terminal capacitor array 140 have a second equivalent capacitance value under the bit combination connection relationship in the holding time. The first coupling capacitor and the second coupling capacitor each have a coupling capacitance value. The offset generated by the positive-end capacitor array 130 and the negative-end capacitor array 140 is the ratio of the second equivalent capacitance value to the coupling capacitance value.

In more detail, the difference Vop-Von between the differential output signals Vop and Von can be expressed as:

Vop-Von=(Vip-Vin)×GA±(Vrt-Vrb)×OFF (Equation 1)

Among them, GA and OFF are gain and offset respectively, and can be further expressed as:

GA=(CG _MSB +(CG _LSB )/(CT _LSB +Cb))/Cf (Equation 2)

OFF=(CO _MSB +(CO _LSB )/(CT _LSB +Cb))/Cf (Equation 3)

Among them, _{the total capacitance value of the CG MSB} and CO _MSB gain adjustment capacitors and the high-bit bit capacitors respectively in the one-bit combination connection relationship:

CG _MSB =Cg+CM _n ×gM _n +CM _n-1 ×gM _n-1 +…CM ₀ ×gM ₀ (Equation 4)

CO _MSB =Cg+CM _n ×oM _n +CM _n-1 ×oM _n-1 +…CM ₀ ×oM ₀ (Equation 5)

CG _LSB and CO _LSB are the total capacitance values of the low-bit bit capacitors under the one-bit combination connection relationship:

CG _LSB = CL _n ×gL _n +CL _n-1 ×gL _n-1 +…CL ₀ ×gL ₀ (Equation 6)

CO _LSB = CL _n ×oL _n +CL _n-1 ×oL _n-1 +…CL ₀ ×oL ₀ (Equation 7)

gM _n , gM _n-1 ,...gM ₀ and gL _n , gL _n-1 ,...gL ₀ are the unit-bit gains of each bit-cell capacitance, respectively. When the bit capacitor is selected to adjust the gain, it is 1, and when the bit capacitor is not selected to adjust the gain, it is 0. oM _n , oM _n-1 , ... oM ₀ and oL _n , oL _n-1 , ... oL ₀ are the unit bit offsets of each bit cell capacitance respectively. When the bit capacitance is selected to adjust the offset, it is 1, and when the bit capacitance is not selected to adjust the offset, it is 0.

CT _LSB is the sum of the capacitance values of all low-bit capacitors:

CT _LSB = CL _n +CL _n-1 +…CL ₀ (Equation 8)

Cb is the capacitance value of the intermediate capacitor Cb. Cf is the capacitance value of the first coupling capacitor CP1 and the second coupling capacitor CP2.

When the value of Cb is C, CL _n is 2 ^Ln C, CM _n is 2 ^Mc C, Cf is 2 ^Ln+1 C, and Cg/Cf is gc, and M _n , M _n-1 , ... M ₀ to L _{When n} , L _n-1 ,...L _{0 are} mapped to K, K-1,...0, (Equation 2) and (Equation 3) can be simplified to:

GA=gc+g _K /2 ¹ +g _K-1 /2 ² +g _k-2 /2 ³ +…g ₀ /2 ^K+1 (Equation 9)

OFF=o _K /2 ¹ +o _K-1 /2 ² +o _k-2 /2 ³ +…o ₀ /2 ^K+1 (Equation 10)

Therefore, after substituting the gain GA and the offset OFF (Equation 1), it will become:

Vop-Von=(Vip-Vin)×(gc+g _K /2 ¹ +g _K-1 /2 ² +g _k-2 /2 ³ +…g ₀ /2 ^K+1 )±(Vrt-Vrb) ×(o _K /2 ¹ +o _K-1 /2 ² +o _k-2 /2 ³ +…o ₀ /2 ^K+1 ) (Equation 11)

In one embodiment, the sample-and-hold amplifier circuit 100 further includes a control circuit 190 configured to determine the difference between the pair of differential output signals Vop and Von relative to the voltage input range RAN of the digital conversion circuit 160 to generate gain based on the difference The control signals GL ₀ ~GL _n , GM ₀ ~GM _n and the offset control signals OL ₀ ~OL _n and OM ₀ ~OM _n are adjusted by feedback mechanism.

It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art can make changes without departing from the spirit of the present invention.

In summary, the sample-and-hold amplifying circuit of the present invention can effectively adjust the gain and offset of the input signal relative to the common-mode input voltage, which conforms to the input range of the back-end circuit.

Although the embodiments of the present invention are as described above, these embodiments are not used to limit the present invention. Those with ordinary knowledge in the art can apply changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may belong to the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to the scope of the patent application in this specification.

100: Sample-and-hold amplifier circuit 110: Positive terminal capacitor array 120: Negative terminal capacitor array 130: Positive terminal switching array 140: Negative terminal switching array 150: Differential output circuit 160: Analog to digital conversion circuit 170: Adjustment selection unit 180: Amplifier 190: control circuit Cb: intermediate capacitor Cg: gain adjustment capacitor CKM: mode control signal CL ₀ ~ CL _n , CM ₀ ~ CM _n : bit capacitor CP1: first coupling capacitor CP2: second coupling capacitor GL ₀ ~ GL _n , GM ₀ ~ GM _n : gain control signal NT: negative output terminal OL ₀ ~ OL _n , OM ₀ ~ OM _n : offset control signal PT: positive output terminal RAN: voltage input range S1: first selection unit S2 : Second selection unit S3: Third selection unit SL ₀ ~ SL _n , SM ₀ ~ SM _n : Switching circuit SW1 ~ SW6: First switch to sixth switch Vcmi: Common mode input voltage Vcmo: Common mode output voltage Vin: Negative input voltage Vip: positive input voltage Vn: negative output voltage Vop, Von: differential output signal Vp: positive output voltage Vrb: second adjusted voltage Vrt: first adjusted voltage

[Figure 1A] shows a circuit diagram of a sample-and-hold amplifier circuit and an analog-to-digital conversion circuit in an embodiment of the present invention; [Figure 1B] shows a more detailed schematic diagram of the positive terminal capacitor array and the positive terminal switching array in an embodiment of the present invention; [Figure 1C] shows an enlarged schematic diagram of the switching circuit and the corresponding bit capacitance in an embodiment of the present invention; [Figure 2] shows a circuit diagram of the positive terminal capacitor array and the positive terminal switching array operating at the sampling time in an embodiment of the present invention; and [Figure 3] shows a circuit diagram of the positive terminal capacitor array and the positive terminal switching array operating in the hold time in an embodiment of the present invention.

100: Sample-and-hold amplifier circuit 110: Positive terminal capacitor array 120: Negative terminal capacitor array 130: Positive terminal switching array 140: Negative terminal switching array 150: Differential output circuit 160: Analog to digital conversion circuit 170: Adjustment selection unit 180: Amplifier 190: control circuit CKM: mode control signal CP1: first coupling capacitor CP2: second coupling capacitor GL ₀ ~GL _n , GM ₀ ~ GM _n : gain control signal NT: negative output terminal OL ₀ ~ OL _n , OM ₀ ~OM _n : Offset control signal PT: Positive output terminal SW1~SW6: First switch to sixth switch Vin: Negative input voltage Vip: Positive input voltage Vn: Negative output voltage Vop, Von: Differential output signal Vp: Positive output voltage Vrb: second adjusted voltage Vrt: first adjusted voltage

Claims (10)

A sample and hold amplifier (SHA) circuit, including: A positive terminal capacitor array and a negative terminal capacitor array each include a plurality of bit capacitors, each of the bit capacitors has a first terminal and a second terminal, wherein the bit capacitors of the positive terminal capacitor array are The second terminal phase is electrically coupled to a positive output terminal, and the second terminal phase of the bit capacitors of the negative terminal capacitor array is electrically coupled to a negative output terminal; A positive terminal switching array and a negative terminal switching array are each configured to enable the bit capacitors to receive a polarity from the first terminal of each bit capacitor according to a first bit combination connection relationship during a sampling time The input voltage is adjusted in gain relative to a common-mode input voltage, and each configuration is configured to enable the bit capacitors to receive a signal from the first end of each bit capacitor according to a second bit combination connection relationship during a holding time The offset adjustment voltage adjusts the offset relative to the common mode input voltage, and generates a positive output voltage and a negative output voltage at the positive output terminal and the negative output terminal, respectively; and A differential output circuit is configured to output the positive output voltage and the negative output voltage as a pair of differential output signals. As for the sample-and-hold amplifying circuit described in item 1 of the scope of patent application, the positive-side switching array and the negative-side switching array each include a plurality of switching circuits, and each of the switching circuits has: A first selection unit configured to receive the polarity input voltage in a selected state or the common mode input voltage in an unselected state according to the control of a gain control signal during the sampling time, wherein the The polarity input voltages corresponding to the positive-end switching array and the negative-end switching array are respectively a positive input voltage and a negative input voltage; A second selection unit configured to selectively receive the offset adjustment voltage in the selected state or receive the offset adjustment voltage in the unselected state according to the control of an offset control signal during the holding time Common mode input voltage; and A third selection unit, configured to control the first selection unit according to a mode control signal during the sampling time, electrically couple the first selection unit to the first end corresponding to one of the capacitors, and during the hold time In this case, the second selection unit is electrically coupled to the first end corresponding to one of the capacitors. In the sample-and-hold amplifier circuit described in item 2 of the scope of patent application, the positive terminal capacitor array and the negative terminal capacitor array further include a gain adjustment capacitor, which has a first terminal and a second terminal, and the positive terminal capacitor The second end of the gain adjustment capacitor of the array is electrically coupled to the positive output end, and the second end of the gain adjustment capacitor of the negative end capacitor array is electrically coupled to the negative output end; The positive-end switching array and the negative-end switching array further include a gain selection unit respectively configured to enable the gain adjustment capacitor to receive the polarity input voltage for gain adjustment relative to the common mode input voltage during the sampling time, and Make the gain adjustment capacitor receive the common mode input voltage during the hold time; The capacitance values of the positive-end gain capacitor and the negative-end gain capacitor make the polarity input voltage produce a gain of more than one time. The sample-and-hold amplifying circuit described in item 2 of the scope of patent application, wherein the differential output circuit is electrically coupled to an analog-to-digital conversion circuit, and the sample-and-hold amplifying circuit further includes a control circuit configured to determine the pair difference A gap between the dynamic output signal and a voltage input range of the analog-to-digital conversion circuit is used to generate the gain control signal and the offset control signal according to the gap. The sample-and-hold amplifier circuit described in item 2 of the scope of patent application, wherein the differential output circuit includes: An amplifier, including: A positive input terminal of an amplifier is electrically coupled to the negative output terminal to receive the negative output voltage; An amplifier input negative terminal electrically coupled to the positive output terminal to receive the positive output voltage; and An amplifier output positive terminal and an amplifier output negative terminal configured to output the pair of differential output signals according to the positive output voltage and the negative output voltage; A first switch and a second switch are respectively configured to control the control signal according to the mode control signal during the sampling time, so that the positive input terminal of the amplifier and the negative input terminal of the amplifier receive the common mode input voltage; A first coupling capacitor and a second coupling capacitor each include a first terminal and a second terminal, the first terminal of the first coupling capacitor is electrically coupled to the negative input terminal of the amplifier, and the second coupling capacitor The first terminal is electrically coupled to the positive input terminal of the amplifier; A third switch and a fourth switch are respectively configured to control the control signal according to the mode control signal during the sampling time so that the second end of the first coupling capacitor and the second coupling capacitor receive a common mode output voltage; and A fifth switch and a sixth switch are respectively configured to control the control signal according to the mode control signal during the holding time so that the second terminal of the first coupling capacitor is electrically coupled to the positive output terminal of the amplifier and the second The second terminal of the coupling capacitor is electrically coupled to the negative output terminal of the amplifier. The sample-and-hold amplifier circuit described in item 5 of the scope of patent application, wherein the positive terminal capacitor array and the negative terminal capacitor array respectively have a first bit combination connection relationship and the second bit combination connection relationship An equivalent capacitance value and a second equivalent capacitance value, the first coupling capacitor and the second coupling capacitor each have a coupling capacitance value, and the gain generated by the positive terminal capacitor array and the negative terminal capacitor array is the first The ratio of the equivalent capacitance value to the coupling capacitance value, and the offset generated by the positive-end capacitance array and the negative-end capacitance array is the ratio of the second equivalent capacitance value to the coupling capacitance value. For example, the sample-and-hold amplifier circuit described in item 1 of the scope of patent application further includes an adjustment selection unit configured to adjust the positive offset relative to the common mode input voltage during the holding time, so that the second The selection unit receives a first adjustment voltage minus a second adjustment voltage to generate a positive adjustment voltage as the offset adjustment voltage, and performs a negative offset adjustment relative to the common mode input voltage during the hold time When the second selection unit receives the second adjustment voltage minus the first adjustment voltage to generate a negative adjustment voltage as the offset adjustment voltage. For example, in the sample-and-hold amplifier circuit described in item 1 of the scope of patent application, the bit capacitors included in the positive-side capacitor array and the negative-side capacitor array are divided into a group of high-bit capacitors and a group of low-bit capacitors. The second end of the bit capacitors of the group of high-bit capacitors is directly electrically coupled to the positive output end or the negative output end, and the second end of the bit capacitors of the group of low-bit capacitors passes through an intermediate The capacitor is electrically coupled to the positive output terminal or the negative output terminal. For example, in the sample-and-hold amplifier circuit described in item 1 of the scope of the patent application, the number of the bit capacitors is N to generate 2 ^N- step gain and offset. For the sample-and-hold amplifier circuit described in item 1 of the scope of patent application, the maximum gain generated by the bit capacitors is 1.

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