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TWI746412B - Method for startup of crystal oscillator with aid of external clock injection, crystal oscillator and monitoring circuit - Google Patents

Method for startup of crystal oscillator with aid of external clock injection, crystal oscillator and monitoring circuit Download PDF

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Publication number
TWI746412B
TWI746412B TW110119928A TW110119928A TWI746412B TW I746412 B TWI746412 B TW I746412B TW 110119928 A TW110119928 A TW 110119928A TW 110119928 A TW110119928 A TW 110119928A TW I746412 B TWI746412 B TW I746412B
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frequency
injection
voltage
signal
demodulated
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TW110119928A
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TW202213944A (en
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陳建瑋
薛育理
黃柏鈞
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聯發科技股份有限公司
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/15Constructional features of resonators consisting of piezoelectric or electrostrictive material

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A method for startup of a crystal oscillator (XO) with aid of external clock injection, XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

Description

借助外部時鐘注入啟動晶體振盪器的方法、晶體振盪器及監 視電路 The method of starting the crystal oscillator with external clock injection, crystal oscillator and monitoring Visual circuit

本發明涉及晶體振盪器(crystal oscillator,XO)的快速啟動,並且更具體地,涉及借助於外部時鐘注入來啟動XO的方法、相關聯的XO以及監視電路(monitoring circuit)。 The present invention relates to a fast start-up of a crystal oscillator (XO), and more specifically, to a method of starting an XO by means of external clock injection, an associated XO, and a monitoring circuit.

對於未來的通信應用(例如,占空比的(duty-cycled)無線/有線系統),當沒有資料要發送或接收時,通信設備內的晶體振盪器(crystal oscillator,XO)可以進入睡眠模式(例如,禁止XO的振盪)以節省電量;當有資料要發送或接收時,XO可以進入喚醒模式以啟動振盪,然後進入具有穩定振盪的監聽(listen)模式,使得通信設備可以正常發送或接收資料。 For future communication applications (for example, duty-cycled wireless/wired systems), when there is no data to send or receive, the crystal oscillator (XO) in the communication device can enter sleep mode ( For example, prohibit the oscillation of XO to save power; when there is data to be sent or received, XO can enter the wake-up mode to start the oscillation, and then enter the listen mode with stable oscillation, so that the communication device can send or receive data normally .

例如,對應於監聽模式的時間段可以是1毫秒(ms),並且對應於喚醒模式的時間段(可以稱為啟動時間TSTART)可以是5ms,其中,喚醒模式會消耗功率(例如,消耗總功率的42.7%)。因此,XO的啟動時間可能成為降低平均功率的瓶頸。設計人員可以通過控制XO內的負電阻來嘗試減少啟動時間,但這可能會帶來額外的功耗。因此,需要一種新穎的XO的啟動方法和相關架構,以解決相關技術的問題。 For example, the time period corresponding to the listening mode may be 1 millisecond (ms), and the time period corresponding to the wake-up mode (may be referred to as the start-up time TSTART) may be 5 ms, where the wake-up mode consumes power (e.g., consumes total power) 42.7%). Therefore, the start-up time of XO may become a bottleneck in reducing average power. Designers can try to reduce the startup time by controlling the negative resistance in the XO, but this may bring additional power consumption. Therefore, a novel XO startup method and related architecture are needed to solve the related technical problems.

本發明的目的是提供一種借助於外部時鐘注入來啟動晶體振盪器(XO)的方法,相關的XO和監視電路,以加速XO的啟動而不會大大增加額外的能量消耗。 The purpose of the present invention is to provide a method for starting a crystal oscillator (XO) by means of external clock injection, related XO and monitoring circuits, to accelerate the starting of the XO without greatly increasing additional energy consumption.

本發明的至少一個實施例提供了一種借助於外部時鐘注入來啟動XO的方法。該方法可以包括:利用XO內XO核心電路外部的外部振盪器來產生注入信號,其中XO包括XO核心電路,位於XO核心電路外部的外部振盪器以及至少一個注入開關。所述至少一個注入開關耦接於所述XO的注入節點與所述XO核心電路的輸出端之間,所述外部振盪器耦接至所述注入節點,且所述外部振盪器的品質因數低於XO核心電路的品質因數;接通至少一個注入開關以使注入信號的能量注入到XO核心電路中,從而在XO的啟動過程中增加XO核心電路的固有振盪信號的能量,其中根據注入信號與固有振盪信號的組合,在注入節點上產生調製信號;根據調製信號控制外部振盪器選擇性的改變注入信號的注入頻率。更特別地,當外部振盪器選擇性地改變注入信號的注入頻率時,至少一個注入開關被接通。 At least one embodiment of the present invention provides a method for starting XO by means of external clock injection. The method may include: using an external oscillator outside the XO core circuit in the XO to generate the injection signal, where the XO includes the XO core circuit, an external oscillator located outside the XO core circuit, and at least one injection switch. The at least one injection switch is coupled between the injection node of the XO and the output terminal of the XO core circuit, the external oscillator is coupled to the injection node, and the quality factor of the external oscillator is low The quality factor of the XO core circuit; turn on at least one injection switch to inject the energy of the injected signal into the XO core circuit, thereby increasing the energy of the natural oscillation signal of the XO core circuit during the start-up process of the XO, wherein according to the injected signal and The combination of natural oscillation signals generates a modulation signal on the injection node; according to the modulation signal, the external oscillator is controlled to selectively change the injection frequency of the injection signal. More specifically, when the external oscillator selectively changes the injection frequency of the injection signal, at least one injection switch is turned on.

本發明的至少一個實施例提供了一種XO。XO可包括XO核心電路,外部振盪器,至少一個注入開關和頻率控制器,其中外部振盪器耦接到XO的注入節點,至少一個注入開關耦接在XO的注入節點和XO核心電路的輸出端之間,頻率控制器耦接到外部振盪器。XO核心電路可以被配置為在XO核心電路內生成固有振盪信號。外部振盪器可以被配置為在外部振盪器內生成注入信號,其中,外部振盪器的品質因數低於XO核心電路的品質因數。例如,當至少一個注入開關被接通時,注入信號的能量被注入到XO核心電路中,以在XO的啟動過程中增加固有振盪信號的能量,並且根據注入信號與固有振盪信號的組合在注入節點上產生調製信號。頻率控制器可以被配置為接收調製信號並根據調製信號控制外部振盪器選擇性地改變注入信號的注入頻率。更特別地,當外部 振盪器選擇性地改變注入信號的注入頻率時,至少一個注入開關被接通。 At least one embodiment of the present invention provides an XO. The XO may include an XO core circuit, an external oscillator, at least one injection switch and a frequency controller, wherein the external oscillator is coupled to the injection node of the XO, and at least one injection switch is coupled to the injection node of the XO and the output terminal of the XO core circuit In between, the frequency controller is coupled to an external oscillator. The XO core circuit may be configured to generate a natural oscillation signal within the XO core circuit. The external oscillator may be configured to generate an injection signal in the external oscillator, wherein the quality factor of the external oscillator is lower than the quality factor of the XO core circuit. For example, when at least one injection switch is turned on, the energy of the injection signal is injected into the XO core circuit to increase the energy of the natural oscillation signal during the XO startup process, and the injection signal is injected according to the combination of the injection signal and the natural oscillation signal. A modulated signal is generated on the node. The frequency controller may be configured to receive the modulation signal and control the external oscillator to selectively change the injection frequency of the injection signal according to the modulation signal. More specifically, when the external When the oscillator selectively changes the injection frequency of the injection signal, at least one injection switch is turned on.

本發明的至少一個實施例提供了一種監視電路,該監視電路用於生成解調電壓序列的連續比較結果,該解調電壓序列攜帶有XO的注入信號和固有振盪信號之間的相對相位的資訊。監視電路可以包括放大器,電容器和回路開關。放大器可以被配置為通過放大器的第一輸入端接收解調電壓序列,其中,解調電壓序列包括第一電壓和跟隨第一電壓的第二電壓。電容器耦接到放大器的第二輸入端,並且電容器可以被配置為順序地存儲解調電壓序列。回路開關耦接在放大器的第二輸入端和輸出端之間,並且回路開關被配置為控制放大器的配置。例如,當回路開關被接通時,放大器被配置為單位增益緩衝器,以將第一電壓從放大器的第一輸入端傳輸到電容器。當所述回路開關斷開時,所述放大器被配置為比較器,用於將所述放大器的第一輸入端上的第二電壓與所述電容器上存儲的第一電壓進行比較,並生成所述連續比較結果的比較結果,其中,比較結果攜帶注入信號與XO的固有振盪信號之間的相對相位的資訊,用於控制注入信號的注入頻率。 At least one embodiment of the present invention provides a monitoring circuit for generating a continuous comparison result of a demodulated voltage sequence, the demodulated voltage sequence carrying information about the relative phase between the XO injection signal and the natural oscillation signal . The monitoring circuit can include amplifiers, capacitors, and loop switches. The amplifier may be configured to receive a demodulated voltage sequence through a first input terminal of the amplifier, wherein the demodulated voltage sequence includes a first voltage and a second voltage following the first voltage. The capacitor is coupled to the second input terminal of the amplifier, and the capacitor may be configured to sequentially store the demodulated voltage sequence. The loop switch is coupled between the second input terminal and the output terminal of the amplifier, and the loop switch is configured to control the configuration of the amplifier. For example, when the loop switch is turned on, the amplifier is configured as a unity gain buffer to transfer the first voltage from the first input terminal of the amplifier to the capacitor. When the loop switch is off, the amplifier is configured as a comparator for comparing the second voltage on the first input terminal of the amplifier with the first voltage stored on the capacitor, and generating all The comparison result of the continuous comparison result, wherein the comparison result carries information about the relative phase between the injection signal and the natural oscillation signal of the XO, and is used to control the injection frequency of the injection signal.

本發明實施例提供的啟動方法及相關的XO可以利用外部振盪器向XO核心電路注入能量,以加速XO的啟動過程。有利的是,在啟動過程中,可以一直接通耦接在外部振盪器和XO核心電路之間的注入開關,從而可以優化時鐘注入的效率。在一些實施例中,當調整注入頻率(鎖定到XO核心電路的固有頻率)時,注入開關可以始終接通,至少接通一段時間,或者交替的接通和斷開以優化或提高時鐘注入效率。與先前技術相比,可以大大減少XO的總體啟動時間。因此,本發明可以優化XO的整體性能而不會引起任何副作用,或者以不太可能引起副作用的方式優化XO的整體性能。 The startup method and the related XO provided by the embodiment of the present invention can use an external oscillator to inject energy into the XO core circuit to accelerate the startup process of the XO. Advantageously, during the startup process, the injection switch coupled between the external oscillator and the XO core circuit can be turned on all the time, so that the efficiency of clock injection can be optimized. In some embodiments, when the injection frequency is adjusted (locked to the natural frequency of the XO core circuit), the injection switch can be turned on all the time, at least for a period of time, or alternately turned on and off to optimize or improve the clock injection efficiency . Compared with the prior art, the overall startup time of XO can be greatly reduced. Therefore, the present invention can optimize the overall performance of the XO without causing any side effects, or optimize the overall performance of the XO in a manner that is unlikely to cause side effects.

在閱讀了在各個附圖和附圖中示出的優選實施例的以下詳細描述之後,本發明的這些和其他目的無疑對於所屬領域具有通常知識者將變得顯而易 見。 After reading the following detailed description of the preferred embodiments shown in the various drawings and drawings, these and other objects of the present invention will undoubtedly become obvious to those with ordinary knowledge in the field. See.

10:XO 10: XO

11:主動器件 11: Active device

20:XO 20: XO

200:外部振盪器 200: external oscillator

100:XO核心電路 100: XO core circuit

300:頻率控制器 300: frequency controller

S310,S320,S330:步驟 S310, S320, S330: steps

210:低Q振盪器 210: Low Q oscillator

220:輸出緩衝器 220: output buffer

310:解調電路 310: Demodulation circuit

D0:二極體 D0: Diode

CS:採樣電容器 C S : sampling capacitor

330:有限狀態機 330: Finite State Machine

320:監視電路 320: monitoring circuit

322:D觸發器 322: D flip-flop

AMPCOMP:放大器 AMP COMP : Amplifier

CCOMP:電容器 C COMP : Capacitor

30:XO 30: XO

COMP:比較器 COMP: Comparator

320A:監視電路 320A: Monitoring circuit

RST,RSTB,SH,SHB,VA,VB:信號 RST, RSTB, SH, SHB, VA, VB: signal

CLKcounting:計數時鐘 CLK counting : counting clock

40:XO 40: XO

320B:ADC 320B: ADC

第1圖是示出根據本發明實施例的關於借助於外部時鐘注入來啟動晶體振盪器(crystal oscillator,XO)的概念的示意圖。 FIG. 1 is a schematic diagram showing the concept of starting a crystal oscillator (XO) by means of external clock injection according to an embodiment of the present invention.

第2圖是示出根據本發明實施例的XO的示意圖。 Figure 2 is a schematic diagram showing an XO according to an embodiment of the present invention.

第3圖是根據本發明實施例的借助於外部時鐘注入的啟動第2圖所示XO的方法的流程圖。 Fig. 3 is a flowchart of a method for starting the XO shown in Fig. 2 by means of external clock injection according to an embodiment of the present invention.

第4圖是示出根據本發明實施例的具有變化的相對相位的一些信號的波形圖案的示意圖。 FIG. 4 is a schematic diagram showing waveform patterns of some signals with varying relative phases according to an embodiment of the present invention.

第5圖示出了根據本發明實施例的固有(intrinsic)振盪信號的增長率與相對相位之間的關係。 Figure 5 shows the relationship between the growth rate and the relative phase of an intrinsic oscillation signal according to an embodiment of the present invention.

第6圖是示出根據本發明實施例的通過解調電路生成一系列解調電壓的詳細實施方式的示意圖。 Fig. 6 is a schematic diagram showing a detailed implementation of generating a series of demodulated voltages by a demodulation circuit according to an embodiment of the present invention.

第7圖示出了根據本發明實施例的相對相位與失真之間的關係的一些細節。 Figure 7 shows some details of the relationship between relative phase and distortion according to an embodiment of the present invention.

第8圖示出了根據本發明實施例的相對相位和解調電壓之間的關係的一些細節。 Figure 8 shows some details of the relationship between the relative phase and the demodulated voltage according to an embodiment of the present invention.

第9圖示出了根據本發明實施例的相對相位與失真之間的關係的一些細節。 Figure 9 shows some details of the relationship between relative phase and distortion according to an embodiment of the present invention.

第10圖示出了根據本發明實施例的相對相位與解調電壓之間的關係的一些細節。 Figure 10 shows some details of the relationship between the relative phase and the demodulated voltage according to an embodiment of the present invention.

第11圖是示出根據本發明的實施例的第2圖所示XO的詳細實施方式的示意圖。 Fig. 11 is a schematic diagram showing a detailed implementation of the XO shown in Fig. 2 according to an embodiment of the present invention.

第12圖示出了在預設置階段(preset phase),第11圖所示的監視電路的操作。 Figure 12 shows the operation of the monitoring circuit shown in Figure 11 during the preset phase.

第13圖示出了在評估階段(evaluation phase),第11圖所示的監視電路的操作。 Figure 13 shows the operation of the monitoring circuit shown in Figure 11 during the evaluation phase.

第14圖示出根據本發明實施例的第2圖中所示XO的詳細實施方式的示意圖。 Figure 14 shows a schematic diagram of a detailed implementation of the XO shown in Figure 2 according to an embodiment of the present invention.

第15圖示出根據本發明另一實施例的第2圖中所示XO的詳細實施方式的示意圖。 Figure 15 shows a schematic diagram of a detailed implementation of the XO shown in Figure 2 according to another embodiment of the present invention.

第16圖是根據本發明實施例的第15圖所示實施方式內的一些信號的時序圖。 Fig. 16 is a timing diagram of some signals in the embodiment shown in Fig. 15 according to an embodiment of the present invention.

第17圖是示出根據本發明另一實施例的第2圖中所示XO的詳細實施方式的示意圖。 Fig. 17 is a schematic diagram showing a detailed implementation of the XO shown in Fig. 2 according to another embodiment of the present invention.

第18圖示出根據本發明實施例的與控制注入頻率有關的一些細節。 Figure 18 shows some details related to controlling the injection frequency according to an embodiment of the present invention.

第19圖示出了根據本發明另一實施例的與控制注入頻率有關的一些細節。 Figure 19 shows some details related to controlling the injection frequency according to another embodiment of the present invention.

在整個以下描述和請求項中使用指示特定組件的某些術語。如所屬領域具有通常知識者將理解的,電子設備製造商可以用不同的名稱來指代組件。本文檔無意區分名稱不同但功能相同的組件。在以下描述和請求項中,術語“包括”和“包含”以開放式方式使用,因此應解釋為表示“包括但不限於...”。同樣,術語“耦接”旨在表示間接或直接的電連接。因此,如果一個設備耦接到另一設備,則該連接可以是通過直接電連接,或者是通過經由其他設備和連接的間接電連接。 Certain terms indicating specific components are used throughout the following description and request items. As those with ordinary knowledge in the field will understand, electronic device manufacturers can use different names to refer to components. This document does not intend to distinguish between components with different names but the same functions. In the following description and claims, the terms "including" and "including" are used in an open-ended manner, and therefore should be interpreted as meaning "including but not limited to...". Likewise, the term "coupled" is intended to mean an indirect or direct electrical connection. Therefore, if one device is coupled to another device, the connection may be through a direct electrical connection, or through an indirect electrical connection through the other device and connection.

第1圖是示出根據本發明實施例的關於借助於外部時鐘注入的晶體振盪器10(XO)的啟動(例如,快速啟動)的概念的示意圖。對於具有高品質因數的振盪器(可以稱為高Q振盪器),與雜訊(例如相位雜訊)相關的性能要比具有低品質因數的振盪器(可以稱為低Q振盪器)好得多,但高Q振盪器所需的啟動時間可能比低Q振盪器所需的啟動時間長得多。高Q振盪器的示例可以包括但不限於:Pierce XO和Colpitts XO。低Q振盪器的示例可以包括但不限於:環形(ring)振盪器和電阻電容(resistor-capacitor,RC)振盪器。第1圖中所示的快速啟動技術可以在時段TINJ期間接通耦接在低Q振盪器和高Q振盪器之間的注 入開關,並且將低Q振盪器的注入信號VINJ的能量注入高Q振盪器(例如,包括主動器件(active device)11(其中具有跨導(transconductance)Gm和負載電容器CL),電容器Cm和Co,電阻器Rm和電感Lm),從而在XO的啟動過程中增加了高Q振盪器的固有振盪信號(intrinsic oscillation signal)的能量(例如Vm,ss和Im,ss),以加速XO的啟動並允許XO輸出固有振盪信號。 FIG. 1 is a schematic diagram showing the concept of start (for example, fast start) of a crystal oscillator 10 (XO) injected by an external clock according to an embodiment of the present invention. For an oscillator with a high quality factor (which can be called a high-Q oscillator), the performance related to noise (such as phase noise) is better than an oscillator with a low quality factor (which can be called a low-Q oscillator) Many, but the startup time required for the high-Q oscillator may be much longer than the startup time required for the low-Q oscillator. Examples of high-Q oscillators may include, but are not limited to: Pierce XO and Colpitts XO. Examples of low-Q oscillators may include, but are not limited to: ring oscillators and resistor-capacitor (RC) oscillators. The quick start technique shown in Figure 1 can turn on the injection switch coupled between the low-Q oscillator and the high-Q oscillator during the period T INJ , and inject the energy of the injection signal V INJ of the low-Q oscillator into A high-Q oscillator (for example, includes an active device 11 (which has transconductance Gm and a load capacitor C L ), capacitors C m and C o , resistor R m and inductance L m ), so that The energy of the intrinsic oscillation signal (for example, V m, ss and Im, ss ) of the high-Q oscillator's intrinsic oscillation signal (for example, V m, ss and Im, ss) is increased during the startup of the XO to accelerate the startup of the XO and allow the XO to output the intrinsic oscillation signal.

實際上,在啟動過程開始時,低Q振盪器的注入頻率通常與高Q振盪器的固有頻率(intrinsic frequency)不同,例如±6000ppm(parts per million),因此注入信號和固有振盪信號之間的相位誤差可能會逐漸累積。在一些實施例中,第1圖中所示的快速啟動技術還可以利用回饋控制機制,該機制檢測固有頻率並相應地修改低Q振盪器,以使注入頻率接近固有頻率。詳細地,可以在第一注入時段期間接通注入開關,並且固有振盪信號的能量可以增加,其中,由於固有振盪信號在開始時不夠強,注入信號可以支配低Q振盪器和高Q振盪器的連接節點上的整體波形(例如,注入信號和固有振盪信號的組合)。為了檢測固有頻率(intrinsic frequency),然後在第一注入時段之後的鎖定/同步時段期間斷開注入開關,以允許檢測固有頻率以控制低Q振盪器。在注入頻率接近固有頻率之後,在鎖定/同步時段之後的第二注入時段期間注入開關再次接通,並且時鐘注入繼續進行。 In fact, at the beginning of the start-up process, the injection frequency of the low-Q oscillator is usually different from the intrinsic frequency of the high-Q oscillator, such as ±6000 ppm (parts per million), so there is a difference between the injection signal and the intrinsic oscillation signal. The phase error may gradually accumulate. In some embodiments, the quick start technique shown in Figure 1 can also utilize a feedback control mechanism that detects the natural frequency and modifies the low-Q oscillator accordingly to make the injection frequency close to the natural frequency. In detail, the injection switch can be turned on during the first injection period, and the energy of the natural oscillation signal can be increased, wherein, since the natural oscillation signal is not strong enough at the beginning, the injection signal can dominate the low-Q oscillator and the high-Q oscillator. The overall waveform on the connection node (for example, the combination of the injected signal and the natural oscillation signal). In order to detect the intrinsic frequency, the injection switch is then turned off during the lock/synchronization period after the first injection period to allow detection of the intrinsic frequency to control the low-Q oscillator. After the injection frequency approaches the natural frequency, the injection switch is turned on again during the second injection period after the lock/synchronization period, and the clock injection continues.

第2圖是示出根據本發明實施例的XO 20的示意圖。如第2圖所示,XO 20可以包括XO核心電路100,XO核心電路100的外部振盪器200(特別地,外部振盪器200位於XO核心電路100的外部),至少一個注入開關(例如一個或多個,其統稱為由信號INJEN控制的注入開關)和頻率控制器300,其中,注入開關耦接在XO 20的注入節點NINJ和XO核心電路的輸出端NOUT之間,外部振盪器耦接到注入節點NINJ,並且頻率控制器300耦接到外部振盪器200。在該實施例中,外部振盪器200的品質因數低於XO核心電路100的品質因數。其中,XO核心電路 100可以是高Q振盪器的示例,而外部振盪器200可以是低Q振盪器的示例。第3圖是示出根據本發明實施例的借助於外部時鐘注入的快速啟動第2圖中所示XO 20的方法的流程圖。應當注意的是,第3圖所示的工作流程僅出於說明性目的,而不是對本發明的限制。在第3圖所示的工作流程中,可以添加,刪除或修改一個或多個步驟。此外,如果可以獲得相同的結果,則不必按照第3圖所示的確切順序執行這些步驟。為了更好的理解,請結合第2圖參考第3圖。 Figure 2 is a schematic diagram showing an XO 20 according to an embodiment of the present invention. As shown in Figure 2, the XO 20 may include an XO core circuit 100, an external oscillator 200 of the XO core circuit 100 (in particular, the external oscillator 200 is located outside the XO core circuit 100), and at least one injection switch (such as one or Multiple, collectively referred to as the injection switch controlled by the signal INJ EN ) and the frequency controller 300, where the injection switch is coupled between the injection node N INJ of the XO 20 and the output terminal N OUT of the XO core circuit, and the external oscillator It is coupled to the injection node N INJ , and the frequency controller 300 is coupled to the external oscillator 200. In this embodiment, the quality factor of the external oscillator 200 is lower than the quality factor of the XO core circuit 100. Among them, the XO core circuit 100 may be an example of a high-Q oscillator, and the external oscillator 200 may be an example of a low-Q oscillator. Fig. 3 is a flowchart showing a method for quickly starting the XO 20 shown in Fig. 2 by means of external clock injection according to an embodiment of the present invention. It should be noted that the workflow shown in Figure 3 is for illustrative purposes only, and is not a limitation of the present invention. In the workflow shown in Figure 3, one or more steps can be added, deleted or modified. In addition, if the same results can be obtained, it is not necessary to perform these steps in the exact order shown in Figure 3. For a better understanding, please refer to Figure 3 in conjunction with Figure 2.

在步驟S310中,外部振盪器200可以在外部振盪器200內產生注入信號(例如,低Q信號)。在該實施例中,頻率控制器300的工作頻率由外部振盪器控制(例如,頻率控制器300的工作頻率可以等於注入信號的注入頻率),但是本發明不限於此。 In step S310, the external oscillator 200 may generate an injection signal (for example, a low-Q signal) in the external oscillator 200. In this embodiment, the operating frequency of the frequency controller 300 is controlled by an external oscillator (for example, the operating frequency of the frequency controller 300 may be equal to the injection frequency of the injection signal), but the present invention is not limited thereto.

在步驟S320中,包括XO 20的系統(例如,占空比無線/有線系統)可以利用信號INJEN接通注入開關,以使注入信號的能量注入XO核心電路100中,從而在XO 20的啟動過程中增加了XO核心電路100的固有振盪信號的能量(例如,諧振器的能量Im(t))。當注入開關被接通時,輸出端NOUT耦接到注入節點NINJ,注入信號和固有振盪信號都存在於注入節點NINJ處,並且根據注入信號和固有振盪信號的組合在注入節點NINJ上產生調幅(amplitude modulation,AM)信號。例如,注入信號(例如,輸出方波)可以被固有振盪信號調製以生成AM信號,如第4圖所示的信號VGATE(t)的波形所示。 In step S320, the system including the XO 20 (for example, the duty cycle wireless/wired system) may use the signal INJ EN to turn on the injection switch, so that the energy of the injected signal is injected into the XO core circuit 100, thereby starting the XO 20 In the process, the energy of the natural oscillation signal of the XO core circuit 100 (for example, the energy of the resonator Im(t)) is increased. When the injection switch is turned on, the output terminal N OUT is coupled to the injection node N INJ , the injection signal and the natural oscillation signal are both present at the injection node N INJ , and according to the combination of the injection signal and the natural oscillation signal at the injection node N INJ Amplitude modulation (AM) signal is generated on it. For example, the injection signal (for example, the output square wave) can be modulated by the natural oscillation signal to generate an AM signal, as shown in the waveform of the signal V GATE (t) shown in FIG. 4.

在步驟S330中,頻率控制器300可以接收AM信號並根據諸如信號VGATE(t)的波形的AM信號控制外部振盪器200來選擇性地改變注入信號的注入頻率。更具體地說,在啟動過程中,當外部振盪器選擇性的改變注入信號的注入頻率時,注入開關總是接通(例如,不關斷)或至少接通一段時間。 In step S330, the frequency controller 300 may receive the AM signal and control the external oscillator 200 according to the AM signal such as the waveform of the signal V GATE (t) to selectively change the injection frequency of the injection signal. More specifically, during the startup process, when the external oscillator selectively changes the injection frequency of the injection signal, the injection switch is always turned on (for example, not turned off) or at least turned on for a period of time.

應該注意的是,注入信號與固有振盪信號之間的不同相對相位(例如,相位誤差)可能導致第4圖所示信號VGATE(t)的不同波形模式,其中還示出了 XO核心電路100內的諧振器的能量Im(t)。例如,當注入頻率(例如FINJ)不等於固有頻率(例如FXO)時,相位誤差可能隨時間累積,並且可能出現跳動行為(beating behavior),其中可以計算出跳動行為的包絡週期Tenvelope如下:

Figure 110119928-A0305-02-0011-1
It should be noted that the different relative phase (for example, phase error) between the injected signal and the natural oscillation signal may result in different waveform patterns of the signal V GATE (t) shown in Figure 4, which also shows the XO core circuit 100 The energy of the internal resonator I m (t). For example, when the injection frequency (for example, F INJ ) is not equal to the natural frequency (for example, F XO ), the phase error may accumulate over time, and beating behavior may occur. The envelope period T envelope of the beating behavior can be calculated as follows :
Figure 110119928-A0305-02-0011-1

△f可以表示注入頻率與固有頻率之間的頻率差。在該實施例中,信號VGATE(t)的波形可以被認為是來自外部振盪器200的方波被來自XO核心電路100的固有振盪信號(可以由Im(t)表示)失真,並且不同的失真(例如,跳動的包絡線)可能對應於注入信號和固有振盪信號之間的不同相對相位。因此,與注入信號和固有振盪信號之間的相對相位有關的資訊由諸如信號VGATE(t)的AM信號攜帶。 Δf can represent the frequency difference between the injection frequency and the natural frequency. In this embodiment, the waveform of the signal V GATE (t) can be considered to be that the square wave from the external oscillator 200 is distorted by the natural oscillation signal (which can be represented by I m (t)) from the XO core circuit 100, and is different The distortion (for example, the jittery envelope) may correspond to different relative phases between the injected signal and the natural oscillation signal. Therefore, information about the relative phase between the injected signal and the natural oscillation signal is carried by the AM signal such as the signal V GATE (t).

第5圖示出了根據本發明實施例的固有振盪信號的增長率與相對相位之間的關係。如第5圖所示,當相對相位落在+90度與-90度之間的間隔中時,回應於外部時鐘注入,固有振盪信號的增長率可能為正。當相對相位落在此間隔之外(例如,相對相位>+90°或相對相位<-90°)時,回應於外部時鐘注入,增長率可能為負,這意味著當相對相位落在+90°和-90°之間的間隔之外時,低Q振盪器會阻礙XO的啟動。 Figure 5 shows the relationship between the growth rate of the natural oscillation signal and the relative phase according to an embodiment of the present invention. As shown in Figure 5, when the relative phase falls in the interval between +90 degrees and -90 degrees, the growth rate of the natural oscillation signal may be positive in response to the external clock injection. When the relative phase falls outside this interval (for example, relative phase>+90° or relative phase<-90°), the growth rate may be negative in response to external clock injection, which means that when the relative phase falls at +90 Outside the interval between ° and -90°, the low-Q oscillator will prevent the XO from starting.

基於此,在第2圖所示的實施例中,在啟用XO 20的啟動過程之後(例如,在接通注入開關之後),注入開關不會斷開直到啟動過程完成。雖然本發明在所需要的鎖定/同步時段內不中斷XO 20的時鐘注入,但是可以根據失真從信號VGATE中提取與相對相位有關的資訊,以控制注入頻率。另外,頻率控制器300可以利用控制機制來確保相對相位總是落在+90°和-90°之間的間隔中,從而防止注入信號阻礙啟動過程。因此,提高了時鐘注入的效率,並且可以大大減少啟動時間。 Based on this, in the embodiment shown in FIG. 2, after the startup process of the XO 20 is enabled (for example, after the injection switch is turned on), the injection switch will not be turned off until the startup process is completed. Although the present invention does not interrupt the clock injection of the XO 20 during the required lock/synchronization period, the information related to the relative phase can be extracted from the signal V GATE according to the distortion to control the injection frequency. In addition, the frequency controller 300 can use a control mechanism to ensure that the relative phase always falls within the interval between +90° and -90°, thereby preventing the injection signal from hindering the startup process. Therefore, the efficiency of clock injection is improved, and the startup time can be greatly reduced.

在一個實施例中,第2圖中所示的頻率控制器300可以包括:解調電路,其中該解調電路可以被配置為接收AM信號並根據該AM信號生成解調電壓序列。第6圖是示出根據本發明實施例的通過解調電路310生成解調電壓序列的詳細實施方式的示意圖,其中,解調電路310可以是上述解調電路的示例。在該實施例中,第2圖中所示的外部振盪器200可以包括第6圖中所示的低Q振盪器210(例如,環形振盪器或RC振盪器)和至少一個輸出緩衝器(例如,一個或多個輸出緩衝器,其統稱為輸出緩衝器220),其中緩衝器220可以耦接在低Q振盪器210和注入節點NINJ之間。在一些實施例中,可以省略緩衝器220。 In an embodiment, the frequency controller 300 shown in Figure 2 may include a demodulation circuit, where the demodulation circuit may be configured to receive an AM signal and generate a demodulation voltage sequence based on the AM signal. FIG. 6 is a schematic diagram showing a detailed implementation manner of generating a demodulated voltage sequence by the demodulation circuit 310 according to an embodiment of the present invention, where the demodulation circuit 310 may be an example of the above-mentioned demodulation circuit. In this embodiment, the external oscillator 200 shown in FIG. 2 may include the low-Q oscillator 210 shown in FIG. 6 (for example, a ring oscillator or an RC oscillator) and at least one output buffer (for example, , One or more output buffers, which are collectively referred to as the output buffer 220), wherein the buffer 220 may be coupled between the low-Q oscillator 210 and the injection node N INJ . In some embodiments, the buffer 220 may be omitted.

在該實施例中,可以通過使用具有採樣和保持機制的二極體來實現解調電路310,如第6圖所示,從諸如信號VGATE(t)的AM信號中提取與相對相位有關的資訊(例如,跳動包絡)。詳細地,解調電路310可以包括二極體D0,由信號RST控制的重置(reset)開關,由信號RSTB控制的採樣開關和採樣電容器CS,其中,二極體D0的陰極(cathode)耦接至解調電路310的採樣節點。在解調電路310中,重置開關耦接在採樣節點與解調電路310的參考端(例如地電壓端)之間,採樣開關耦接在二極體D0的陽極(anode)與注入節點NINJ之間(或在其他實施例中,其耦接在二極體D0的陽極與XO核心電路100的輸出端NOUT之間),以及採樣電容器CS耦接在採樣節點與參考端之間。例如,在解調電路310的重置時段(reset period),當重置開關為接通(turned on)而採樣開關為斷開(turned off)時,採樣節點的電壓電平被重置為參考端的參考電平。當在採樣時段中重置開關斷開並且採樣開關接通時,回應於AM信號的電壓電平超過對應於二極體D0的閾值,電荷在採樣節點上累積(例如,回應於信號VGATE(t)的電壓電平使二極體D0的陰極和陽極之間的電壓差大於二極體D0的閾值電壓),以在採樣節點上生成解調電壓序列中的解調電壓。解調電路310的操作類似於積分器,因此與失真有關的資訊可以對應於解調電壓序列,其中解調電壓序列可以由信號VDe-MOD 表示。注意,通過相同的二極體(即,二極體D0)產生解調電壓序列中的每個解調電壓,並且在解調電壓序列中不引入失配問題。 In this embodiment, the demodulation circuit 310 can be realized by using a diode with a sample and hold mechanism. As shown in Figure 6, the AM signal such as the signal V GATE (t) is extracted from the AM signal related to the relative phase. Information (for example, the jitter envelope). In detail, the demodulation circuit 310 may include a diode D0, a switch controlled by the reset signal RST (RESET), controlled by the signal RSTB sampling switch and a sampling capacitor C S, wherein the cathode of the diode D0 body (Cathode) It is coupled to the sampling node of the demodulation circuit 310. In the demodulation circuit 310, the reset switch is coupled between the sampling node and the reference terminal (for example, the ground voltage terminal) of the demodulation circuit 310, and the sampling switch is coupled between the anode of the diode D0 and the injection node N. between the INJ (or in other embodiments, coupled between the anode and the XO diode D0 core circuit output terminal 100 of the N OUT), and a sampling capacitor C S is coupled between the sampling node and the reference terminal . For example, in the reset period of the demodulation circuit 310, when the reset switch is turned on and the sampling switch is turned off, the voltage level of the sampling node is reset to the reference The reference level of the terminal. When the reset switch is turned off and the sampling switch is turned on during the sampling period, in response to the voltage level of the AM signal exceeding the threshold corresponding to the diode D0, the charge is accumulated on the sampling node (for example, in response to the signal V GATE ( The voltage level of t) makes the voltage difference between the cathode and anode of the diode D0 greater than the threshold voltage of the diode D0) to generate the demodulated voltage in the demodulated voltage sequence on the sampling node. The operation of the demodulation circuit 310 is similar to an integrator, so the information related to distortion can correspond to a demodulated voltage sequence, where the demodulated voltage sequence can be represented by the signal V De-MOD . Note that each demodulated voltage in the demodulated voltage sequence is generated by the same diode (ie, the diode D0), and no mismatch problem is introduced in the demodulated voltage sequence.

第7圖示出了根據本發明實施例的相對相位和失真(例如,跳動包絡)之間的關係的一些細節。為了更好地理解,假設諸如信號VXO的固有振盪信號的能量(例如信號VXO的幅度)不變。具有不同的相對相位Ø的跳動包絡可以如下計算:

Figure 110119928-A0305-02-0013-2
Figure 7 shows some details of the relationship between relative phase and distortion (e.g., jitter envelope) according to an embodiment of the present invention. For a better understanding, it is assumed that the energy of a natural oscillation signal such as the signal V XO (for example, the amplitude of the signal V XO) does not change. The jitter envelope with different relative phase Ø can be calculated as follows:
Figure 110119928-A0305-02-0013-2

根據此等式,當Ø分別為-90°,-45°,0°,+45°和90°時,由Env1(Ø)表示的跳動包絡可以為0,-

Figure 110119928-A0305-02-0013-31
A 0,-2A 0,-
Figure 110119928-A0305-02-0013-30
A 0和0,其中A0可以代表信號VXO的幅度。基於此,導致跳動包絡Env1(Ø)最小的相對相位Ø min 可以是0°。因此,如第8圖所示,當相對相位Ø=Ø min =0°時,諸如信號VDe-MOD的解調電壓序列可以具有最小電壓。 According to this equation, when Ø is -90°, -45°, 0°, +45° and 90°, respectively, the jitter envelope represented by Env1(Ø) can be 0,-
Figure 110119928-A0305-02-0013-31
A 0 ,-2 A 0 ,-
Figure 110119928-A0305-02-0013-30
A 0 and 0, where A 0 can represent the amplitude of the signal V XO. Based on this, the relative phase Ø min that causes the minimum jitter envelope Env1(Ø) can be 0°. Therefore, as shown in Fig. 8, when the relative phase Ø=Ø min =0°, the demodulated voltage sequence such as the signal V De-MOD can have the minimum voltage.

實際上,如第9圖所示,諸如信號VXO的固有振盪信號的能量(例如,信號VXO的幅度)可能隨時間增長。具有不同相對相位Ø的跳動包絡可作如下修改:

Figure 110119928-A0305-02-0013-6
In fact, as shown in Figure 9, the energy of a natural oscillation signal such as the signal V XO (for example, the amplitude of the signal V XO ) may increase over time. The jitter envelope with different relative phase Ø can be modified as follows:
Figure 110119928-A0305-02-0013-6

具有信號VXO幅度增大的跳動包絡可以由Env1(Ø)表示。根據此等式,當Ø分別為-90°,-45°,0°,+45°和+90°時,跳動包絡Env1(Ø)可以為0,-

Figure 110119928-A0305-02-0013-28
[A 0+kØ],-2[A 0+kØ],-
Figure 110119928-A0305-02-0013-29
[A 0+kØ]和0,其中k可以代表信號VXO幅度的增長率。基於此,當相對相位Ø在正方向上累積時,當A0和k為正值時,導致跳動包絡Env1(Ø)最小的相對相位Ø min 可能落在0°至90°之間的間隔內。因此,如第10圖所示,當Ø=Ø min 時,諸如信號VDe-MOD的解調電壓序列可以具有最小電 壓。類似地,當相對相位Ø在負方向上累積時,當A0和k為正值時,導致跳動包絡Env1(Ø)最小的相對相位Ø min 可能落在0°至-90°之間的間隔內。根據以上描述,可以知道,導致出現了解調電壓序列中的最小電壓(更具體地,局部最小電壓)出現的注入信號與固有振盪信號之間的相對相位,落入+90°和-90°之間的間隔。其中,局部最小電壓可以是在解調電壓序列中解調電壓降低的變化趨勢出現反轉時的電壓。 The jitter envelope with the increased amplitude of the signal V XO can be represented by Env1 (Ø). According to this equation, when Ø is -90°, -45°, 0°, +45° and +90°, the jitter envelope Env1(Ø) can be 0,-
Figure 110119928-A0305-02-0013-28
[ A 0 + k Ø],-2[ A 0 + k Ø],-
Figure 110119928-A0305-02-0013-29
[ A 0 + k Ø] and 0, where k can represent the growth rate of the signal V XO amplitude. Based on this, when the relative phase Ø accumulates in the positive direction, when A 0 and k are positive values, the relative phase Ø min that causes the jitter envelope Env1 (Ø) to be the smallest may fall within the interval between 0° and 90°. Therefore, as shown in FIG. 10, when Ø = Ø min, such as demodulation sequence voltage signal V De-MOD may have a minimum voltage. Similarly, when the relative phase Ø accumulates in the negative direction, when A 0 and k are positive values, the relative phase Ø min that causes the jitter envelope Env1 (Ø) to be the smallest may fall in the interval between 0° and -90° Inside. According to the above description, it can be known that the relative phase between the injection signal and the natural oscillation signal that caused the minimum voltage (more specifically, the local minimum voltage) in the demodulated voltage sequence to appear falls between +90° and -90° The interval between. Wherein, the local minimum voltage may be the voltage when the change trend of the demodulation voltage decrease in the demodulation voltage sequence is reversed.

第11圖是示出根據本發明實施例的XO 20的詳細實施方式的示意圖。注意,在啟動過程中注入開關接通,為簡潔起見在第11圖中被省略。除了第6圖所示的解調電路310之外,第3圖中所示的頻率控制器300可以進一步包括:耦接到解調電路的監視電路320,以及耦接到監視電路320和外部振盪器200(例如,低Q振盪器210)的有限狀態機(finite state machine,FSM)330(具有計數器的FSM)。在該實施例中,FSM 330可以利用注入的信號作為用於FSM的計數時鐘(例如,CLKcounting),但是本發明不限於此。在該實施例中,監視電路320可以被配置為根據解調電壓序列來生成監視結果,並且FSM 330可以被配置為通過信號Vcontrol來控制外部振盪器200(例如,低Q振盪器210),以便根據監視結果選擇性的改變注入頻率,以確保相對相位落在+90度和-90度之間的間隔中。在第11圖的實施例中,監視電路320可以包括放大器AMPCOMP,電容器CCOMP和由信號LOOPEN控制的回路開關,其中,放大器AMPCOMP的第一輸入端(在第11圖所示的放大器AMPCOMP上標記為“+”)可以耦接到解調電路310(例如其中的採樣節點),電容器CCOMP可以耦接在參考端和放大器AMPCOMP的第二輸入端(在第11圖中示出的放大器AMPCOMP上標記為“-”)之間,並且回路開關可以耦接在放大器AMPCOMP的第二輸入端和輸出端之間。在該實施例中,由信號LOOPEN控制的D觸發器(D flip-flop,DFF)322可以被包括在監視電路320中,其中DFF耦接在放大器AMPCOMP的輸出端和FSM 330之間,以使FSM 330僅接收 數字結果,但是本發明不限於此。 FIG. 11 is a schematic diagram showing a detailed implementation of the XO 20 according to an embodiment of the present invention. Note that the injection switch is turned on during the startup process, which is omitted in Figure 11 for brevity. In addition to the demodulation circuit 310 shown in FIG. 6, the frequency controller 300 shown in FIG. 3 may further include: a monitoring circuit 320 coupled to the demodulation circuit, and coupled to the monitoring circuit 320 and an external oscillator The finite state machine (FSM) 330 (FSM with counter) of the device 200 (for example, the low-Q oscillator 210). In this embodiment, the FSM 330 can use the injected signal as a counting clock (for example, CLK counting ) for the FSM, but the present invention is not limited to this. In this embodiment, the monitoring circuit 320 may be configured to generate a monitoring result according to the demodulated voltage sequence, and the FSM 330 may be configured to control the external oscillator 200 (for example, the low-Q oscillator 210) through the signal V control, In order to selectively change the injection frequency according to the monitoring result, to ensure that the relative phase falls within the interval between +90 degrees and -90 degrees. In the embodiment of FIG. 11, the monitoring circuit 320 may include an amplifier AMP COMP , a capacitor C COMP and a loop switch controlled by a signal LOOP EN , wherein the first input terminal of the amplifier AMP COMP (in the amplifier shown in FIG. 11 AMP COMP marked as "+") can be coupled to the demodulation circuit 310 (for example, the sampling node therein), and the capacitor C COMP can be coupled to the reference terminal and the second input terminal of the amplifier AMP COMP (shown in Figure 11). The output amplifier AMP COMP is marked as "-"), and the loop switch can be coupled between the second input terminal and the output terminal of the amplifier AMP COMP. In this embodiment, a D flip-flop (DFF) 322 controlled by the signal LOOP EN may be included in the monitoring circuit 320, where the DFF is coupled between the output terminal of the amplifier AMP COMP and the FSM 330, So that the FSM 330 only receives digital results, but the present invention is not limited to this.

詳細地,放大器AMPCOMP可以被配置為通過其第一輸入端接收解調電壓序列,電容器CCOMP可以被配置為順序存儲解調電壓序列,並且回路開關被配置為控制監視電路320的配置。為了更好地理解,請參考第12圖和第13圖,其中,第12圖示出了在預設置階段第11圖所示的監視電路320的操作。第13圖示出了在評估階段第11圖所示的監視電路320的操作。在監視電路320的預設置階段期間,回路開關被接通,監視電路320被配置為單位增益緩衝器,以從放大器AMPCOMP的第一輸入端到電容器CCOMP(例如,放大器AMPCOMP的第二輸入端)傳輸解調電壓序列內的第一解調電壓。在評估階段,將回路開關斷開,將監視電路320配置為比較器,以將放大器AMPCOMP的第一輸入端上的第二解調電壓與電容器上存儲的第一解調電壓(放大器AMPCOMP的第二輸入端上的)進行比較,並產生比較結果,其中,監視結果包括比較結果。以此類推,可以生成解調電壓序列的連續比較結果,其中這些連續比較結果可以表示監視結果。 In detail, the amplifier AMP COMP may be configured to receive the demodulated voltage sequence through its first input terminal, the capacitor C COMP may be configured to sequentially store the demodulated voltage sequence, and the loop switch may be configured to control the configuration of the monitoring circuit 320. For a better understanding, please refer to Figs. 12 and 13, where Fig. 12 shows the operation of the monitoring circuit 320 shown in Fig. 11 in the pre-setting stage. Figure 13 shows the operation of the monitoring circuit 320 shown in Figure 11 during the evaluation phase. During the preset phase of the monitoring circuit 320, the loop switch is turned on, and the monitoring circuit 320 is configured as a unity gain buffer to go from the first input terminal of the amplifier AMP COMP to the capacitor C COMP (for example, the second input terminal of the amplifier AMP COMP). The input terminal) transmits the first demodulated voltage in the demodulated voltage sequence. In the evaluation phase, the loop switch is turned off, and the monitoring circuit 320 is configured as a comparator to compare the second demodulated voltage on the first input terminal of the amplifier AMP COMP with the first demodulated voltage stored on the capacitor (amplifier AMP COMP On the second input terminal of) to compare and generate a comparison result, where the monitoring result includes the comparison result. By analogy, continuous comparison results of the demodulated voltage sequence can be generated, where these continuous comparison results can represent monitoring results.

假設監視電路320的比較結果為“0”表示解調電壓序列內兩個連續解調電壓的先前的解調電壓(例如,上述的第一解調電壓)大於解調電壓序列內這兩個連續解調電壓的後面的解調電壓(例如上述的第二解調電壓),並且監視電路320的比較結果為“1”指示這兩個連續解調電壓中的先前的解調電壓小於後面的解調電壓。因此,當比較結果從“0”變為“1”時,意味著檢測到解調電壓序列的局部最小值。 Assuming that the comparison result of the monitoring circuit 320 is "0", it means that the previous demodulated voltage of the two consecutive demodulated voltages in the demodulated voltage sequence (for example, the aforementioned first demodulated voltage) is greater than the two consecutive demodulated voltages in the demodulated voltage sequence. The demodulated voltage after the demodulated voltage (for example, the above-mentioned second demodulated voltage), and the comparison result of the monitoring circuit 320 is "1", which indicates that the previous demodulated voltage of the two consecutive demodulated voltages is smaller than the subsequent demodulated voltage. Adjust the voltage. Therefore, when the comparison result changes from "0" to "1", it means that the local minimum of the demodulated voltage sequence is detected.

實際上,可能存在由放大器AMPCOMP的第一輸入端和第二輸入端的不匹配引起的固有偏移VOS。基於第12圖和第13圖所示的操作,可以從比較結果中去除來自固有偏移VOS的影響。例如,當在預設置階段將第一解調電壓(可以由“V[n]”表示)從放大器AMPCOMP的第一輸入端傳輸到放大器AMPCOMP的第二輸入端時,固有偏移量VOS可以與第一電壓一起存儲在電容器CCOMP上,因此電 容器CCOMP可以存儲電壓V[n]-VOS;在評估階段,第二解調電壓(可以由V[n+1]表示)可以與固有偏移VOS一起存在於放大器AMPCOMP的第一端上。由於放大器AMPCOMP的第一輸入端和第二輸入端在各自端上都具有固有偏移,因此比較結果(例如,第13圖所示的ADRESULT)將不受固有偏移的影響。 In fact, there may be an inherent offset V OS caused by a mismatch between the first input terminal and the second input terminal of the amplifier AMP COMP . Based on the operations shown in Figs. 12 and 13, the influence from the inherent offset V OS can be removed from the comparison result. For example, when the first demodulated voltage (may be represented by "V [n]") is provided in the pre-stage of the transmission from the first input terminal of the amplifier AMP COMP to a second input of the amplifier AMP COMP, and the specific offset V OS can be stored on the capacitor C COMP together with the first voltage, so the capacitor C COMP can store the voltage V[n]-V OS ; in the evaluation phase, the second demodulated voltage (which can be represented by V[n+1]) can be It is present on the first end of the amplifier AMP COMP together with the inherent offset V OS. Since the first input terminal and the second input terminal of the amplifier AMP COMP have inherent offsets at their respective ends, the comparison result (for example, AD RESULT shown in Fig. 13) will not be affected by the inherent offset.

應當注意,監視電路320不限於在第11圖中所示的XO 20中使用。任何需要連續比較操作的系統(例如,生成關於資料(或者電壓)序列內相鄰資料(或電壓)的比較結果)可以由監視電路320實施。 It should be noted that the monitoring circuit 320 is not limited to use in the XO 20 shown in FIG. 11. Any system that requires continuous comparison operations (for example, generating a comparison result about adjacent data (or voltage) in the data (or voltage) sequence) can be implemented by the monitoring circuit 320.

在另一個實施例中,解調電路310中的二極體D0可以用如第14圖所示的電晶體M0(例如N型電晶體)代替,其中電晶體M0的閘極端耦接到電晶體M0的漏極端,以使電晶體起二極體的作用,但是本發明不限於此。注意,在啟動過程中注入開關接通,並且在第11圖中為簡潔起見而被省略。 In another embodiment, the diode D0 in the demodulation circuit 310 can be replaced with a transistor M0 (for example, an N-type transistor) as shown in FIG. 14, wherein the gate terminal of the transistor M0 is coupled to the transistor The drain terminal of M0 enables the transistor to act as a diode, but the present invention is not limited to this. Note that the injection switch is turned on during startup and is omitted in Figure 11 for brevity.

在另一個實施例中,監視電路320可以被監視電路320A代替,如第15圖中示出的XO 30所示,其中監視電路320A可以包括比較器COMP,由信號SH控制的第一採樣開關,由信號SHB控制的第二採樣開關,第一採樣電容器C1和第二採樣電容器C2。注意,在啟動過程中注入開關是接通的,並且為簡潔起見在第11圖中被省略。如第15圖所示,第一採樣開關和第一採樣電容器C1形成第一採樣和保持電路,該第一採樣和保持電路耦接到比較器COMP的第一輸入端子(在比較器COMP上標記為“+”),第二採樣開關和第二採樣電容器C2形成第二採樣和保持電路,該第二採樣和保持電路耦接到比較器COMP的第二輸入端(在比較器COMP上標記為“-”),其中信號VA和VB表示比較器COMP的第一輸入端和第二輸入端上的電壓。 In another embodiment, the monitoring circuit 320 can be replaced by a monitoring circuit 320A, as shown in XO 30 shown in Figure 15, where the monitoring circuit 320A can include a comparator COMP, a first sampling switch controlled by the signal SH, The second sampling switch controlled by the signal SHB, the first sampling capacitor C 1 and the second sampling capacitor C 2 . Note that the injection switch is turned on during the startup process and is omitted in Figure 11 for brevity. As shown in FIG. 15, a first sample switch and the first sampling capacitors C 1 forming a first sample and hold circuit, the first sample and hold circuit coupled to the first input terminal of the comparator COMP (comparator COMP in the Marked as "+"), the second sampling switch and the second sampling capacitor C 2 form a second sampling and holding circuit, which is coupled to the second input terminal of the comparator COMP (on the comparator COMP (Marked as "-"), where the signals VA and VB represent the voltages on the first input terminal and the second input terminal of the comparator COMP.

第16圖是根據本發明實施例示出的第15圖所示的XO 20內的一些信號(例如,計數時鐘CLKcounting,信號RST,RSTB,SH,SHB以及信號VA和VB)的時序圖。在本實施例中,信號RST,RSTB,SH和SHB可以由定時控制器(timing controller)(未示出)根據計數時鐘CLKcounting產生,但是本發明不限於此。根據第16圖所示的時序,可以交替/輪流的在採樣電容器C1和C2上對解調電壓序列的解調電壓進行採樣,並且可以從比較器COMP輸出解調電壓序列的相應監視結果。例如,採樣電容器C1對第一解調電壓進行採樣,採樣電容器C2對第二解調電壓進行採樣,採樣電容器C1對第三解調電壓進行採樣,採樣電容器C2對第四解調電壓進行採樣。 FIG. 16 is a timing diagram of some signals (for example, the counting clock CLK counting , the signals RST, RSTB, SH, SHB, and the signals VA and VB) in the XO 20 shown in FIG. 15 according to an embodiment of the present invention. In this embodiment, the signals RST, RSTB, SH and SHB may be generated by a timing controller (not shown) according to the counting clock CLKcounting, but the present invention is not limited to this. According to the timing shown in Figure 16, the demodulated voltage of the demodulated voltage sequence can be sampled alternately/in turn on the sampling capacitors C1 and C2, and the corresponding monitoring result of the demodulated voltage sequence can be output from the comparator COMP. For example, the sampling capacitor C1 samples the first demodulation voltage, the sampling capacitor C2 samples the second demodulation voltage, the sampling capacitor C1 samples the third demodulation voltage, and the sampling capacitor C2 samples the fourth demodulation voltage.

在另一實施例中,如第17圖中的XO 40所示,可以將監視電路320替換為模數轉換器(analog-to-digital converter,ADC)320B。請注意,在啟動過程中注入開關接通,並且為了簡潔起見在第17圖中被省略。例如,ADC 320B可以順序地將解調電壓序列轉換成數位代碼,其中這些數位代碼可以表示前述的監視結果,並且FSM 330可以控制低Q振盪器210根據這些數位代碼來選擇性地改變注入頻率。 In another embodiment, as shown by XO 40 in Figure 17, the monitoring circuit 320 can be replaced with an analog-to-digital converter (ADC) 320B. Please note that the injection switch is turned on during startup and is omitted in Figure 17 for the sake of brevity. For example, the ADC 320B can sequentially convert the demodulated voltage sequence into digital codes, where these digital codes can represent the aforementioned monitoring results, and the FSM 330 can control the low-Q oscillator 210 to selectively change the injection frequency according to these digital codes.

第18圖示出了根據本發明實施例的與注入頻率的控制有關的一些細節。如第18圖中所示,FSM 330可以根據監視結果控制外部振盪器(例如,低Q振盪器210)將注入頻率交替/輪流地切換到多個候選頻率中的一個或多個目標頻率,以使注入頻率逐步(stepwise)接近固有振盪信號的固有頻率,其中多個候選頻率分別對應於FSM 330的多個狀態。在該實施例中,假設固有頻率(可以被認為是目標頻率)等於多個候選頻率中的中心頻率(例如,相對於中心頻率具有0ppm的頻率誤差)。當注入頻率最初處於第一頻率時,該第一頻率相對於多個候選頻率中的中心頻率具有-5000ppm的頻率誤差,固有振盪信號和注入信號之間的相對相位(例如相位誤差)可以開始在正方向上累積,其中,固有振盪信號的能量在增加,而解調電壓序列(例如信號VDe-MOD)的電平在降低,因此,監視電路320的比較結果在開始時保持為“0”。當監視結果表明在時間點t1處後面的解調電壓大於先前的解調電壓時(例如,來自監視電路320的比較結果從“0” 變為“1”),這意味著檢測到解調電壓序列的局部最小電壓(例如,信號VDe-MOD),其中,FSM 330可以確定小於第一頻率的候選頻率不可用,並控制外部振盪器200(例如,低Q振盪器)將注入頻率從第一頻率切換到第二頻率,該第二頻率相對於中心頻率具有+5000ppm的頻率誤差,然後比較結果返回到“0”。類似地,當監視結果指示比較結果在時間點t2從“0”變為“1”時,FSM 330可以確定大於第二頻率的候選頻率不可用,並控制外部振盪器200(例如低Q振盪器)將注入頻率從第二頻率切換到第三頻率,該第三頻率相對於中心頻率具有-4000ppm頻率誤差。以此類推,注入頻率可以分別在時間點t3,t4,t5和t6切換到第四頻率,第五頻率,第六頻率和第七頻率。為簡潔起見,在此不再重複類似的描述。據此,每當解調電壓序列內的解調電壓達到最小值時,就可以適當地調整注入頻率,使得相對相位可以在交替的方向上累積,從而確保相對相位被限制在±90°以內,(通常在±40°或更小範圍內),因此固有振盪信號的能量始終會增加。 Figure 18 shows some details related to the control of the injection frequency according to an embodiment of the present invention. As shown in Figure 18, the FSM 330 can control the external oscillator (for example, the low-Q oscillator 210) to switch the injection frequency alternately/in turn to one or more target frequencies among the multiple candidate frequencies according to the monitoring result. The injection frequency is stepwise approached to the natural frequency of the natural oscillation signal, wherein multiple candidate frequencies respectively correspond to multiple states of the FSM 330. In this embodiment, it is assumed that the natural frequency (which can be regarded as the target frequency) is equal to the center frequency of the plurality of candidate frequencies (for example, has a frequency error of 0 ppm with respect to the center frequency). When the injection frequency is initially at the first frequency, the first frequency has a frequency error of -5000ppm relative to the center frequency of the multiple candidate frequencies, and the relative phase (for example, phase error) between the natural oscillation signal and the injection signal can start at In the positive direction, the energy of the natural oscillation signal is increasing, while the level of the demodulation voltage sequence (for example, the signal V De-MOD ) is decreasing. Therefore, the comparison result of the monitoring circuit 320 remains "0" at the beginning. When the monitoring result indicates that the subsequent demodulated voltage at time point t1 is greater than the previous demodulated voltage (for example, the comparison result from the monitoring circuit 320 changes from "0" to "1"), it means that the demodulated voltage is detected The local minimum voltage of the sequence (for example, the signal V De-MOD ), where the FSM 330 may determine that a candidate frequency less than the first frequency is not available, and control the external oscillator 200 (for example, a low-Q oscillator) to inject the frequency from the first frequency One frequency is switched to a second frequency, which has a frequency error of +5000 ppm relative to the center frequency, and then the comparison result returns to "0". Similarly, when the monitoring result indicates that the comparison result changes from "0" to "1" at time t2, the FSM 330 may determine that a candidate frequency greater than the second frequency is not available, and control the external oscillator 200 (for example, a low-Q oscillator ) Switch the injection frequency from the second frequency to the third frequency, which has a frequency error of -4000 ppm relative to the center frequency. By analogy, the injection frequency can be switched to the fourth frequency, the fifth frequency, the sixth frequency, and the seventh frequency at the time points t3, t4, t5, and t6, respectively. For the sake of brevity, similar descriptions are not repeated here. Accordingly, whenever the demodulated voltage in the demodulated voltage sequence reaches the minimum value, the injection frequency can be appropriately adjusted so that the relative phase can be accumulated in alternating directions, thereby ensuring that the relative phase is limited to within ±90°, (Usually in the range of ±40° or less), so the energy of the natural oscillation signal will always increase.

第19圖示出了根據本發明另一實施例的與注入頻率的控制有關的一些細節。在該實施例中,假設固有頻率(可以被認為是目標頻率)相對於中心頻率具有+4500ppm的頻率誤差。如第19圖所示,監視結果指示比較結果在時間點t7從“0”變為“1”(即,解調電壓V1小於解調電壓V2),FSM 330可以確定小於該第三頻率(具有-4000ppm頻率誤差)的候選頻率不可用,並且控制外部振盪器200(例如低Q振盪器)以將注入頻率從第三頻率切換為相對於中心頻率具有+4000ppm頻率誤差的第四頻率。然而,因為解調電壓V3大於解調電壓V2,比較結果在時間點t8仍保持為“1”,這意味著從第三頻率到第四頻率的切換無法改變相對相位的累加方向。因此,FSM 330可以控制外部振盪器200(例如,低Q振盪器)進一步將注入頻率從第四頻率切換到大於第四頻率(具有+4000ppm頻率誤差)的第八頻率(具有+4500ppm頻率誤差),以改變相對相位的累積方向。類似地,如果在注入頻率從第九頻率切換到小於第九頻率的第十頻率之後 比較結果仍保持在“1”,則FSM 330可以控制外部振盪器200(例如,低Q振盪器)進一步將注入頻率從第十頻率切換到小於第十頻率的第十一頻率。 Figure 19 shows some details related to the control of the injection frequency according to another embodiment of the present invention. In this embodiment, it is assumed that the natural frequency (which can be regarded as the target frequency) has a frequency error of +4500 ppm with respect to the center frequency. As shown in Figure 19, the monitoring result indicates that the comparison result changes from "0" to "1" at time t7 (ie, the demodulated voltage V1 is less than the demodulated voltage V2), and the FSM 330 can determine that the third frequency is less than the third frequency (having The candidate frequency of -4000ppm frequency error) is not available, and the external oscillator 200 (for example, a low-Q oscillator) is controlled to switch the injection frequency from the third frequency to the fourth frequency with +4000ppm frequency error relative to the center frequency. However, because the demodulated voltage V3 is greater than the demodulated voltage V2, the comparison result remains "1" at the time point t8, which means that the switching from the third frequency to the fourth frequency cannot change the accumulation direction of the relative phase. Therefore, the FSM 330 can control the external oscillator 200 (for example, a low-Q oscillator) to further switch the injection frequency from the fourth frequency to the eighth frequency (with +4500ppm frequency error) greater than the fourth frequency (with +4000ppm frequency error) , To change the accumulation direction of the relative phase. Similarly, if after the injection frequency is switched from the ninth frequency to the tenth frequency which is less than the ninth frequency The comparison result remains at "1", the FSM 330 may control the external oscillator 200 (for example, a low-Q oscillator) to further switch the injection frequency from the tenth frequency to the eleventh frequency which is less than the tenth frequency.

在一些實施例中,根據監視結果,FSM 330可以控制外部振盪器200(例如,低Q振盪器210)將注入頻率交替地切換到第一候選頻率(例如,第一頻率具有-5000ppm頻率誤差)或第二候選頻率(例如,第二頻率具有+5000ppm的頻率誤差)。注意,第一頻率大於固有振盪信號的固有頻率,並且第二頻率小於固有頻率,因此,在第一候選頻率和第二候選頻率之間的每次切換確實能夠改變相對相位的累積方向。因此,相對相位仍然可以被限制在±90°以內,並且可以確保在啟動過程期間僅借助於兩個候選頻率固有振盪信號的能量一直增加。 In some embodiments, according to the monitoring result, the FSM 330 may control the external oscillator 200 (for example, the low-Q oscillator 210) to alternately switch the injection frequency to the first candidate frequency (for example, the first frequency has a frequency error of -5000ppm) Or the second candidate frequency (for example, the second frequency has a frequency error of +5000 ppm). Note that the first frequency is greater than the natural frequency of the natural oscillation signal, and the second frequency is less than the natural frequency. Therefore, each switch between the first candidate frequency and the second candidate frequency can indeed change the cumulative direction of the relative phase. Therefore, the relative phase can still be limited to within ±90°, and it can be ensured that the energy of the natural oscillation signal with only the two candidate frequencies is always increased during the start-up process.

在一些實施例中,可以接通注入開關預定時間段。即,可以預先確定斷開注入開關的時間點(或完成啟動過程的時間)。在其他實施例中,包括XO 20的系統可以監視XO 20內的至少一個信號,以響應於上述至少一個信號滿足特定條件來觸發系統完成啟動過程(例如,斷開注入開關)。在一個實施例中,假設初始解調電壓代表在啟動過程開始處的解調電壓序列的第一解調電壓,則當檢測到解調電壓序列的目標解調電壓時,系統可以確定啟動過程完成,並且注入開關可以被斷開(turned off),其中目標解調電壓與初始解調電壓之間的電壓差大於或等於預定值。因此,當固有振盪信號的能量增長到導致目標解調電壓出現的特定值時,可以認為啟動過程已經完成,並且注入開關被斷開。 In some embodiments, the injection switch may be turned on for a predetermined period of time. That is, the time point at which the injection switch is turned off (or the time at which the startup process is completed) can be predetermined. In other embodiments, the system including the XO 20 may monitor at least one signal in the XO 20 to trigger the system to complete the startup process (for example, turn off the injection switch) in response to the above-mentioned at least one signal satisfying a specific condition. In one embodiment, assuming that the initial demodulated voltage represents the first demodulated voltage of the demodulated voltage sequence at the beginning of the start-up process, when the target demodulated voltage of the demodulated voltage sequence is detected, the system can determine that the start-up process is complete , And the injection switch may be turned off, wherein the voltage difference between the target demodulated voltage and the initial demodulated voltage is greater than or equal to a predetermined value. Therefore, when the energy of the natural oscillation signal increases to a specific value that causes the target demodulation voltage to appear, it can be considered that the start-up process has been completed and the injection switch is turned off.

本發明實施例提供的啟動方法及相關的XO架構,可以根據注入信號和固有振盪信號的幅度調製引起的失真方波,控制注入頻率的切換,以使注入信號和固有振盪信號之間的相對相位限制在期望的間隔內(例如,±90°)。基於此,在前述的鎖定/同步時段中不需要斷開注入開關,並且進一步確保了固有振盪信號的能量總是增加。假設當注入信號的注入頻率與XO核心電路的固有頻 率相同時,啟動過程需要一參考時間段。關於在以前鎖定/同步時段暫時中斷時鐘注入的方法,對於啟動過程可能需要參考時間段的17.4倍至90.6倍。關於直到完成啟動過程才斷開注入的啟動方法,可能需要1.05到1.5倍的參考時間段,這意味著本發明確實大大提高了時鐘注入效率,並且啟動時間可以被大大的減少。 The startup method and the related XO architecture provided by the embodiments of the present invention can control the switching of the injection frequency according to the distorted square wave caused by the amplitude modulation of the injection signal and the natural oscillation signal, so that the relative phase between the injection signal and the natural oscillation signal can be controlled. Limit to the desired interval (e.g., ±90°). Based on this, there is no need to turn off the injection switch during the aforementioned lock/synchronization period, and it is further ensured that the energy of the natural oscillation signal is always increased. Assume that when the injection frequency of the injected signal and the natural frequency of the XO core circuit When the rate is the same, the startup process requires a reference time period. Regarding the method of temporarily interrupting the clock injection in the previous lock/synchronization period, 17.4 times to 90.6 times of the reference time period may be required for the startup process. Regarding the startup method of disconnecting injection until the startup process is completed, a reference time period of 1.05 to 1.5 times may be required, which means that the present invention does greatly improve the clock injection efficiency, and the startup time can be greatly reduced.

所屬領域具有通常知識者將容易地觀察到,在保持本發明的教導的同時,可以對裝置和方法進行多種修改和變更。因此,以上公開內容應被解釋為僅由所附請求項的界限來限定。 Those with ordinary knowledge in the field will easily observe that while maintaining the teachings of the present invention, various modifications and changes can be made to the device and method. Therefore, the above disclosure should be interpreted as being limited only by the bounds of the appended claims.

以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

S310,S320,S330:步驟 S310, S320, S330: steps

Claims (20)

一種借助於外部時鐘注入來啟動晶體振盪器(XO)的方法,該方法包括:利用在所述晶體振盪器的晶體振盪器核心電路外部的外部振盪器產生注入信號,其中所述晶體振盪器包括晶體振盪器核心電路,位於所述晶體振盪器核心電路外部的所述外部振盪器,以及至少一個注入開關,所述至少一個注入開關耦接在所述晶體振盪器的注入節點與所述晶體振盪器核心電路的輸出端之間,所述外部振盪器耦接至所述注入節點,且所述外部振盪器的品質因數低於所述晶體振盪器核心電路的品質因數;接通所述至少一個注入開關,使所述注入信號的能量注入到所述晶體振盪器核心電路中,從而增加所述晶體振盪器核心電路的固有振盪信號的能量,其中,根據所述注入信號和所述固有振盪信號的組合,在所述注入節點上產生調製信號;以及根據所述調製信號控制所述外部振盪器選擇性的改變所述注入信號的注入頻率;其中,當所述外部振盪器選擇性的改變所述注入信號的注入頻率時,所述至少一個注入開關接通。 A method for starting a crystal oscillator (XO) by means of an external clock injection, the method comprising: generating an injection signal using an external oscillator outside the crystal oscillator core circuit of the crystal oscillator, wherein the crystal oscillator includes The crystal oscillator core circuit, the external oscillator located outside the crystal oscillator core circuit, and at least one injection switch, the at least one injection switch is coupled to the injection node of the crystal oscillator and the crystal oscillator Between the output terminals of the crystal oscillator core circuit, the external oscillator is coupled to the injection node, and the quality factor of the external oscillator is lower than the quality factor of the crystal oscillator core circuit; The injection switch causes the energy of the injection signal to be injected into the crystal oscillator core circuit, thereby increasing the energy of the natural oscillation signal of the crystal oscillator core circuit, wherein, according to the injection signal and the natural oscillation signal The combination of generating a modulation signal on the injection node; and controlling the external oscillator according to the modulation signal to selectively change the injection frequency of the injection signal; wherein, when the external oscillator selectively changes the injection frequency When the injection frequency of the injection signal is described, the at least one injection switch is turned on. 如請求項1所述的方法,其中,根據所述調製信號控制所述外部振盪器以選擇性地改變所述注入信號的注入頻率的步驟包括:利用所述晶體振盪器的解調電路根據所述調製信號生成解調電壓序列,所述解調電壓序列攜帶所述注入信號與所述固有振盪信號之間的相對相位的資訊;利用所述晶體振盪器的監視電路,根據所述解調電壓序列生成監視結果;以及 根據所述監視結果控制所述外部振盪器選擇性地改變所述注入頻率。 The method according to claim 1, wherein the step of controlling the external oscillator according to the modulation signal to selectively change the injection frequency of the injection signal includes: using the demodulation circuit of the crystal oscillator according to the The modulation signal generates a demodulation voltage sequence, and the demodulation voltage sequence carries information about the relative phase between the injection signal and the natural oscillation signal; using the monitoring circuit of the crystal oscillator, according to the demodulation voltage Sequence to generate monitoring results; and The external oscillator is controlled to selectively change the injection frequency according to the monitoring result. 如請求項2所述的方法,其中,根據所述監視結果控制所述外部振盪器選擇性地改變所述注入頻率的步驟包括:根據所述監視結果交替地將所述注入頻率切換為第一頻率或第二頻率,以使所述相對相位落在+90度和-90度之間的間隔中,其中,所述第一頻率大於所述固有振盪信號的固有頻率,以及所述第二頻率小於所述固有頻率;或者,根據所述監視結果交替地將所述注入頻率切換為第一組頻率中的頻率或者第二組頻率中的頻率,其中,所述第一組頻率大於所述固有振盪信號的固有頻率,以及所述第二組頻率小於所述固有頻率。 The method according to claim 2, wherein the step of controlling the external oscillator to selectively change the injection frequency according to the monitoring result comprises: alternately switching the injection frequency to the first according to the monitoring result Frequency or second frequency such that the relative phase falls within the interval between +90 degrees and -90 degrees, wherein the first frequency is greater than the natural frequency of the natural oscillation signal, and the second frequency Or, alternately switch the injection frequency to a frequency in a first group of frequencies or a frequency in a second group of frequencies according to the monitoring result, wherein the first group of frequencies are greater than the natural frequency The natural frequency of the oscillating signal, and the second set of frequencies are less than the natural frequency. 如請求項2所述的方法,其中,根據所述監視結果控制所述外部振盪器選擇性地改變所述注入頻率的步驟包括:根據所述監視結果,在多個候選頻率中切換所述注入頻率,以使所述注入頻率接近所述固有振盪信號的固有頻率,其中所述多個候選頻率分別對應於有限狀態機(FSM)的多個狀態。 The method according to claim 2, wherein the step of controlling the external oscillator to selectively change the injection frequency according to the monitoring result comprises: switching the injection frequency among a plurality of candidate frequencies according to the monitoring result Frequency such that the injection frequency is close to the natural frequency of the natural oscillation signal, wherein the multiple candidate frequencies respectively correspond to multiple states of a finite state machine (FSM). 如請求項2所述的方法,其中,所述解調電壓序列包括第一解調電壓和跟隨所述第一解調電壓的第二解調電壓,並且根據所述監視結果控制所述外部振盪器選擇性地改變所述注入頻率的步驟包括:回應於所述監視結果指示所述第二解調電壓大於所述第一解調電壓,將所述注入頻率從第一頻率切換到第二頻率。 The method according to claim 2, wherein the demodulated voltage sequence includes a first demodulated voltage and a second demodulated voltage following the first demodulated voltage, and the external oscillation is controlled according to the monitoring result The step of the device selectively changing the injection frequency includes: in response to the monitoring result indicating that the second demodulation voltage is greater than the first demodulation voltage, switching the injection frequency from the first frequency to the second frequency . 如請求項5所述的方法,其中,所述解調電壓序列還包括跟隨所述第二解調電壓的第三解調電壓,並且根據所述監視結果控制所述外部振盪器選擇性地改變所述注入頻率的步驟還包括:回應於所述監視結果指示所述第三解調電壓大於所述第二解調電壓,將所 述注入頻率從所述第二頻率切換為所述第三頻率;其中,所述第一頻率大於所述第二頻率,所述第二頻率大於所述第三頻率;或者,所述第一頻率小於所述第二頻率,所述第二頻率小於所述第三頻率。 The method according to claim 5, wherein the demodulated voltage sequence further includes a third demodulated voltage following the second demodulated voltage, and the external oscillator is controlled to selectively change according to the monitoring result The step of injecting frequency further includes: in response to the monitoring result indicating that the third demodulation voltage is greater than the second demodulation voltage, The injection frequency is switched from the second frequency to the third frequency; wherein, the first frequency is greater than the second frequency, and the second frequency is greater than the third frequency; or, the first frequency Less than the second frequency, and the second frequency is less than the third frequency. 如請求項2所述的方法,其中,所述解調電壓序列包括第一解調電壓和跟隨所述第一解調電壓的第二解調電壓,所述監視電路包括放大器和電容器,以及利用所述監視電路根據所述解調電壓序列生成監視結果的步驟包括:通過接通耦接在所述放大器的第二輸入端和輸出端之間的回路開關,將所述監視電路配置為單位增益緩衝器,以將所述第一解調電壓從所述放大器的第一輸入端傳輸到與所述放大器的第二輸入端耦接的電容器;以及將所述監視電路配置為比較器,以通過斷開所述回路開關來將所述放大器的所述第一輸入端上的第二解調電壓與存儲在所述電容器上的第一解調電壓進行比較,並相應地產生比較結果,其中,所述監視結果包括:所述比較結果。 The method according to claim 2, wherein the demodulated voltage sequence includes a first demodulated voltage and a second demodulated voltage following the first demodulated voltage, the monitoring circuit includes an amplifier and a capacitor, and uses The step of the monitoring circuit generating a monitoring result according to the demodulated voltage sequence includes: configuring the monitoring circuit to unity gain by turning on a loop switch coupled between the second input terminal and the output terminal of the amplifier A buffer to transmit the first demodulated voltage from the first input terminal of the amplifier to a capacitor coupled with the second input terminal of the amplifier; and configure the monitoring circuit as a comparator to pass Turn off the loop switch to compare the second demodulated voltage on the first input terminal of the amplifier with the first demodulated voltage stored on the capacitor, and generate a comparison result accordingly, wherein, The monitoring result includes: the comparison result. 如請求項2所述的方法,其中,利用所述解調電路根據所述調製信號生成所述解調電壓序列的步驟包括:接通所述解調電路的重置開關並斷開所述解調電路的採樣開關,以在重置時段內將所述解調電路的採樣節點的電壓電平重置為參考電平;以及在採樣時段中,回應於所述調製信號的電壓電平超過與所述解調電路的二極體相對應的閾值,斷開所述重置開關並接通所述採樣開關,以在所述採樣節點上累積電荷,以在所述採樣節點上生成所述解調電壓序列的解調電壓。 The method according to claim 2, wherein the step of using the demodulation circuit to generate the demodulation voltage sequence according to the modulation signal includes: turning on a reset switch of the demodulation circuit and turning off the demodulation circuit The sampling switch of the modulation circuit to reset the voltage level of the sampling node of the demodulation circuit to the reference level during the reset period; and during the sampling period, the voltage level in response to the modulation signal exceeds and The threshold corresponding to the diode of the demodulation circuit, turn off the reset switch and turn on the sampling switch to accumulate charge on the sampling node to generate the solution on the sampling node Modulate the demodulated voltage of the voltage sequence. 如請求項2所述的方法,其中,初始解調電壓表示所述解調電壓序列中的第一解調電壓,並且所述方法還包括:回應於檢測到解調電壓序列中目標解調電壓以指示啟動過程完成,斷開至少一個注入開關,其中所述目標解調電壓與所述初始解調電壓之間的電壓差大於或等於預定值。 The method according to claim 2, wherein the initial demodulated voltage represents the first demodulated voltage in the demodulated voltage sequence, and the method further includes: responding to detecting the target demodulated voltage in the demodulated voltage sequence To indicate that the startup process is completed, at least one injection switch is turned off, wherein the voltage difference between the target demodulated voltage and the initial demodulated voltage is greater than or equal to a predetermined value. 一種晶體振盪器(XO),包括:晶體振盪器核心電路,用於產生固有振盪信號;外部振盪器,耦接至所述晶體振盪器的注入節點,用於產生注入信號,其中,所述外部振盪器的品質因數低於所述晶體振盪器核心電路的品質因數;至少一個注入開關,耦接在所述注入節點與所述晶體振盪器核心電路的輸出端之間,其中,當至少一個注入開關接通時,所述注入信號的能量注入所述晶體振盪器核心電路,以增加固有振盪信號的能量,根據所述注入信號和所述固有振盪信號的組合,在所述注入節點上產生調製信號;以及頻率控制器,耦接至所述外部振盪器,用於根據所述調製信號控制所述外部振盪器選擇性地改變所述注入信號的注入頻率;其中,當所述外部振盪器選擇性地改變所述注入信號的注入頻率時,所述至少一個注入開關接通。 A crystal oscillator (XO) includes: a crystal oscillator core circuit for generating a natural oscillation signal; an external oscillator, coupled to an injection node of the crystal oscillator, for generating an injection signal, wherein the external oscillator The quality factor of the oscillator is lower than the quality factor of the crystal oscillator core circuit; at least one injection switch is coupled between the injection node and the output terminal of the crystal oscillator core circuit, wherein when at least one injection When the switch is turned on, the energy of the injection signal is injected into the crystal oscillator core circuit to increase the energy of the natural oscillation signal, and modulation is generated on the injection node according to the combination of the injection signal and the natural oscillation signal Signal; and a frequency controller, coupled to the external oscillator, for controlling the external oscillator to selectively change the injection frequency of the injection signal according to the modulation signal; wherein, when the external oscillator is selected When the injection frequency of the injection signal is changed sexually, the at least one injection switch is turned on. 如請求項10所述的晶體振盪器,其中,所述頻率控制器包括:解調電路,用於接收調製信號,並根據所述調製信號生成解調電壓序列,所述解調電壓序列中攜帶所述注入信號與所述固有振盪信號之間的相對相位的資訊;監視電路,耦接至所述解調電路,用於根據所述解調電壓序列產生監視結 果;以及有限狀態機(FSM),耦接到所述監視電路和所述外部振盪器,被配置為根據所述監視結果控制所述外部振盪器選擇性地改變所述注入頻率。 The crystal oscillator according to claim 10, wherein the frequency controller includes a demodulation circuit for receiving a modulation signal and generating a demodulation voltage sequence according to the modulation signal, and the demodulation voltage sequence carries Information about the relative phase between the injection signal and the natural oscillation signal; a monitoring circuit, coupled to the demodulation circuit, for generating a monitoring junction according to the demodulation voltage sequence And a finite state machine (FSM), coupled to the monitoring circuit and the external oscillator, configured to control the external oscillator to selectively change the injection frequency according to the monitoring result. 如請求項11所述的晶體振盪器,其中,所述有限狀態機根據所述監視結果控制所述外部振盪器交替地將所述注入頻率切換為第一頻率或第二頻率,以使所述相對相位落入+90度與-90度之間的間隔內,其中所述第一頻率大於所述固有振盪信號的固有頻率,所述第二頻率小於所述固有頻率。 The crystal oscillator according to claim 11, wherein the finite state machine controls the external oscillator to alternately switch the injection frequency to the first frequency or the second frequency according to the monitoring result, so that the The relative phase falls within the interval between +90 degrees and -90 degrees, wherein the first frequency is greater than the natural frequency of the natural oscillation signal, and the second frequency is less than the natural frequency. 如請求項11所述的晶體振盪器,其中,所述有限狀態機根據所述監視結果控制所述外部振盪器在多個候選頻率中切換所述注入頻率,以使所述注入頻率接近所述固有振盪信號的固有頻率,其中,所述多個候選頻率分別對應於所述有限狀態機的多個狀態。 The crystal oscillator according to claim 11, wherein the finite state machine controls the external oscillator to switch the injection frequency among a plurality of candidate frequencies according to the monitoring result, so that the injection frequency is close to the injection frequency. The natural frequency of the natural oscillation signal, wherein the multiple candidate frequencies respectively correspond to multiple states of the finite state machine. 如請求項11所述的晶體振盪器,其中,所述解調電壓序列包括第一解調電壓和跟隨所述第一解調電壓的第二解調電壓;以及當所述監視結果指示所述第二解調電壓大於所述第一解調電壓時,所述有限狀態機控制所述外部振盪器將所述注入頻率從第一頻率切換到第二頻率。 The crystal oscillator according to claim 11, wherein the demodulated voltage sequence includes a first demodulated voltage and a second demodulated voltage following the first demodulated voltage; and when the monitoring result indicates the When the second demodulation voltage is greater than the first demodulation voltage, the finite state machine controls the external oscillator to switch the injection frequency from the first frequency to the second frequency. 如請求項14所述的晶體振盪器,其中,所述解調電壓序列還包括跟隨所述第二解調電壓的第三解調電壓,當監視結果指示第三解調電壓大於第二解調電壓時,所述有限狀態機控制外部振盪器將所述注入頻率從第二頻率切換為第三頻率,其中,所述第一頻率大於第二頻率,所述第二頻率大於所述第三頻率;或者,所述第一頻率小於所述第二頻率所述,第二頻率小於所述第三頻率。 The crystal oscillator according to claim 14, wherein the demodulated voltage sequence further includes a third demodulated voltage following the second demodulated voltage, and when the monitoring result indicates that the third demodulated voltage is greater than the second demodulated voltage When the voltage is applied, the finite state machine controls the external oscillator to switch the injection frequency from the second frequency to the third frequency, wherein the first frequency is greater than the second frequency, and the second frequency is greater than the third frequency Or, the first frequency is less than the second frequency, and the second frequency is less than the third frequency. 如請求項11所述的晶體振盪器,其中,所述解調電壓序列包括第一解調電壓和跟隨所述第一解調電壓的第二解調電壓,所述監視電路包括:放大器,耦接至所述解調電路,用於通過所述放大器的第一輸入端接收所 述解調電壓序列;電容器,耦接到所述放大器的第二輸入端,用於順序存儲所述解調電壓序列;以及回路開關,耦接於所述放大器的所述第二輸入端與輸出端之間,用以控制所述監視電路的配置;其中,當所述回路開關接通時,所述監視電路被配置為單位增益緩衝器,以將所述第一解調電壓從所述放大器的第一輸入端傳輸至所述電容器;以及當所述回路開關斷開時,所述監視電路被配置為比較器,用於將所述放大器的第一輸入端上的第二解調電壓與所述電容器上存儲的第一解調電壓進行比較,並產生比較結果,其中,所述監視結果包括所述比較結果。 The crystal oscillator according to claim 11, wherein the demodulated voltage sequence includes a first demodulated voltage and a second demodulated voltage following the first demodulated voltage, and the monitoring circuit includes: an amplifier, a coupling Connected to the demodulation circuit for receiving the The demodulated voltage sequence; a capacitor, coupled to the second input terminal of the amplifier, for sequentially storing the demodulated voltage sequence; and a loop switch, coupled to the second input terminal and output of the amplifier Between terminals to control the configuration of the monitoring circuit; wherein, when the loop switch is turned on, the monitoring circuit is configured as a unity gain buffer to transfer the first demodulated voltage from the amplifier The first input terminal of the amplifier is transmitted to the capacitor; and when the loop switch is turned off, the monitoring circuit is configured as a comparator for comparing the second demodulated voltage on the first input terminal of the amplifier with The first demodulated voltage stored on the capacitor is compared, and a comparison result is generated, wherein the monitoring result includes the comparison result. 如請求項11所述的晶體振盪器,其中,所述解調電路包括:二極體,該二極體的陰極耦接到所述解調電路的採樣節點;重置開關,耦接在所述採樣節點與所述解調電路的參考端之間;採樣開關,耦接到所述二極體的陽極;以及採樣電容器,耦接到所述採樣節點;其中,當在復位時段所述重置開關接通且所述採樣開關斷開時,所述採樣節點的電壓電平被重置為所述參考端的參考電平;以及當在採樣時段所述重置開關斷開且所述採樣開關接通時,回應於所述調製信號的電壓電平超過對應於所述二極體的閾值,電荷在所述採樣節點上累積,在所述採樣節點上產生所述解調電壓序列的解調電壓。 The crystal oscillator according to claim 11, wherein the demodulation circuit includes: a diode, the cathode of which is coupled to the sampling node of the demodulation circuit; a reset switch, which is coupled to the sampling node of the demodulation circuit; Between the sampling node and the reference terminal of the demodulation circuit; a sampling switch, which is coupled to the anode of the diode; and a sampling capacitor, which is coupled to the sampling node; wherein, when the reset period is in the reset period, the re When the reset switch is turned on and the sampling switch is turned off, the voltage level of the sampling node is reset to the reference level of the reference terminal; and when the reset switch is turned off and the sampling switch is turned off during the sampling period When turned on, in response to the voltage level of the modulation signal exceeding the threshold corresponding to the diode, charge is accumulated on the sampling node, and the demodulation of the demodulation voltage sequence is generated on the sampling node Voltage. 如請求項11所述的晶體振盪器,其中,初始解調電壓表示所述解調電壓序列中的第一解調電壓;當檢測到所述解調電壓序列中的目標解調電壓以指示啟動過程完成時,所述至少一個注入開關斷開,其中,所述目標解 調電壓與所述初始解調電壓之間的電壓差大於或等於預定值。 The crystal oscillator according to claim 11, wherein the initial demodulated voltage represents the first demodulated voltage in the demodulated voltage sequence; when the target demodulated voltage in the demodulated voltage sequence is detected to indicate the start When the process is completed, the at least one injection switch is turned off, wherein the target solution The voltage difference between the modulation voltage and the initial demodulation voltage is greater than or equal to a predetermined value. 一種監視電路,用於產生解調電壓序列的連續比較結果,所述解調電壓序列攜帶注入信號和晶體振盪器的固有振盪信號之間的相對相位的資訊,所述監視電路包括:放大器,用於通過所述放大器的第一輸入端接收所述解調電壓序列,其中,所述解調電壓序列包括第一電壓和跟隨所述第一電壓的第二電壓;電容器,耦接到所述放大器的第二輸入端,用於順序的存儲所述解調電壓序列;以及回路開關,耦接於所述放大器的第二輸入端與輸出端之間,用於控制所述監視電路的配置;其中,當所述回路開關接通時,所述監視電路被配置為單位增益緩衝器,用於將所述第一電壓從所述放大器的第一輸入端傳輸至所述電容器;當所述回路開關斷開時,所述監視電路被配置為比較器,用於將所述放大器的第一輸入端上的第二電壓與所述電容器上存儲的第一電壓進行比較,並生成所述連續比較結果中的比較結果;其中,所述比較結果攜帶所述注入信號與晶體振盪器的固有振盪信號之間的相對相位的資訊,用於控制所述注入信號的注入頻率。 A monitoring circuit for generating a continuous comparison result of a demodulated voltage sequence, the demodulated voltage sequence carrying information about the relative phase between an injection signal and a natural oscillation signal of a crystal oscillator, the monitoring circuit comprising: an amplifier, The demodulated voltage sequence is received through the first input terminal of the amplifier, wherein the demodulated voltage sequence includes a first voltage and a second voltage following the first voltage; a capacitor is coupled to the amplifier The second input terminal of the amplifier is used to sequentially store the demodulated voltage sequence; and a loop switch, coupled between the second input terminal and the output terminal of the amplifier, is used to control the configuration of the monitoring circuit; wherein When the loop switch is turned on, the monitoring circuit is configured as a unity gain buffer for transmitting the first voltage from the first input terminal of the amplifier to the capacitor; when the loop switch When disconnected, the monitoring circuit is configured as a comparator for comparing the second voltage on the first input terminal of the amplifier with the first voltage stored on the capacitor, and generating the continuous comparison result Wherein, the comparison result carries information about the relative phase between the injection signal and the natural oscillation signal of the crystal oscillator, and is used to control the injection frequency of the injection signal. 如請求項19所述的監視電路,其中,當所述回路開關接通時,由所述放大器的第一輸入端和第二輸入端的不匹配引起的固有偏移與所述第一電壓一起存儲在所述電容器上,從而防止所述比較結果受到固有偏移的影響。 The monitoring circuit according to claim 19, wherein when the loop switch is turned on, the inherent offset caused by the mismatch between the first input terminal and the second input terminal of the amplifier is stored together with the first voltage On the capacitor, thereby preventing the comparison result from being affected by the inherent offset.
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