TWI744030B - Display - Google Patents

Abstract

A display includes a plurality of scan lines, a plurality of data lines, a pixel array, a plurality of first fan-out traces, a plurality of first signal lines and a plurality of pads. The scan lines extend in a first direction, and the data lines extend in a second direction, where the first direction is not parallel with the second direction. The pixel array is connected to the scan lines and the data lines. Each first fan-out trace is electrically connected to a data line. The extension direction of each first fan-out trace is not parallel with the first direction. Each first signal line includes a first segment, a second segment, and a first linking structure. The first segment is connected to one end of the first fan-out trace, and the first linking structure is connected to the first segment and the second segment. The first segment and the second segment both extend in the second direction. The second segment of each first signal line is electrically connected to a pad.

Description

monitor

The present invention relates to a display, and more particularly to a display with fan-out trace.

At present, some displays, such as liquid crystal displays, use conductive glue to adhere the driving element to the pixel array substrate, and electrically connect the driving element to a plurality of pads of the pixel array substrate, so that the driving element can control the pixel array substrate . In the actual manufacturing process of the display, the driving element is sometimes not stuck in the correct position, so that the driving element is not electrically connected to the corresponding pad. At this time, the staff will separate the combined driving element from the pixel array substrate. Then, conductive glue is used to re-adhere the driving element on the pixel array substrate, so that the driving element is adhered to the correct position, thereby electrically connecting the corresponding pads.

In the process of re-adhering the driving element to the pixel array substrate, the conductive glue remaining on the pixel array substrate must be removed to make the surface of the pixel array substrate clean and flat. Otherwise, the remaining conductive glue will make the surface of the pixel array substrate become uneven, thereby hindering the electrical connection between the driving element and the pixel array substrate. In detail, the remaining conductive glue will hinder the connection between the driving element and the pad, resulting in that the driving element cannot be electrically connected to the corresponding pad, resulting in disconnection.

The above-mentioned residual conductive adhesive is usually removed by a sharp tool, such as a toothpick, by a worker. However, the remaining conductive glue usually covers the circuit structure of the pixel array substrate, and the above-mentioned sharp tools are easy to accidentally damage the fragile part of the circuit structure. Forced to scrap.

At least one embodiment of the present invention provides a display to reduce or prevent the fragile part of the circuit structure from being covered by conductive glue.

A display provided by at least one embodiment of the present invention includes a substrate, a plurality of parallel scan lines, a plurality of parallel data lines, a pixel array, a plurality of first fan-out traces, a plurality of parallel first signal lines, and a plurality of A connection pad. The substrate has a display area and a non-display area outside the display area. These scan lines are arranged on the substrate and extend along the first direction. The data lines are arranged on the substrate and extend along the second direction, wherein the first direction is not parallel to the second direction. The pixel array is arranged on the substrate and located in the display area, and the pixel array connects the scan lines and the data lines. These first fan-out traces are arranged on the substrate and located in the non-display area. Each of the first fan-out traces is electrically connected to one of the data lines, and each first fan-out trace extends in the direction Not parallel to the first direction. These first signal lines are arranged on the substrate and located in the non-display area. Each first signal line includes a first line segment, a second line segment and a first switching structure. The first line segment connects one end of one of the first fan-out traces, and the first transition structure connects the first line segment and the second line segment, wherein the first line segments and the second line segments all extend along the second direction . The pads are arranged on the substrate and located in the non-display area. The second line segment of each first signal line is electrically connected to one of the pads.

In at least one embodiment of the present invention, a shortest distance between the pads and the first transition structure is greater than or equal to 300 microns, and an average distance between the pads and the first transition structure is greater than 500 Micrometers.

In at least one embodiment of the present invention, there is the shortest distance between at least one of the two outermost first transition structures and these pads.

In at least one embodiment of the present invention, the first switching structures are not arranged along the first direction and the second direction.

In at least one embodiment of the present invention, there is the shortest distance between at least one of the two outermost first transition structures and these pads, and the distance between any one of the first transition structures and the pads The distance is greater than or equal to the shortest distance.

In at least one embodiment of the present invention, the non-display area has a first area and a second area. The first area is adjacent to the second area, and both the first area and the second area are arranged along the first direction. These first signal lines are located in the first area and the second area. The first switching structures located in the first area are arranged along a first straight line, and the first switching structures located in the second area are arranged along a second straight line. The first straight line and the second straight line are not parallel, and the first straight line and the second straight line are not parallel to the first direction and the second direction.

In at least one embodiment of the present invention, the non-display area has a first area, a second area, and a central area. The central area is located between the first area and the second area, and the first area, the central area, and the second area are all arranged along the first direction. The first signal lines are located in the first area, the second area, and the central area. The first switching structures located in the first area are arranged along the first straight line, and the first switching structures located in the second area are arranged along the first straight line. The connection structures are arranged along a second straight line, wherein the first straight line and the second straight line are not parallel, and the first straight line and the second straight line are not parallel to the first direction and the second direction. In addition, the first switching structures located in the central area are arranged along the first direction.

In at least one embodiment of the present invention, the above-mentioned display further includes a plurality of second fan-out wiring lines and a plurality of parallel second signal lines. The second fan-out traces are arranged on the substrate and located in the non-display area, and each of the second fan-out traces is electrically connected to one of the data lines. The second signal lines are disposed on the substrate and located in the non-display area. The second signal lines are respectively connected to one end of the second fan-out traces, and each of the second signal lines is electrically connected to one of the pads.

In at least one embodiment of the present invention, the non-display area has a first area, a second area, and a central area. The central area is located between the first area and the second area, and the first area, the central area, and the second area are all arranged along the first direction. The first signal lines are located in the first area, the second area, and the central area, wherein at least one first line segment located in the central area has a first impedance control archline.

In at least one embodiment of the present invention, the second signal lines are located in the first area, the second area, and the central area, and at least one of the second signal lines located in the central area has a second impedance control archline.

In at least one embodiment of the present invention, the above-mentioned display further includes a plurality of second switching structures and a plurality of third signal lines. The second switching structures respectively connect the second line segments and the second signal lines. The third signal lines are respectively connected between the second transfer structure and the pads.

In at least one embodiment of the present invention, the above-mentioned display further includes a driving element, wherein the driving element is mounted on the pads.

In at least one embodiment of the present invention, the above-mentioned display further includes conductive glue, wherein the conductive glue is distributed in an area between the first transition structures and the pads, and covers at least a part of each second line segment and the connections. pad.

Utilizing the display design of at least one embodiment of the present invention described above can help reduce or avoid the fragile part of the circuit structure (such as the first transition structure) being covered by the conductive glue, so that the staff can use sharp tools to remove the residual conductive glue. In this way, the fragile part of the above-mentioned circuit structure is reduced or prevented from being damaged by sharp tools.

In the following text, in order to clearly present the technical features of the case, the dimensions (such as length, width, thickness, and depth) of the elements (such as layers, films, substrates, and regions) in the drawings will be enlarged in unequal proportions. . Therefore, the description and explanation of the following embodiments are not limited to the size and shape presented by the elements in the drawings, but should cover the size, shape, and deviation of the two caused by actual manufacturing processes and/or tolerances. For example, the flat surface shown in the drawing may have rough and/or non-linear characteristics, and the acute angle shown in the drawing may be round. Therefore, the elements shown in the drawings of this case are mainly used for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the scope of the patent application in this case.

Secondly, the words "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated value and range of values, but also cover the understanding of those with ordinary knowledge in the technical field of the invention. The allowable deviation range of, wherein the deviation range can be determined by the error generated during the measurement, and this error is caused by the limitation of the measurement system or the process conditions, for example. For example, two objects (such as the plane or trace of the substrate) are "substantially parallel" or "substantially perpendicular", where "substantially parallel" and "substantially perpendicular" represent the parallel and perpendicular between the two objects, respectively Can include non-parallel and non-perpendicular caused by the allowable deviation range.

In addition, "about" may mean within one or more standard deviations of the above-mentioned value, for example, within ±30%, ±20%, ±10%, or ±5%. The terms "about", "approximately" or "substantially" appearing in this text can be used to select acceptable deviation ranges or standard deviations based on optical properties, etching properties, mechanical properties, or other properties. The standard deviation applies all the above optical properties, etching properties, mechanical properties, and other properties.

FIG. 1A is a schematic top view of a display according to at least one embodiment of the invention. 1A, the display 100 includes a substrate 110, a plurality of parallel scan lines 120, a plurality of parallel data lines 130, and a pixel array 140. The scan lines 120, the data lines 130, and the pixel array 140 are all disposed on the substrate 110, where the substrate 110 may be a transparent plate, such as a glass plate or a transparent plastic plate.

The scan lines 120 extend along the first direction D1, and the data lines 130 extend along the second direction D2. In other words, the main body of each scan line 120 is substantially parallel to the first direction D1, and the main body of each data line 130 is substantially parallel to the second direction D2. In addition, the first direction D1 is not parallel to the second direction D2. Taking FIG. 1A as an example, the first direction D1 is a horizontal direction, and the second direction D2 is a vertical direction, so the first direction D1 and the second direction D2 may be substantially perpendicular to each other. Therefore, the scan lines 120 and the data lines 130 are interlaced with each other and arranged in a mesh shape, as shown in FIG. 1A.

The substrate 110 has a display area 111 and a non-display area 112 outside the display area 111. The pixel array 140 is located in the display area 111 and connects the scan lines 120 and the data lines 130. The pixel array 140 includes a plurality of control elements 141 and a plurality of pixel elements 142, wherein the control elements 141 are electrically connected to the pixel elements 142, respectively. In the embodiment shown in FIG. 1A, the control element 141 may be a transistor, such as a thin-film transistor (TFT, TFT). In addition, the control element 141 in FIG. 1A is represented by a circuit symbol of a transistor.

The display 100 may be one of multiple types of displays. For example, the display 100 may be a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode Display (OLED Display), or a micro LED Display (μLED Display). Depending on the type of the end-view display 100, the pixel element 142 can have various implementations.

When the display 100 is a liquid crystal display, the display 100 may further include a liquid crystal layer (not shown) and an opposite substrate (not shown), and the pixel element 142 may be a pixel electrode, which is formed of, for example, a transparent conductive film The main material of the transparent conductive film can be metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opposite substrate is disposed relative to the substrate 110, and the liquid crystal layer is sandwiched between the substrate 110 and the opposite substrate, wherein the opposite substrate may be a color filter substrate. When the display 100 is an organic light emitting diode display or a micro light emitting diode display, the pixel element 142 may be an organic light emitting diode or a micro light emitting diode.

In the embodiment shown in FIG. 1A, the control element 141 is a transistor (such as a thin film transistor), and each control element 141 has a gate, a source, and a drain (the gate, source, and drain are not marked in FIG. 1A). ). The scan lines 120 are electrically connected to the gates of the control elements 141, and the data lines 130 are electrically connected to the sources of the control elements 141, and the drains of the control elements 141 are electrically connected to the pixel elements 142, respectively.

It can be seen that the voltage transmitted by the scan lines 120 can turn on and off the control elements 141 to control the data lines 130 to input pixel signals from the control elements 141 to the pixel elements 142. In this way, according to the pixel signal, the pixel elements 142 can enable the display 100 to generate a plurality of pixels with various gray levels, so that the display 100 can display images. In addition, since the pixel array 140 is located in the display area 111, the image will be displayed in the display area 111 but not in the non-display area 112.

The display 100 further includes a plurality of first fan-out wiring lines 151, a plurality of second fan-out wiring lines 152, a plurality of parallel first signal lines 161, and a plurality of parallel second signal lines 162. The first fan-out wiring 151, the second fan-out wiring 152, the first signal line 161, and the second signal line 162 are all disposed on the substrate 110 and are also located in the non-display area 112. The first fan-out traces 151 and the second fan-out traces 152 are electrically connected to the data lines 130, respectively. That is, each of the first fan-out wires 151 is electrically connected to one of the data lines 130, and each of the second fan-out wires 152 is electrically connected to the other data line 130.

The extension directions of the first fan-out wires 151 and the second fan-out wires 152 are obviously not parallel to the first direction D1. Taking FIG. 1A as an example, each of the first fan-out traces 151 and each of the second fan-out traces 152 are not parallel to the first direction D1, that is, not parallel to the horizontal direction. Therefore, the first fan-out wiring 151 and the second fan-out wiring 152 do not completely extend along the first direction D1 (for example, the horizontal direction).

The first signal lines 161 are respectively connected to one end of the first fan-out lines 151, and the second signal lines 162 are respectively connected to one end of the second fan-out lines 152, wherein each of the first signal lines 161 and each of the second The extension directions of both the signal lines 162 may be substantially parallel to the second direction D2 (for example, the vertical direction). Therefore, the extension direction of both the first signal line 161 and the second signal line 162 can be the same as the extension direction of the data line 130. In addition, each of the first signal lines 161 includes the first switching structure V1, but the second signal line 162 does not include the first switching structure V1.

The display 100 may further include a plurality of second switching structures V2, a plurality of third signal lines 163, and a plurality of pads 170, wherein the second switching structures V2, the third signal lines 163, and the pads 170 are all provided On the substrate 110, they are all located in the non-display area 112. The second switching structures V2 are respectively connected to the first signal lines 161 and the second signal lines 162, and each of the second switching structures V2 is connected to a first signal line 161 or a second signal line 162. The third signal lines 163 are respectively connected between the second switching structure V2 and the pads 170.

Each second switching structure V2 is connected between the adjacent first signal line 161 and the third signal line 163, or connected between the adjacent second signal line 162 and the third signal line 163. Using the second switching structures V2 and the third signal lines 163, each of the first signal lines 161 or each of the second signal lines 162 can be electrically connected to one of the pads 170. In this way, the pads 170 can be electrically connected to the data lines 130 via the first signal lines 161, the second signal lines 162, the first fan-out lines 151 and the second fan-out lines 152.

The display 100 may further include a driving element 180 and a conductive glue 190 (the area where the dots are distributed in FIG. 1A ), where the conductive glue 190 may be an anisotropic conductive film (ACF). The driving element 180 may be a chip or a circuit substrate on which a chip has been installed, and the aforementioned circuit substrate may be a flexible circuit board. The conductive adhesive 190 is distributed in the area Z1 between the first transfer structure V1 and the pads 170, and even exceeds the area Z1 to cover the pads 170.

The conductive glue 190 can adhere and fix the driving element 180 on the substrate 110 so that the driving element 180 can be installed on the pads 170 in the non-display area 112 and can be electrically connected to the pads 170. In this way, the driving element 180 can transmit pixel signals from the pads 170 to the data lines 130, so that the data lines 130 can input the pixel signals to the pixel elements 142, so that the display 100 can display images.

FIG. 1B is a schematic partial top view of the display in FIG. 1A at the non-display area, and FIG. 1C is a schematic cross-sectional view along the line 1C-1C in FIG. 1B. It is noted in advance that the aforementioned FIG. 1A roughly shows the first signal line 161, the second signal line 162, the first fan-out wiring 151, and the second fan-out wiring 152 to simply show the overall extension direction and position of these lines. FIG. 1A is a simplified drawing of the above-mentioned circuits in the form of a circuit diagram, and these circuits are not shown in detail.

However, FIG. 1B specifically illustrates the first signal line 161, the second signal line 162, the first fan-out wiring 151, and the second fan-out wiring 152, and reveals the layout of these circuits. Therefore, there is a difference between Fig. 1A and Fig. 1B. However, these differences do not affect the understanding of the technical features and means of this embodiment by those with ordinary knowledge in the technical field to which the invention belongs, that is, those with ordinary knowledge in the technical field to which the invention belongs can still use the contents of the description of the present case and FIGS. 1A to 1C. Accordingly, the display 100 is realized.

1B and 1C, the first fan-out wiring 151 and the second fan-out wiring 152 are obviously not on the same plane, and the first fan-out wiring 151 is located above the second fan-out wiring 152. In other words, the height of the first fan-out trace 151 relative to the substrate 110 is significantly greater than the height of the second fan-out trace 152 relative to the substrate 110. In addition, the first fan-out wiring lines 151 may overlap with the second fan-out wiring lines 152, wherein at least a part of the second fan-out wiring lines 152 extend along the first fan-out wiring lines 151, so in FIG. 1B, some of the first fan-out wiring lines 151 The second fan-out wiring 152, especially the second fan-out wiring 152 located on the left half, will be covered by the first fan-out wiring 151.

In the embodiment shown in FIG. 1C, the display 100 may further include multiple insulating layers 101, 102, 103, and 104 stacked on each other. The insulating layer 101 is formed on the substrate 110, and the insulating layers 102 and 103 are both located on the insulating layer 101. And 104, where the insulating layer 102 is stacked on the insulating layer 101, and the insulating layer 103 is stacked on the insulating layer 102, so the insulating layer 102 is located between the insulating layers 101 and 103, and the insulating layer 103 is located between the insulating layers 102 and 104 between.

The first fan-out wiring 151 is formed on the insulating layer 103 and is covered by the insulating layer 104, so the first fan-out wiring 151 is sandwiched between the insulating layers 103 and 104. The second fan-out wiring 152 is formed on the insulating layer 102 and is covered by the insulating layer 103, so the second fan-out wiring 152 is sandwiched between the insulating layers 102 and 103. Therefore, the first fan-out wiring 151 will be located above the second fan-out wiring 152, that is, the distance between the first fan-out wiring 151 and the substrate 110 will be greater than the distance between the second fan-out wiring 152 and the substrate 110, such as Shown in Figure 1C.

In particular, the first fan-out wiring 151 and the second fan-out wiring 152 shown in FIG. 1A are both represented by a single solid line, and FIG. 1A shows the first fan-out wiring 151 and the second fan-out wiring that are separated from each other. Lines 152 to clearly show the overall extension directions of the first fan-out wires 151 and the second fan-out wires 152. Therefore, although FIG. 1A does not show the first fan-out wiring 151 and the second fan-out wiring 152 overlapping each other, FIG. 1A is only used to clearly show the overall extension direction of the first fan-out wiring 151 and the second fan-out wiring 152 It is not intended to restrict the first fan-out wiring 151 and the second fan-out wiring 152 not to overlap with each other.

Each first signal line 161 also includes a first line segment S1 and a second line segment S2. The first line segment S1 is connected to one end of one of the first fan-out wires 151, and the first switching structure V1 connects the first line segment S1 and the second line segment S2, so that the first line segment S1 can pass through the first switching structure V1 is electrically connected to the second line segment S2. In addition, the first line segments S1 and the second line segments S2 all extend along the second direction D2, and the first signal lines 161 and the second signal lines 162 may be arranged in a staggered manner, as shown in FIG. 1B.

The first line segment S1 and the second line segment S2 are obviously not on the same plane. Taking FIG. 1C as an example, the first line segment S1 is formed on the insulating layer 103 and is covered by the insulating layer 104, so the first line segment S1 is sandwiched between the insulating layers 103 and 104, where the first line segment S1 and The first fan-out wiring 151 may be substantially on the same plane. The second line segment S2 is formed on the insulating layer 102 and is covered by the insulating layer 103, so the second line segment S2 is sandwiched between the insulating layers 102 and 103, where the second line segment S2 and the second fan-out trace 152 can be substantially On the same plane. It can be seen that the first line segment S1 will be located above the second line segment S2, that is, the height of the first line segment S1 relative to the substrate 110 is significantly greater than the height of the second line segment S2 relative to the substrate 110, as shown in FIG. 1C.

The first line segments S1 and the first fan-out traces 151 can be formed from a single conductive layer by photolithography, and the second line segments S2 and the second fan-out traces 152 can be formed from another conductive layer by photolithography. The conductive layer may be a metal layer or the aforementioned transparent conductive film. Therefore, the first line segment S1 and the first fan-out wiring 151 connected to each other may be integrally formed. In addition, the data lines 130 (see FIG. 1A), the second line segments S2, and the second fan-out traces 152 can also be formed from the same conductive layer by photolithography, and the data lines 130, the second line segments S2 and The second fan-out wiring 152 may be substantially on the same plane.

Since the first line segment S1 is located above the second line segment S2, the first signal line 161 includes two layers of lines that are not on the same plane (that is, the first line segment S1 and the second line segment S2), and it is obviously not conducted by a single layer. The layer is formed by photolithography. The first transition structure V1 can connect the first line segment S1 and the second line segment S2 that are not on the same plane, so that the first line segment S1 is electrically connected to the second line segment S2.

Taking FIG. 1C as an example, each first transition structure V1 includes two conductive pillars V11 and V12 and a bridge line V13. The bridge line V13 is formed on the insulating layer 104 and connects the conductive pillars V11 and V12. Therefore, the conductive posts V11 and V12 can be electrically connected to each other through the bridge wire V13. The conductive pillar V11 penetrates the insulating layer 104 and connects to the first line segment S1 of the first signal line 161, and the conductive pillar V12 penetrates through the insulating layers 104 and 103 and connects to the second line segment S2 of the first signal line 161. In this way, through the first switching structure V1, the first line segment S1 is electrically connected to the second line segment S2. In addition, the conductive pillars V11, V12 and the bridge wiring V13 can be formed by photolithography of a transparent conductive material or a metal material, wherein the transparent conductive material can be the aforementioned metal oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO). ).

The second signal line 162 and the second line segment S2 may be substantially on the same plane. In other words, the second signal line 162 is also formed on the insulating layer 102 and is covered by the insulating layer 103 so that the second signal line 162 is sandwiched between the insulating layers 102 and 103. Therefore, the data lines 130 (please refer to FIG. 1A), the second line segments S2, the second fan-out traces 152, and the second signal lines 162 can be formed by photolithography on the same conductive layer, and the second line segments connected to each other can be formed by photolithography. The signal line 162 and the second fan-out wiring 152 may be integrally formed, and the conductive layer may be the above-mentioned transparent conductive film or metal layer.

These third signal lines 163 are formed on the insulating layer 101 and are covered by the insulating layer 102, so the third signal lines 163 are sandwiched between the insulating layers 101 and 102. The third signal line 163 is located below the second line segment S2, and the second line segment S2 is located between the third signal line 163 and the first line segment S1, as shown in FIG. 1C. Of course, since the second signal line 162 and the second line segment S2 can be substantially on the same plane, the second signal line 162 is also located between the third signal line 163 and the first line segment S1.

In the embodiment shown in FIG. 1C, each second via structure V2 may be a conductive pillar and penetrate through the insulating layer 102. The second switching structures V2 are respectively connected to the second line segments S2 and the second signal lines 162, wherein each second switching structure V2 is connected between the adjacent second line segments S2 and the third signal line 163, or It is connected between adjacent second signal lines 162 and third signal lines 163, so that the first signal lines 161 and the second signal lines 162 are electrically connected to the third signal lines 163, respectively.

Since the third signal lines 163 are electrically connected to the pads 170, the second switching structure V2 and the third signal lines 163 are used to electrically connect the second line segment S2 of each first signal line 161. One pad 170, and each of the second signal lines 162 can be electrically connected to the other pad 170. In this way, the driving element 180 can transmit pixel signals from the pads 170 to the data lines 130 so that the pixel elements 142 receive the pixel signals, so that the display 100 can display images.

In particular, in this embodiment, each first transition structure V1 includes two conductive posts V11, V12 and a bridge wire V13. However, in other embodiments, the first transfer structure V1 may also be a conductive pillar penetrating the insulating layer 103 and electrically connected between the first line segment S1 and the second line segment S2. Therefore, FIG. 1C is for illustration only, and does not limit the first transition structure V1 to include two conductive posts V11 and V12 and a bridge line V13.

The shortest distance G1 between the pads 170 and the first transition structures V1 may be greater than or equal to 300 μm, for example, may be between 300 μm and 1760 μm, where the shortest distance G1 may be along the second direction D2. In other words, the distance between any one of the first transition structures V1 and the pads 170 (along the second direction D2) may be greater than or equal to the shortest distance G1, for example, 300 microns. In addition, the average distance between the pads 170 and the first transfer structure V1 may be greater than 500 microns, and the average distance may also be along the second direction D2.

Please refer to FIGS. 1A and 1B, the conductive adhesive 190 mainly adheres the driving element 180 to and electrically connects the pads 170. During the process of the conductive glue 190 adhering the driving element 180 to the pads 170, the conductive glue 190 will be squeezed by the driving element 180 and the substrate 110 and overflow, so that the conductive glue 190 not only covers the pads 170, but also The pads 170 overflow to the third signal lines 163, the second switching structures V2, and the second line segments S2, so as to cover the third signal lines 163, the second switching structures V2, and the second line segments S2. Line segment S2.

Generally speaking, the longest distance that the conductive adhesive 190 overflows from the pad 170 along the direction parallel to the second direction D2 toward the display area 111 is about 500 microns. Since the shortest distance G1 between the pads 170 and the first transition structures V1 is greater than or equal to 300 micrometers, for example, between 300 micrometers and 1760 micrometers, and between the pads 170 and the first transition structures V1 The average distance is greater than 500 microns, so most of the first transition structure V1 will be outside the overflow range of the conductive adhesive 190. In other words, the conductive glue 190 covers at least a part of each second line segment S2 and a few first transfer structures V1, but most of the first transfer structures V1 will not be covered by the conductive glue 190, even these first transfer structures V1 Either one may not be covered by the conductive glue 190.

Referring to FIG. 1C, the first transfer structure V1 is located on the outermost side of the display 100, and the second transfer structure V2 is provided with insulating layers 103 and 104. Therefore, compared with the second switching structure V2, the first switching structure V1 is easily damaged by foreign objects (such as toothpicks), or even damaged, so that the display 100 may be forced to be scrapped. In other words, the first switching structure V1 is a fragile part of the circuit structure of the display 100.

However, in the display 100 of this embodiment, most or even all of the first transfer structure V1 will not be covered by the conductive glue 190. Therefore, during the production process of the display 100, most of the remaining conductive glue 190 will not cover the first transfer structure V1, so as to reduce or avoid the first transfer structure V1 being damaged by sharp tools, thereby improving the display 100 Yield.

1B, there is a shortest distance G1 between at least one of the two outermost first transition structures V1 and the pads 170, and in this embodiment, the two outermost first transition structures V1 , That is, the distances between the two first transfer structures V1 at the leftmost and rightmost in FIG. 1B and these pads 170 are the shortest distance G1. In addition, the conductive glue 190 may completely cover the outermost second line segment S2.

The non-display area 112 has a first area 112a and a second area 112b. The first area 112a is adjacent to the second area 112b, and the first area 112a and the second area 112b are arranged along the first direction D1. The first signal lines 161 and the second signal lines 162 are located in the first area 112a and the second area 112b, and the first switching structures V1 are not arranged along the first direction D1 and the second direction D2.

Taking FIG. 1B as an example, the first transition structures V1 located in the first area 112a are arranged along the first straight line L1, and the first transition structures V1 located in the second area 112b are arranged along the second straight line L2. The first straight line L1 and the second straight line L2 are both virtual reference straight lines. The first straight line L1 and the second straight line L2 are not parallel, and neither the first straight line L1 nor the second straight line L2 is parallel to the first direction D1 and the second direction D2. In addition, the first straight line L1 and the second straight line L2 will intersect and form an inverted V shape as shown in FIG. 1B.

Since the shortest distance G1 between the first transfer structure V1 and the pad 170 is between the outermost first transfer structure V1 and the pad 170, the intersection of the first straight line L1 and the second straight line L2 and these The distance between the pads 170 will be greater than the shortest distance G1, and the intersection point can be at or near the first transition structure V1 in the middle. In addition, the change in the distance between the first transfer structure V1 and the pad 170 may be decreasing from the first transfer structure V1 in the middle toward the first transfer structure V1 on the outermost sides, so the first transfer structure V1 located in the middle and near the middle A transition structure V1 is difficult to be covered by the conductive adhesive 190. In this way, the first transfer structure V1 damaged by sharp tools can be reduced or avoided, so as to improve the yield of the display 100.

In particular, in this embodiment, the display 100 includes a first signal line 161, a second signal line 162, a first fan-out wiring 151, and a second fan-out wiring 152. However, in other embodiments, the display 100 may include the first signal line 161 and the first fan-out wiring 151, but does not include any second signal line 162 and the second fan-out wiring 152. In other words, the second signal line 162 and the second fan-out wiring 152 shown in FIGS. 1A to 1C can be omitted. Therefore, the display 100 is not limited to include the second signal line 162 and the second fan-out wiring 152.

FIG. 2 is a schematic partial top view of a display according to another embodiment of the present invention. Please refer to FIG. 2, the display 200 of this embodiment is similar to the display 100 of the previous embodiment. For example, the overall circuit structure of the display 200 is substantially the same as the display 100 shown in FIG. 1A, and the display 200 also includes a plurality of scan lines 120, a plurality of data lines 130 and a pixel array 140. The only difference between the displays 100 and 200 is that they have different wiring in the non-display area. The following mainly describes the above-mentioned differences, in which FIG. 2 only shows the wiring of the display 200 in the non-display area 212 thereof. In principle, the same features of the displays 100 and 200 will not be repeated in description and illustration.

The substrate (for example, the substrate 110) included in the display 200 has a display area 111 (see FIG. 1A) and a non-display area 212, wherein the non-display area 212 has a first area 212a, a second area 212b, and a central area 212c, and these second areas A fan-out trace 151, the second fan-out traces 152, the first signal lines 161, the second signal lines 162, and the third signal lines 163 are all located in the first area 212a, the second area 212b, and the central area Within 212c.

The central area 212c is located between the first area 212a and the second area 212b, and the first area 212a, the central area 212c, and the second area 212b are all arranged along the first direction D1. Similar to the display 100 in FIG. 1B, the first switching structures V1 located in the first area 212a are arranged along the first straight line L1, and the first switching structures V1 located in the second area 212b are arranged along the second straight line L2 arrangement. Secondly, the shortest distance G1 (which may be greater than or equal to 300 μm) between the first transfer structure V1 and the pad 170 is between the outermost first transfer structure V1 and the pad 170. In other words, the shortest distance G1 will be within at least one of the first area 212a and the second area 212b.

Different from the display 100 in FIG. 1B, the first switching structures V1 located in the central area 212c are arranged along a third straight line L3, where the third straight line L3 is a virtual reference straight line and is parallel to the first direction D1, Therefore, the first switching structures V1 located in the central area 212c are arranged along the first direction D1.

Since the shortest distance G1 is in at least one of the first area 212a and the second area 212b, the distance between the first transition structures V1 and the pads 170 in the central area 212c will exceed the shortest distance G1. Therefore, during the production process of the display 200, the remaining conductive glue 190 basically does not cover the first transition structure V1 located in the central area 212c, so as to reduce or avoid the first transition structure V1 damaged by sharp tools. , Thereby improving the yield of the display 200.

FIG. 3 is a schematic partial top view of a display according to another embodiment of the present invention. Please refer to FIG. 3, the display 300 of this embodiment is similar to the display 200 of the previous embodiment. For example, the display 300 also includes a substrate (such as the substrate 110), a plurality of first fan-out traces 151, a plurality of second fan-out traces 152, a plurality of first signal lines 361, a plurality of second signal lines 362, and a plurality of Three signal lines 163 and a plurality of second switching structures V2.

The non-display area of the substrate also has a first area, a second area, and a central area, such as the first area 212a, the second area 212b, and the central area 212c shown in FIG. 2. The first signal lines 361, the second signal lines 362, and the third signal lines 163 are all located in the first area, the second area, and the central area. Each first signal line 361 includes a first line segment S31, a second line segment S2, and a first switching structure V1, wherein each first switching structure V1 is electrically connected to adjacent first line segment S31 and second line segment S2 , So that the first line segments S31 are electrically connected to the second line segments S2 respectively. In addition, these first connecting structures V1 are also arranged along the first straight line L1, the second straight line L2, and the third straight line L3, as shown in FIG. 2.

The main difference between the display 300 and the display 200 is shown in FIG. 3, where the display 300 shown in FIG. 3 is a top view of the central area thereof. Specifically, different from the display 200 of the foregoing embodiment, in the central area of the display 300, at least one first line segment S31 has a first impedance control bow line S31a, and at least one second signal line 362 has a second impedance Adjust the bow line 362a.

Taking FIG. 3 as an example, the plurality of first line segments S31 respectively have a plurality of first impedance adjusting arch wires S31a, and the plurality of second signal lines 362 have a plurality of second impedance adjusting arch wires 362a, respectively. In addition, in other embodiments, only one first line segment S31 may have a first impedance adjusting bow wire S31a, and only one second signal line 362 may have a second impedance adjusting bow wire 362a, so FIG. 3 does not limit the first impedance adjusting The number of arch wires S31a and the second impedance control arch wires 362a.

The first impedance control bow wire S31a and the second impedance control bow wire 362a can respectively increase the path lengths of the first signal line 361 and the second signal line 362, thereby increasing both the first signal line 361 and the second signal line 362的impedance. Specifically, the first fan-out trace and the second fan-out trace near the outside of the non-display area have a longer length, but the first fan-out trace and the second fan-out trace located near and near the center of the non-display area The line has a shorter length (as shown in Figure 1A).

Therefore, the first signal line 361 and the second signal line 362 close to the outer side of the non-display area generally have larger impedances, while the first signal line 361 and the second signal line 362 located at and near the center of the non-display area Usually will have a smaller impedance. Therefore, not only the impedance difference between the first signal lines 361 is very large, but also the impedance difference between the second signal lines 362 is also very large. In this way, these data lines 130 will receive distorted pixel signals, which will cause image quality degradation.

However, the first impedance regulating bow wire S31a and the second impedance regulating bow wire 362a located in the central area can increase the impedance of both the first signal line 361 and the second signal line 362 respectively, so that the first signal lines 361 and these The impedance gap between the second signal lines is reduced. In this way, the pixel signals transmitted by the first signal line 361 and the second signal line 362 will not be too different, thereby helping to maintain or improve the image quality of the display 300.

In particular, both the first impedance regulating bow wire S31a and the second impedance regulating bow wire 362a shown in FIG. 3 can be applied to the display 100 shown in FIG. 1B. In detail, the at least one first signal line 161 and the at least one second signal line 162 in the center of FIG. 1B can be replaced with a first signal line 361 having a first impedance regulating bow line S31a and a second impedance regulating bow Line 362a is the second signal line 362.

In other words, in the display 200 shown in FIG. 2, the first switching structures V1 in the central area 212c can be arranged in an inverted V shape as shown in FIG. 2, instead of being arranged along the third straight line L3. Both the first impedance adjusting archwire S31a and the second impedance adjusting archwire 362a shown in 3 can be formed in at least one first signal line 161 and at least one second signal line 162 in the central area 212c. Therefore, the first impedance-regulating archwire S31a and the second impedance-regulating archwire 362a are also applicable to the foregoing embodiments, and are not limited to be used only in the display 300 of this embodiment.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of invention protection shall be subject to the scope of the attached patent application.

100, 200, 300: display 101, 102, 103, 104: insulating layer 110: substrate 111: display area 112, 212: non-display area 112a, 212a: the first area 112b, 212b: second area 120: scan line 130: data line 140: pixel array 141: control element 142: Pixel Components 151: First fan out routing 152: Second fan-out routing 161, 361: the first signal line 162, 362: second signal line 163: Third Signal Line 170: pad 180: drive element 190: conductive adhesive 212c: Central area 362a: Second impedance control bow line L1: first straight line L2: second straight line L3: third straight line D1: First direction D2: second direction G1: shortest distance S1, S31: the first line segment S2: second line segment S31a: The first impedance control bow line V1: The first transfer structure V2: The second transfer structure V11, V12: conductive pillar V13: Bridge wiring Z1: zone

FIG. 1A is a schematic top view of a display according to at least one embodiment of the invention. FIG. 1B is a schematic partial top view of the display in FIG. 1A in a non-display area. FIG. 1C is a schematic cross-sectional view along the line 1C-1C in FIG. 1B. FIG. 2 is a schematic partial top view of a display according to another embodiment of the present invention. FIG. 3 is a schematic partial top view of a display according to another embodiment of the present invention.

100: display

112: Non-display area

112a: The first area

112b: second area

151: First fan out routing

152: Second fan-out routing

161: The first signal line

162: The second signal line

163: Third Signal Line

170: pad

L1: first straight line

L2: second straight line

D1: First direction

D2: second direction

G1: shortest distance

S1: The first line segment

S2: second line segment

V1: The first transfer structure

V2: The second transfer structure

Claims (13)

A display includes: a substrate with a display area and a non-display area outside the display area; a plurality of parallel scanning lines arranged on the substrate and extending along a first direction; a plurality of parallel data Line, arranged on the substrate and extending along a second direction, wherein the first direction is not parallel to the second direction; a pixel array arranged on the substrate and located in the display area, wherein the The pixel array connects the scan lines and the data lines; a plurality of first fan-out traces are arranged on the substrate and located in the non-display area, wherein each of the first fan-out traces is electrically connected to the data lines One of them, and the extending direction of each of the first fan-out traces is not parallel to the first direction; a plurality of first signal lines arranged on the substrate and located in the non-display area, wherein each of the first signal lines The line includes: a first line segment connected to one end of the first fan-out wiring; a second line segment, wherein the first line segment and the second line segment are not on the same plane; a first transition structure connected The first line segment and the second line segment that are not on the same plane, wherein the first line segments and the second line segments all extend along the second direction; a plurality of pads are arranged on the substrate, And is located in the non-display area, wherein the second line segment of each of the first signal lines is electrically connected to one of the pads. The display according to claim 1, wherein the pads and The shortest distance between the first transition structures is greater than or equal to 300 microns, and the average distance between the pads and the first transition structures is greater than 500 microns. The display according to claim 2, wherein the shortest distance exists between at least one of the two outermost first transition structures and the pads. The display according to claim 1, wherein the first switching structures are not arranged along the first direction and the second direction. The display according to claim 1, wherein there is a shortest distance between at least one of the two outermost first switching structures and the pads, and any one of the first switching structures is connected to the pads. The distance between the pads is greater than or equal to the shortest distance. The display according to claim 5, wherein the non-display area has a first area and a second area, the first area is adjacent to the second area, and the first area and the second area are both along the first area. Arranged in a direction, the first signal lines are located in the first area and the second area, wherein the first transition structures located in the first area are arranged along a first straight line, and are located in the second area The first transition structures within are arranged along a second straight line, wherein the first straight line and the second straight line are not parallel, and the first straight line and the second straight line are not parallel to the first direction and the second straight line. square Towards. The display according to claim 5, wherein the non-display area has a first area, a second area, and a central area, the central area is located between the first area and the second area, and the first area, The central area and the second area are all arranged along the first direction. The first signal lines are located in the first area, the second area, and the central area, and the first signal lines are located in the first area. The first switching structures are arranged along a first straight line, the first switching structures located in the second area are arranged along a second straight line, and the first switching structures located in the central area are arranged along a The first direction is arranged, wherein the first straight line and the second straight line are not parallel, and the first straight line and the second straight line are not parallel to the first direction and the second direction. The display according to claim 1, further comprising: a plurality of second fan-out traces arranged on the substrate and located in the non-display area, wherein each of the second fan-out traces is electrically connected to one of the data lines ; And a plurality of parallel second signal lines are arranged on the substrate and located in the non-display area, wherein the second signal lines are respectively connected to one end of the second fan-out traces, and each of the second signal lines One of the pads is electrically connected. The display according to claim 8, wherein the non-display area has a first area, a second area, and a central area, and the central area The domain is located between the first area and the second area, and the first area, the central area, and the second area are all arranged along the first direction. The first signal lines are located in the first area, In the second area and the central area, at least one first line segment located in the central area has a first impedance control archline. The display according to claim 9, wherein the second signal lines are located in the first area, the second area, and the central area, wherein at least one second signal line located in the central area has a first 2. Impedance control bow line. The display according to claim 8, further comprising: a plurality of second switching structures respectively connected to the second line segments and the second signal lines; and a plurality of third signal lines respectively connected to the second signal lines Between the transfer structure and the pads. The display according to any one of claims 1 to 11, further comprising a driving element, wherein the driving element is installed on the pads. The display according to any one of claims 1 to 11, further comprising a conductive adhesive, wherein the conductive adhesive is distributed in an area between the first transfer structures and the pads, and covers each of the first transfer structures. At least a part of the two line segments and the pads.

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