TWI744004B - Method for minimizing divots at edges of shallow trench isolations - Google Patents

Abstract

A method for minimizing divots at edges of shallow trench isolations, including steps of providing a substrate with multiple active areas, an oxide layer on the active areas and shallow trench isolations between the active areas, and performing a wet etching process to remove the oxide layer, wherein the wet etching process is soaking the substrate in a completely still, non-flow etchant.

Description

Method for reducing edge depression of shallow trench isolation structure

The present invention relates to a semiconductor manufacturing process, and more specifically, it relates to a method for reducing divots at the edges of shallow trench isolation structures.

In the manufacturing process of semiconductor circuits below 250 nm, the traditional local oxidation of silicon (LOCOS) method is usually replaced by a shallow trench isolation method because of its bird's beak effect and surface unevenness. However, although the shallow trench isolation structure (STI) can enhance the integration of semiconductor devices, it also derives some problems that need to be solved in order to avoid the degradation of its electrical properties and the isolation performance of the devices.

In the conventional technology, as shown in FIG. 1, the pad oxide layer and the pad nitride layer on the active region 20 adjacent to the shallow trench isolation structure 10 are removed, and the wet etching process is performed to remove the subsequent active region 20 formed During the sacrificial oxide step, the edge portion of the shallow trench isolation structure 10 is susceptible to over-etching, resulting in edge divot 30 features. When the gate structure crosses the boundary of the shallow trench isolation structure 10, the gate conductor part will sink into the edge recess 30, causing the local electric field at this part to increase and prematurely inducing the transistor characteristics at the edge of the device, which will lead to The Id-Vg logarithmic curve in the subcritical region has a hump phenomenon. Furthermore, as the portion of the edge recess 30 expands, the gate material is likely to remain in the edge recess 30 during the subsequent gate fabrication.

The above phenomenon will become more and more as the size of semiconductor components shrinks and the channel width decreases. Increasingly, it will affect the critical voltage and drain saturation current of the device. Therefore, those skilled in the art still need to further improve the existing shallow trench isolation method to solve the conventional problem of the above-mentioned shallow trench isolation structure edge depression.

In view of the aforementioned conventional problem that the divot feature of the shallow trench isolation structure affects the electrical properties of the device, the present invention hereby proposes a novel semiconductor manufacturing process, which reduces the duration of the shallow trench isolation process by changing the wet etching process. The effect of the etching process on the shallow trench isolation structure.

The object of the present invention is to provide a method for reducing the edge depression of a shallow trench isolation structure. The steps include providing a substrate with a plurality of active regions, an oxide layer located on the active regions, and a gap between the active regions. Between the shallow trench isolation structure and performing a wet etching process to remove the oxide layer, wherein the wet etching process is to immerse the substrate in a completely static and non-flowing etching solution.

Such objects and other objects of the present invention should become more apparent after readers have read the detailed description of the preferred embodiments described below with various illustrations and drawings.

10: Shallow trench isolation structure

20: active zone

30: Sunken edges

100: base

102: pad oxide layer

104: pad nitride layer

106: active area

106a: doped area

108: Ditch

110: Shallow trench isolation structure

111: Groove

112: Sacrificial oxide layer

114: sunken edge

116: by-product

d1, d2: depth

This specification contains drawings and constitutes a part of this specification in the text, so that readers can have a further understanding of the embodiments of the present invention. These figures depict some embodiments of the present invention and together with the description herein, explain the principles. In these figures: Figure 1 is a schematic cross-sectional view of a divot of a shallow trench isolation structure in the prior art; Figures 2-9 are diagrams of a method for fabricating a shallow trench isolation structure according to a preferred embodiment of the present invention A schematic cross-sectional view of the process steps; and Figure 10 is a schematic cross-sectional view of the difference between the conventional technology and the manufacturing method of the present invention in the recessed part of the edge picture.

It should be noted that all the illustrations in this manual are illustrations in nature. For clarity and convenience of illustration, the parts in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the figures The same reference symbols will be used to indicate corresponding or similar element features in modified or different embodiments.

Now, exemplary embodiments of the present invention will be described in detail below, which will illustrate the described features with reference to the accompanying drawings so that readers can understand and achieve technical effects. Readers will understand that the description in the text is only done by way of example, and is not intended to limit the case. The various embodiments of this case and various features in the embodiments that do not conflict with each other can be combined or re-arranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to this case are understandable to those skilled in the art, and are intended to be included in the scope of this case.

Readers should be able to easily understand that the meanings of "on", "on" and "on" in this case should be interpreted in a broad way, so that "on" not only means "directly on" "Something is "on" but also includes something "on" with the meaning of intervening features or layers in between, and "on" or "above" not only means "on" or "on" something The meaning of "above" can also include the meaning of "above" or "above" something without intervening features or layers (that is, directly on something).

In addition, space-related terms such as "below", "below", "lower", "above", "upper" and other space-related terms may be used herein to describe one element or feature and another for convenience of description. The relationship of one or more elements or features is as shown in the drawings.

As used herein, the term "substrate" refers to a material on which subsequent materials are added. The substrate itself can be patterned. The material added on the top of the substrate can be patterned or can Keep it unpatterned. In addition, the substrate may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of the lower or upper structure, or may have a range smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or non-homogeneous continuous structure whose thickness is less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. The layers can extend horizontally, vertically, and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers on, above, and/or below it. The layer may include multiple layers. For example, the interconnection layer may include one or more conductor and contact layers (where contacts, interconnection lines, and/or vias are formed) and one or more dielectric layers.

Now the following embodiments will illustrate the manufacturing method of the shallow trench isolation structure of the present invention based on the cross-sectional structure shown in FIG. 2 to FIG. 9. It should be noted that the focus of the present invention is to explain and solve the problem of divot at the junction of the shallow trench isolation structure (STI) and the active area. In order to avoid blurring the focus, only the shallow trench isolation structure and the active area are shown in the figure. Other components, such as gates, contacts, and metal wires, which will be formed in the semiconductor manufacturing process, are not shown in the figure.

First, referring to Figure 2, the semiconductor manufacturing process of the present invention starts from the substrate. First, a substrate 100 is provided, such as a p-type doped single crystal silicon substrate, which can be divided into different regions, such as logic regions and memory cell regions. Basically, each different area will define individual active areas for its components or functional parts, and separate these active areas by fabricating shallow trench isolation structures. In order to define the active region, a pad oxide layer 102 and a pad nitride layer 104 are first formed on the substrate 100 in sequence. The material of the pad oxide layer 102 is silicon oxide, which can be formed by thermal oxidation, and the material of the pad nitride layer 104 is silicon nitride, which can be formed by any available deposition method. Among them, the pad oxide layer 102 is used as a stress buffer layer between the pad nitride layer 104 and the substrate 100, and can also be used as an etching stop layer in a subsequent process. The pad nitride layer 104 It will be used as a polishing stop layer in the subsequent manufacturing process.

Please refer to Figure 3. After the pad oxide layer 102 and the pad nitride layer 104 are formed, a photolithography process is then performed to pattern the substrate 100, the pad oxide layer 102, and the pad nitride layer 104 to form a plurality of active regions separated by trenches 108. The photolithography process can be an anisotropic etching process, such as a reactive ion etching (RIE) process. The steps include first forming a hard mask layer on the pad nitride layer 104 and a photoresist defining an active region pattern. (Not shown), then use the photoresist as an etching mask to etch the hard mask layer to transfer the active area pattern to the hard mask layer, and finally use the hard mask layer as an etching mask to etch the underlying substrate 100 , The pad oxide layer 102 and the pad nitride layer 104, thus forming trenches 108 and active regions 106 defined by the trenches 108.

Please refer to Figure 4. After the trench 108 is formed and the active region 106 is defined, then a dielectric material is filled in the trench 108 to form the shallow trench isolation structure 110. The filled dielectric material can be tetraethoxysilane (TEOS) or undoped silica glass (USG), which can be deposited through a high-density plasma chemical vapor deposition (HDP-CVD) process and fill each trench 108. Afterwards, a chemical mechanical planarization (CMP) process is performed using the pad nitride layer 104 as a polishing stop layer to remove the excess dielectric material above the height of the pad nitride layer 104 and the hard mask that may be formed in the previous steps In this way, a shallow trench isolation structure 110 located only in the trench 108 is formed.

Please refer to Figure 5. After the shallow trench isolation structure 110 is formed, the pad nitride layer 104 between the shallow trench isolation structure 110 is then removed. This can be achieved by a wet etching process using hot phosphoric acid, which is selective to silicon nitride, as an etching solution. For it. After the pad nitride layer 104 is removed, the shallow trench isolation structure 110 appears to protrude from the substrate surface, and a groove 111 is formed therebetween to expose the pad oxide layer 102 underneath.

In some embodiments, the pad oxide layer 102 is removed and a new sacrificial oxide layer is formed to play a role in the subsequent manufacturing process. Please refer to Figure 6. After the pad nitride layer 104 is removed, the pad oxide layer 102 exposed between the shallow trench isolation structures 110 is then removed, which can be etched by using diluted hydrofluoric acid (HF), which is selective to silicon oxide. Liquid wet etching process to avoid The bottom 100 causes damage. Since under normal circumstances, the shallow trench isolation structure 110 also uses silicon oxide as the main material, the wet etching process for removing the pad oxide layer 102 will also remove part of the surrounding shallow trench isolation in an isotropic manner. Structure 110. Therefore, after the wet etching process, in addition to the pad oxide layer 102 being removed to expose the underlying substrate 100, the corner edges of the shallow trench isolation structure 110 protruding above the substrate 100 will also be etched as shown in the figure. In this step, it is possible to produce slight divot defect features.

Please refer to Figure 7. After the pad oxide layer 102 is removed, a new sacrificial oxide layer 112 will be formed on the substrate 100 to remove damages and defects on the surface of the substrate 100, which is helpful for the subsequent generation of a high-quality gate oxide layer and serves as a gate oxide layer. The barrier layer avoids the channel tunneling effect during the subsequent ion implantation process. The sacrificial oxide layer 112 can be formed by a rapid thermal oxidation process or an in-situ vapor generation process, and it will only be formed on the surface of the exposed substrate 100.

Please refer to Figure 8. After the sacrificial oxide layer 112 is formed, an ion implantation process is performed to define a predetermined doped region 106a in each active region 106, for example, phosphorous ions or arsenic ions are implanted in a p-type doped single crystal silicon substrate To form an n-type doped region or well region, which may include a high-temperature furnace process to diffuse ions and temper to repair broken bonds in the lattice.

Please refer to Figure 9. After the formation of the doped region 106a, similar to the step of removing the pad oxide layer 102, a wet etching process is performed to remove the sacrificial oxide layer 112, which can use diluted hydrofluoric acid (HF), which is selective to silicon oxide. It is a wet etching process of an etching solution to avoid damage to the underlying active area substrate 100. Similarly, this wet etching process will also remove part of the surrounding shallow trench isolation structure 110 made of silicon oxide. Therefore, it is possible to generate or exacerbate the existing divot defect features in this step.

Next, please refer to FIG. 10, which is a schematic cross-sectional view of the difference between the conventional technology and the manufacturing method of the present invention in the recessed portion of the edge. As mentioned in the foregoing description, since the shallow trench isolation structure 110 and the pad oxide layer 102/sacrificial oxide layer 112 are made of silicon oxide, the above-mentioned oxide layer removal step cannot be avoided. Ground-free will remove the non-predetermined part of the shallow trench isolation structure 110, resulting in the defect of the edge depression 114 at the junction of the shallow trench isolation structure 110 and the active region 106 as shown in the figure. This edge depression 114 will cause subsequent formation of components The electrical hump phenomenon occurs and affects the critical voltage (Vt) and drain saturation current (Ids) of the device. Especially when the shallow trench isolation structure 110 and the pad oxide layer 102/sacrificial oxide layer 112 are respectively formed by different processes such as CVD and thermal oxidation, the wet etching process for removing the oxide layer has an etching selection ratio of the two (definition Because the etching rate of the wet etching process to the shallow trench isolation structure/the etching rate of the wet etching process to the oxide layer) will become larger, it is not easy to control the parameters and time of the etching process, so that the wet etching process will remove more The shallow trench isolation structure 110 causes the height difference between the edge recess 114 and the surrounding base surface to increase.

In order to solve the above problems, the present invention changes the wet etching process for removing the oxide layer. During the wet etching process, the substrate 100 (such as a wafer) is immersed in an etching solution (such as diluted hydrofluoric acid) so that the etching solution Keeping completely still and not flowing, this is different from the conventional wet etching process, which opens the overflow mode so that the etching solution circulates in the etching tank differently. As shown in Figure 10, the left half of Figure 10 is a schematic diagram of the prior art in which the overflow mode is turned on to allow the etching solution to circulate. From the figure, it can be seen that the pad oxide layer 102/sacrificial oxidation is in the overflow mode. The etching process by-product 116 on the surface of the layer 112 and the shallow trench isolation structure 110, such as tetrafluorosilicic acid, hexafluorosilicic acid or water, will be quickly taken away by the etching solution under the overflow circulation action, like the arrow in the figure The directions are shown. Such by-products 116 have the effect of protecting the surface during the wet etching process. Therefore, in an environment where the by-products are removed from the etched surface at a high speed, the shallow trench isolation structure 110 is susceptible to over-etching, which makes the defect enlargement of the edge recess 114 aggravated.

On the other hand, in the embodiment of the present invention, as shown in the right half of Figure 10, the etching solution in a completely static state will not take away the by-products 116 generated on the etching surface, and the by-products 116 will only pass through the natural The diffusion power leaves or approaches the etched surface, as shown in the direction of the arrow in the figure. In this mode, the by-product 116 is easier to accumulate on the etching surface, especially the edge recess 114, so that the etching rate of this portion becomes slower due to the shielding of the by-product 116. In this way, the impact of the wet etching process on shallow trenches can be reduced The etching selection ratio of the trench isolation structure 110 and the pad oxide layer 102/sacrificial oxide layer 112 (the etching rate of the wet etching process to the shallow trench isolation structure/the etching rate of the wet etching process to the oxide layer) makes the process parameters better Control, minimize or even avoid the formation of the recess 114 at the edge of the shallow trench isolation structure 110. It can be seen that the depth d2 of the edge recess 114 formed by the method of the present invention is smaller than the depth d1 of the edge recess 114 formed by the conventional method.

In addition, in other embodiments, in addition to not opening the etching solution overflow circulation during the wet etching process, some methods can also be used to additionally reduce the etching solution disturbance during the process, such as installing specific guide fins in the etching bath. Soothes turbulence and so on. This type of approach can help reduce the edge depression of the shallow trench isolation structure.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

102: pad oxide layer

106: active area

110: Shallow trench isolation structure

112: Sacrificial oxide layer

114: sunken edge

116: by-product

d1, d2: depth

Claims (7)

A method for reducing the edge depression of a shallow trench isolation structure includes: providing a substrate with a plurality of active regions, an oxide layer located on the active regions, and a shallow trench isolation structure between the active regions; And performing a wet etching process to remove the oxide layer, wherein the wet etching process is to immerse the substrate in a completely static and non-flowing etching solution. The method for reducing the edge depression of the shallow trench isolation structure as described in item 1 of the scope of patent application, wherein the etching solution is diluted hydrofluoric acid. The method for reducing the edge depression of the shallow trench isolation structure as described in the first item of the scope of patent application, wherein the etching selectivity ratio of the etching solution to the oxide layer and the shallow trench isolation structure in the wet etching process is lower than that of the etching solution in the flow of the etching solution. The etching selection ratio of the oxide layer and the shallow trench isolation structure in the state of, wherein the etching selection ratio is the etching rate of the wet etching process to the shallow trench isolation structure/the etching rate of the wet etching process to the oxide layer. The method for reducing the edge depression of a shallow trench isolation structure as described in claim 1, wherein the oxide layer is a pad oxide layer, and the steps of forming the active regions and the shallow trench isolation structures include: providing the substrate, and The pad oxide layer and a pad nitride layer are sequentially formed on the substrate; and a photolithography process is performed to pattern the substrate, the pad oxide layer, and the pad nitride layer to form a plurality of active regions separated by trenches Fill the trenches with dielectric materials to form the shallow trench isolation structures; and remove the pad nitride layer and the pad oxide layer. The method for reducing the edge depression of the shallow trench isolation structure as described in the first item of the scope of patent application, wherein the oxide layer is a sacrificial oxide layer. As described in item 5 of the scope of patent application, the method for reducing the edge depression of the shallow trench isolation structure further includes performing an ion implantation process after forming the sacrificial oxide layer to form doped regions in the active regions. The method for reducing the edge depression of the shallow trench isolation structure as described in item 6 of the scope of patent application further includes performing the wet etching process to remove the sacrificial oxide layer after the formation of the doped regions.

Images