TWI743915B - Chip on film package structure and display device - Google Patents

Abstract

The present invention discloses a chip on film package structure and a display device. The chip on film package structure includes a thin film substrate, a chip, and a first heat dissipation element. The thin film substrate has a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface of the thin film substrate and is electrically connected to the thin film substrate. The first heat dissipation element is disposed on the first surface of the thin film substrate and completely covers the chip. The first heat dissipation element has a plurality of through holes located on the periphery of the chip.

Description

Film-on-chip packaging structure and display device

The present invention relates to a packaging structure, in particular to a chip on film (COF) packaging structure and a display device using the chip on film packaging structure.

In semiconductor packaging technology, the types can be roughly divided into Tape Carrier Package (TCP) packaging, Chip On Film (COF) packaging and Chip On Glass (COG) packaging, etc. In the third category, the mainstream packaging technology was originally TCP. However, due to the continuous high-density technology development, COF packaging using flip-chip bonding has replaced TCP's Tape Automated Bonding (TAB), making the chip and flexible substrate extremely compatible. High-density bonding, and due to the development of packaging and testing technology toward wafer particle size reduction and fine pitch (Fine Pitch) processes, COF packaging has gradually replaced TCP packaging and has become the mainstream.

Generally speaking, the COF packaging structure is flexible. Therefore, in the general application of the COF packaging structure, in order to match the shape, size and installation space of the electronic device, it is often the case that the COF packaging structure is bent.

The purpose of the present invention is to provide a thin film on chip package structure and a display device, which can not only make the bending of the thin film on chip package structure easier, but also reduce the thermal stress of the high heat area to achieve the requirement of the maximum heat dissipation area.

To achieve the above objective, a chip-on-film package structure according to the present invention includes a film substrate, a chip, and a first heat sink. The film substrate has a first surface and an opposite to the first surface A second surface. The chip is arranged on the first surface of the film substrate and is electrically connected to the film substrate. The first heat dissipation element is arranged on the first surface of the film substrate and completely covers the chip, and the first heat dissipation element has a plurality of through holes located at the periphery of the chip.

In one embodiment, the film substrate is a polyimide substrate.

In one embodiment, in the direction perpendicular to the first surface, the through holes do not overlap with the wafer.

In one embodiment, the wafer has a width along a first direction, and the shortest distance of the two through holes located on opposite sides of the wafer along the first direction is greater than or equal to the width.

In an embodiment, the first direction is parallel to the long axis direction of the wafer.

In one embodiment, a second direction is perpendicular to the first direction, and the second direction is parallel to the long axis direction of the wafer.

In one embodiment, the first heat sink has a turning portion adjacent to the chip, and at least a part of the through hole is located at the turning portion.

In one embodiment, the shape of the through hole is a circle, an ellipse circle, a polygon, or an irregular shape, or a combination thereof.

In an embodiment, the first heat dissipation element includes a substrate, a first adhesive layer, a thermally conductive layer, a first metal layer, a second adhesive layer, a second metal layer, and a third adhesive layer. An adhesive layer, a thermal conductive layer, a first metal layer, a second adhesive layer, a second metal layer, and a third adhesive layer are sequentially arranged on the substrate.

In one embodiment, the first adhesive layer, the second adhesive layer, or the third adhesive layer is a graphene adhesive film.

In one embodiment, the material of the thermal conductive layer includes graphene, artificial graphite, natural graphite, carbon nanotubes, aluminum oxide, boron nitride, or zinc oxide, or a combination thereof.

In one embodiment, the first metal layer or the second metal layer is a metal ion deposition layer or a metal sheet.

In an embodiment, the chip-on-film package structure further includes a second heat dissipation element, which is disposed on the second surface of the film substrate, and the position of the second heat dissipation element corresponds to the chip.

To achieve the above objective, a display device according to the present invention includes a display panel and the above-mentioned chip-on-film package structure, and the chip-on-film package structure is electrically connected to the display panel.

Based on the above, in the film-on-chip package structure and display device of the present invention, the chip is disposed on the surface of the film substrate and electrically connected to the film substrate, and the first heat sink is disposed on the surface of the film substrate and completely Covering the chip, and the first heat dissipating element has a structure design with multiple through holes located at the periphery of the chip. In addition to making it easier to bend the film-on-chip package structure, it can also quickly conduct heat during the operation of the chip and dissipate it to the outside world. At the same time, the thermal stress in the high-heat area can be reduced to achieve the maximum heat dissipation area.

In addition, in an embodiment of the present invention, the shortest distance along a direction of any two through holes located on opposite sides of the chip may be greater than or equal to the width of the chip in that direction; at least a part of the through holes are located in the first heat sink. The structural design of the turning part of the first heat sink, when the air in the gap between the chip and the film substrate is thermally expanded, the hot air can be discharged through the through hole, thereby preventing the first heat sink from deforming or even separating from the chip Therefore, the film-on-chip package structure and the display device have excellent heat dissipation performance and structural reliability.

1,1a,1b,1c,1d,22: Thin film flip chip package structure

11,221: Film substrate

12,222: chips

13,223: The first heat sink

131: Substrate

132: The first adhesive layer

133: Thermal Conductive Layer

134: The first metal layer

135: second adhesive layer

136: second metal layer

137: Third Adhesive Layer

14: The second heat sink

2: display device

21: display panel

211: display surface

212: Back

213: side

23: Control circuit board

A-A: Cutting line

d: width

D1: First direction

D2: second direction

D3: Third party

G: gap

O: Through hole

P: flat part

S1: First surface

S2: second surface

T: Turning part

FIG. 1A is a schematic top view of a chip-on-film package structure according to a preferred embodiment of the present invention.

FIG. 1B is a schematic cross-sectional view of the chip-on-film package structure shown in FIG. 1A along the A-A cutting plane.

1C is a schematic cross-sectional view of the first heat sink of the chip-on-film package structure of FIG. 1B.

2A is a schematic cross-sectional view of a chip-on-film package structure according to different embodiments of the present invention.

2B and FIG. 2C are schematic top views of the chip-on-film package structure according to different embodiments of the present invention, respectively.

2D is a schematic cross-sectional view of a chip-on-film package structure according to different embodiments of the present invention.

FIG. 3 is a schematic diagram of a display device according to an embodiment of the invention.

Hereinafter, referring to related drawings, the structure of the chip-on-film package and the display device having the chip-on-film package structure according to some embodiments of the present invention will be described, in which the same components will be described with the same reference signs.

The size (length, width, or height) and proportions of the components appearing in the following figures only illustrate the relationship between the components, and have nothing to do with the size and proportion of the real components. In addition, the drawings of the following embodiments define a first direction D1, a second direction D2, and a third direction D3, where the first direction D1 is perpendicular to the second direction D2, and the third direction D3 is the same as the first directions D1 and D3, respectively. The second direction D2 is vertical.

Please refer to FIGS. 1A and 1B. FIG. 1A is a schematic top view of a chip on film (COF) package structure according to a preferred embodiment of the present invention, and FIG. 1B is the chip on film (COF) package shown in FIG. 1A A schematic cross-sectional view of the structure along the AA cut line.

The chip-on-film package structure 1 includes a film substrate 11, a chip 12 and a first heat sink 13. In this embodiment, the second direction D2 is parallel to the long axis direction of the wafer 12 (the second direction D2 is parallel to the extending direction of the long side of the wafer 12), and the extending direction of the film substrate 11 is parallel to the first direction D1 and the first direction. The plane formed by the two directions D2, and the third direction D3 is perpendicular to the upper surface of the film substrate 11, and perpendicular to the first direction D1 and the second direction D2, respectively.

The film substrate 11 has a first surface S1 (upper surface) and a second surface S2 (lower surface) opposite to the first surface S1. The film substrate 11 is a flexible substrate with flexibility and can be a thermoplastic material. Its material can include organic polymer materials, such as but not limited to polyimide (PI), polyethylene (PE), and polyvinyl chloride. (Polyvinylchloride, PVC), polystyrene (PS), acrylic (acrylic), fluoropolymer, polyester or nylon, or other materials. The film substrate 11 of this embodiment is a polyimide (PI) substrate as an example. In some embodiments, the first surface S1 and/or the second surface S2 of the film substrate 11 may also have a plurality of wires (not shown), one end of the wire is electrically connected to the chip 12, and the other end of the wire is away from the chip 12 Since the chip 12 extends in the direction of 12, the chip 12 can transmit signals through wires.

The chip 12 is an integrated circuit (IC), which is disposed on the first surface S1 of the film substrate 11 and is electrically connected to the film substrate 11. In this embodiment, the chip 12 is Flip Chip Bonding (Flip Chip Bonding) on the film substrate 11 to become a chip on film (COF). In some embodiments of the display device, the chip 12 may be, for example, a data drive IC or a scan drive IC of the display device, or an IC that integrates data drive and scan drive functions, and is not limited to this. In different embodiments, The chip 12 may also have other driving or control functions.

The first heat sink 13 is disposed on the first surface S1 of the film substrate 11 and completely covers the wafer 12. In other words, the first heat sink 13 can completely cover the top surface of the chip 12 away from the film substrate 11. Therefore, when the flip-chip package structure 1 is viewed from above, only the first heat sink 13 and the film substrate 11 can be seen. Among them, the first heat dissipation member 13 is a heat-conducting/heat-dissipating film, which can quickly guide the heat generated during the operation of the chip 12 and dissipate it to the outside.

Please refer to FIG. 1C first, which is a schematic cross-sectional view of the first heat sink 13 in FIG. 1B. In this embodiment, the first heat dissipation element 13 includes a substrate 131, a first adhesive layer 132, a thermally conductive layer 133, a first metal layer 134, a second adhesive layer 135, a second metal layer 136, and A third adhesive layer 137. The substrate 131 is a heat-resistant substrate and can be an insulating protective layer, and the first adhesive layer 132, the thermally conductive layer 133, the first metal layer 134, the second adhesive layer 135, the second metal layer 136, and the third adhesive layer 137 are based on It is sequentially arranged on the substrate 131 (inverted state in FIG. 1C), and the first heat sink 13 is adhered to the chip 12 and the film substrate 11 through the third adhesive layer 137. In some embodiments, the first heat dissipation member 13 may not include the third adhesive layer 137.

The thermally conductive layer 133 may be a thermally conductive/heat-dissipating film, and its material may include, for example, but not limited to, graphene, artificial graphite, natural graphite, carbon nanotubes, aluminum oxide, boron nitride, or zinc oxide, or a combination thereof. Therefore, the thermally conductive layer 133 may be a graphene thermally conductive film, a graphite thermally conductive film, a carbon nanotube thermally conductive film, an aluminum oxide thermally conductive film, a boron nitride thermally conductive film, or a zinc oxide thermally conductive film, or a combination thereof. The material of the thermal conductive layer 133 in this embodiment is based on graphene, so that the thermal conductive layer 133 is a graphene thermal film (GTF). Through the thermal guiding effect of graphene, the thermal conductive layer 133 can have good heat conduction and heat dissipation effects in the xy direction (that is, the plane formed by the directions D1 and D2), so that the first heat sink 13 also has a good xy direction. Heat conduction and heat dissipation effect.

厚度

3nm)，而各石墨烯微片的片徑可大於等於4.5微米，且小於等於25微米(4.5μm

片徑

25μm)。此外，前述 的膠材可例如但不限於為壓感膠(pressure sensitive adhesive,PSA)，其材料可例如包括橡膠系、壓克力系、或矽利康系、或其組合；而化學構成可為橡膠類、丙烯酸類、或有機硅類、或其組合。由於本實施例的第一黏著層132、第二黏著層135及第三黏著層137具有黏性，並且還具有可協助導熱的石墨烯微片，因此除了具有黏著功能外，還可協助熱能的傳導而提升導熱及散熱效能。 The first adhesive layer 132, the second adhesive layer 135, and/or the third adhesive layer 137 may be double-sided tape; in some embodiments, the first adhesive layer 132, the second adhesive layer 135, and/or the third adhesive layer 137 can be a thermally conductive adhesive with thermal conductivity. The first adhesive layer 132, the second adhesive layer 135, and the third adhesive layer 137 in this embodiment are respectively graphene adhesive films as examples. The graphene adhesive film may include a plurality of graphene microchips and a glue material, and the graphene microchips are mixed in the glue material. In some embodiments, the thickness of the graphene microplates may be greater than or equal to 0.3 nanometers (nm) and less than or equal to 3 nanometers (0.3nm).

thickness

3nm), and the diameter of each graphene microchip can be greater than or equal to 4.5 microns, and less than or equal to 25 microns (4.5μm

Film diameter

25μm). In addition, the aforementioned adhesive material may be, for example, but not limited to, pressure sensitive adhesive (PSA). The material may include rubber, acrylic, or silicone, or a combination thereof; and the chemical composition may be Rubber-based, acrylic-based, or silicone-based, or a combination thereof. Since the first adhesive layer 132, the second adhesive layer 135, and the third adhesive layer 137 of this embodiment are adhesive and also have graphene microchips that can assist in heat conduction, in addition to the adhesive function, they can also assist in the heat transfer. Conduction to enhance heat conduction and heat dissipation performance.

In addition, the material of the first metal layer 134 and the second metal layer 136 may include metal materials or particles with high thermal conductivity, such as but not limited to copper, aluminum, iron, silver, gold, or other high thermal conductivity metal materials or particles. This has a good heat guiding effect in the Z-axis direction (that is, the D3 direction). In some embodiments, the first metal layer 134 or the second metal layer 136 may be a metal ion deposition layer or a metal sheet. In some embodiments, a metal ion deposition layer may be formed by electrodeposition (electrodeposition); in some embodiments, for example, electroplating, chemical vapor deposition (Chemical Vapor Deposition, CVD) or physical vapor deposition (Physical Vapor Deposition) may be used. Vapor Deposition, PVD), or other appropriate methods to form a metal ion deposition layer. In this embodiment, the first metal layer 134 is a metal ion deposition layer, and the second metal layer 136 is a thin metal sheet as an example. Of course, in different embodiments, the first metal layer 134 may be a thin metal sheet. , The second metal layer 136 may be a metal ion deposition layer; or, the first metal layer 134 and the second metal layer 136 are both metal ion deposition layers; or, the first metal layer 134 and the second metal layer 136 are both thin Metal pieces. The aforementioned metal ion deposition layer can not only have a good thermal guiding effect in the Z-axis direction (ie D3 direction), but also has the characteristics of being easy to bend and not easy to break, and can protect the first heat sink 13 from damage caused by bending. The resulting thermal energy transfer is interrupted and the heat dissipation effect is reduced. In addition, the metal sheet can also have a good heat guiding effect in the Z-axis direction (that is, the D3 direction).

Please refer to FIG. 1A and FIG. 1B again. As shown in FIG. 1A and FIG. Wherein, the shape of the through hole O can be a circle, an ellipse circle, a polygon, or an irregular shape, or a combination thereof. In this embodiment, the periphery of the chip 12 has six through holes O located on opposite sides of the long side of the chip 12, and the shapes of the through holes O are respectively quadrangular as an example. In addition, in this embodiment, in the direction D3 perpendicular to the first surface S1, each through hole O does not overlap with the wafer 12 at all, and the sidewall of the through hole O is also aligned with the sidewall of the wafer 12.

In conclusion, in the film-on-chip package structure 1 of this embodiment, since the temperature of the chip 12 during operation is quite high (for example, more than 100°C, even up to 200°C), the first heat sink 13 completely Covering the chip 12 can quickly conduct the thermal energy of the chip 12 to dissipate to the outside. In addition, in the general application of the film-on-chip package structure 1, in order to match the shape, size and installation space of the electronic device, it is often the case that the film-on-chip package structure 1 is bent. Therefore, the first heat sink is adopted in this embodiment. 13 has a plurality of through-holes O located on the periphery of the chip 12, which can make the bending of the whole film-on-chip package structure 1 easier, and at the same time can reduce the thermal stress of the high-heat area to achieve the requirement of the maximum heat dissipation area.

In addition, traditionally, in the process of attaching the heat dissipating material to the film substrate and covering the chip, it is difficult to make the heat dissipating material and the chip closely adhere to each other. Therefore, there is often an air gap between the chip and the heat dissipating material. ) (For example, the gap G between the first heat sink 13, the chip 12 and the film substrate 11 in FIG. 1B), so in the subsequent thermal process or chip operation, the air trapped between the chip and the heat sink will be caused by Thermal expansion may cause the heat dissipation material to separate from the chip, reducing the reliability of the chip package. Furthermore, since the thermal conductivity of air is quite low, the air trapped between the chip and the heat dissipation material will also affect the efficiency of the heat generated by the chip to the heat dissipation material.

Therefore, in the film-on-chip package structure 1 of this embodiment, the chip 12 has a width d along the first direction D1, and the shortest distance between any two through holes O located on opposite sides of the chip 12 along the first direction D1 It must be at least equal to ("at least equal to" means that it can be greater than or equal to) the width d; in addition, the first heat dissipation member 13 has a turning portion T adjacent to the chip 12, and the through hole O (may have only one, more or all through holes) At least a part of the hole O) is located at the turning portion T. Here, it is taken as an example that the shortest distance between the two through holes O located on the opposite sides of the chip 12 along the first direction D1 is equal to the width d, and all the through holes O are located at the turning portion T of the first heat sink 13. In some embodiments, the shortest distance of any two through holes O located on opposite sides of the wafer 12 along the first direction D1 may be slightly larger than the width d to ensure that the first heat sink 13 can cover the entire top surface of the wafer 12. The size of the through hole O is not limited, as long as the hot air in the gap G can be discharged.

Therefore, the first heat sink 13 has a plurality of through holes O, and the shortest distance of any two through holes O located on opposite sides of the chip 12 along the first direction D1 is at least equal to the width d, and at least a part of the through holes O are located The design of the turning portion T of the first heat dissipating member 13 can reserve a covering position of the chip 12 on the first heat dissipating member 13 to conduct the thermal energy generated by the chip 12 to the outside. When the air in the gap G is heated and expanded At this time, the hot air can also be discharged through the through hole O at least partly located in the turning portion T, thereby preventing the deformation of the first heat dissipating member 13 or even the separation from the chip 12, so that the film-on-chip package structure 1 has excellent heat dissipation. Performance and structural reliability.

In addition, please refer to FIG. 2A to FIG. 2D, where FIG. 2A and FIG. 2D are respectively cross-sectional schematic diagrams of the thin film flip chip package structure of different embodiments of the present invention, and FIG. 2B and FIG. 2C are respectively different embodiments of the present invention. A schematic top view of the film-on-chip package structure of.

As shown in FIG. 2A, the chip-on-film package structure 1a of this embodiment and the chip-on-chip package structure 1 of the previous embodiment have substantially the same component composition and connection relationship of the components. The difference is that in the chip-on-film package structure 1a of this embodiment, not all the through holes O are located at the turning portion T. Here, in addition to the turning portion T, the first heat sink 13 of this embodiment also has a flat portion P, which refers to the portion of the first heat sink 13 attached to the first surface S1 of the film substrate 11. , And a part of the through hole O is located at the turning portion T, and another part of the through hole O is located at the flat portion P.

In addition, as shown in FIG. 2B, the chip-on-film package structure 1b of this embodiment and the chip-on-chip package structure 1 of the previous embodiment have substantially the same component composition and connection relationship of the components. The difference is that in the chip-on-film package structure 1b of this embodiment, the first direction D1 is parallel to the long axis direction of the chip 12. In addition, the number of through holes O in this embodiment is two, and they are located on opposite sides of the short side of the wafer 12.

In addition, as shown in FIG. 2C, the chip-on-chip package structure 1c of the present embodiment has substantially the same component composition and connection relationship of the components of the chip-on-chip package structure 1 of the previous embodiment. The difference is that in the thin film on chip package structure 1c of this embodiment, the number of through holes O is eight, six of which are located on opposite sides of the long side of the chip 12, and two of them are located on the opposite side of the short side of the chip 12. On both sides.

In addition, as shown in FIG. 2D, the chip-on-film package structure 1d of this embodiment and the chip-on-chip package structure 1 of the previous embodiment have substantially the same component composition and connection relationship of the components. The difference lies in that, in the chip-on-film package structure 1d of this embodiment, a second heat dissipation member 14 is further included. The second heat dissipation member 14 is disposed on the second surface S2 of the film substrate 11, and the second heat dissipation member 14 The setting position corresponds to the wafer 12. The structure and material of the second heat dissipation element 14 and the first heat dissipation element 13 may be the same or different, which is not limited. Specifically, in order to assist in dissipating the heat generated by the chip 12 to the outside, a second heat sink 14 may be provided on the second surface S2 of the film substrate 11 corresponding to the position directly below the chip 12, and the second heat sink 14 (And the first heat sink 13) the area projected to the film substrate 11 is larger than the area of the chip 12 projected to the film substrate 11, thereby achieving a better heat dissipation effect. The second heat sink 14 of this embodiment can also be applied to the above-mentioned embodiments of the above-mentioned chip-on-film packaging structures 1a, 1b, and 1c.

Please refer to FIG. 3, which is a schematic diagram of a display device according to an embodiment of the present invention. The display device 2 includes a display panel 21 and a chip on film package structure 22, and the display panel 21 is connected to the chip on film package structure 22. The display panel 21 can be a liquid crystal display panel (LCD) or an electroluminescence display panel (for example, an organic light emitting diode display panel, OLED), and is not limited. The display panel 21 has a display surface 211, a back surface 212 opposite to the display panel 21, and a side surface 213 connected to the display surface 211 and the back surface 212 respectively. One side of the chip-on-film package structure 22 is connected to the display panel 21 and may include a film substrate 221, a chip 222, and a first heat sink 223. Here, the thin film substrate 221 and the chip 222 can be a chip on film (COF), and the chip 222 can be, for example, a data driver IC or a scan driver IC of the display panel 21, or an IC that integrates data and scan driver functions, and is not limited . The chip-on-film package structure 22 of this embodiment can be one of the above-mentioned chip-on-film package structure 1, 1a~1d, or a variation thereof. For the specific technical content, please refer to the above-mentioned chip-on-film package structure 1, 1a~1d. The same components of, will not be explained here.

The film-on-chip package structure 22 of this embodiment also has a plurality of through holes O, which is easy to bend, and can also quickly conduct the heat energy of the chip 222 during operation to escape to the outside, and can also reduce the thermal stress in the high-heat area to achieve the maximum The need for heat dissipation area. When the chip-on-film package structure 22 is bent, the first heat dissipation member 223 covering the chip 222 can face the side surface 213 or the back surface 212 of the display panel 21. Here, the side surface 213 of the chip 222 and the first heat sink 223 facing the display panel 21 is taken as an example. In addition, the display device 2 of this embodiment may further include a control circuit board 23. The control circuit board 23 is connected to the other side of the film substrate 221 away from the display panel 21, so that the control circuit board 23 can pass through the film substrate 221 and the display panel 21. Electrical connection. The control circuit board 23 is, for example, but not limited to, a printed circuit board, and has a driving circuit for controlling the operation of the display panel 21 to drive or control the display panel 21 through the film substrate 221 and the chip 222.

In summary, in the film-on-chip package structure and display device of the present invention, the chip is disposed on the surface of the film substrate and is electrically connected to the film substrate, and the first heat sink is disposed on the surface of the film substrate and completely Covering the chip, and the first heat dissipating element has a structure design with multiple through holes located at the periphery of the chip. In addition to making it easier to bend the film-on-chip package structure, it can also quickly conduct heat during the operation of the chip and dissipate it to the outside world. At the same time, the thermal stress in the high-heat area can be reduced to achieve the maximum heat dissipation area.

In addition, in an embodiment of the present invention, the shortest distance in one direction through any two through holes located on opposite sides of the wafer is equal to or greater than the width of the wafer in that direction; at least a part of the through holes The structural design of the turning part of the first heat sink is designed so that when the air in the gap between the first heat sink, the chip and the film substrate is thermally expanded, the hot air can be discharged through the through hole, thereby preventing the first heat sink from deforming Or even the problem of separation from the chip, so that the film-on-chip packaging structure and the display device have excellent heat dissipation performance and structural reliability.

The above descriptions are merely illustrative and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the appended patent application.

1: Thin film flip chip package structure

11: Thin film substrate

12: chip

13: The first heat sink

A-A: Cutting line

d: width

D1: First direction

D2: second direction

O: Through hole

S1: First surface

S2: second surface

Claims (13)

A chip-on-film packaging structure includes: a film substrate having a first surface and a second surface opposite to the first surface; a chip disposed on the first surface of the film substrate and connected to the film substrate Electrically connected; and a first heat dissipating member disposed on the first surface of the film substrate and completely covering the chip, and the first heat dissipating member has a plurality of through holes located at the periphery of the chip, wherein the first heat dissipating member The heat dissipation element includes a substrate, a first adhesive layer, a thermally conductive layer, a first metal layer, a second adhesive layer, a second metal layer, and a third adhesive layer. The first adhesive layer and the thermally conductive layer , The first metal layer, the second adhesive layer, the second metal layer, and the third adhesive layer are sequentially disposed on the substrate. The chip-on-film package structure according to claim 1, wherein the film substrate is a polyimide substrate. The chip-on-film package structure according to claim 1, wherein, in a direction perpendicular to the first surface of the film substrate, each of the through holes does not overlap the chip. The chip-on-film package structure according to claim 1, wherein the first heat sink has a turning portion adjacent to the chip, and at least a part of the through hole is located at the turning portion. The chip-on-film package structure according to claim 1, wherein the chip has a width along a first direction, and the shortest distance of two through holes located on opposite sides of the chip along the first direction is greater than or equal to the width. The chip-on-film package structure according to claim 5, wherein the first direction is parallel to the long axis direction of the chip. The chip-on-film package structure according to claim 5, wherein a second direction is perpendicular to the first direction, and the second direction is parallel to the long axis direction of the chip. The chip-on-film package structure according to claim 1, wherein the shape of the through hole is a circle, an ellipse circle, a polygon, or an irregular shape, or a combination thereof. The film-on-chip package structure according to claim 1, wherein the first adhesive layer, the second adhesive layer, or the third adhesive layer is a graphene adhesive film. The thin film flip chip package structure according to claim 1, wherein the material of the thermally conductive layer includes graphene, artificial graphite, natural graphite, carbon nanotube, aluminum oxide, boron nitride, or zinc oxide, or a combination thereof. The thin film flip chip package structure according to claim 1, wherein the first metal layer or the second metal layer is a metal ion deposition layer or a metal sheet. The chip-on-film package structure according to claim 1, further comprising: a second heat dissipation element disposed on the second surface of the film substrate, and the position of the second heat dissipation element corresponding to the chip. A display device includes: a display panel; and the thin-film-on-chip package structure according to any one of claims 1 to 12, which is electrically connected to the display panel.

Images