TWI742855B - Gate driving device - Google Patents

Abstract

A gate driving device is provided. The gate driving device includes a plurality of gate drive units. An nth-stage gate drive unit charges a bias node during the first time interval. The nth-stage gate driving unit provides the nth-stage gate driving signal and the nth-stage replica signal during the second time interval, and prevents the voltage leakage of the bias node according to the nth-stage replica signal. In a third time interval that lags behind the second time interval, the nth-stage gate drive unit discharges the voltage value of the bias node. The second time interval lags behind the first time interval and the second time interval is separated from the first time interval by a default time length.

Description

Gate drive device

The present invention relates to a driving device, and more particularly to a gate driving device.

Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) have become the mainstream of modern display technology products. Compared with Poly-Si TFT, the display made of amorphous silicon thin film transistor (a-Si TFT) can reduce production cost, and can be fabricated on a large area glass substrate at low temperature, uniformly It has good performance and can increase the production rate.

With the concept of System-on-Glass (System-on-Glass, SOG) being put forward one after another, recently many products integrate the gate driving device in the display driving circuit on the glass substrate, that is, GOA (Gate Driver on Array) Circuit. GOA has many advantages. In addition to reducing the area of the display frame to achieve a narrow frame, it can also reduce the use of gate scan driver ICs, reduce the cost of purchasing ICs, and avoid the problem of disconnection during glass and IC bonding, so as to improve products Yield.

However, when displays are used in automotive products, they may encounter problems with long-term use and wide-ranging temperature operation, such as extreme low temperatures (for example, -40 degrees Celsius) and extreme high temperatures (for example, 70 degrees Celsius). From this, it can be seen that how to design a drive device with high reliability under extreme temperatures is one of the current development focuses of drive devices.

The present invention provides a gate drive device with high reliability under extreme temperatures.

The gate driving device of the present invention includes a plurality of gate driving units. The plurality of gate driving units are coupled in series. The n-th stage gate drive unit in the plurality of gate drive units includes a power supply circuit, an output circuit, and a bias control circuit. The power supply circuit is configured to charge the low bias voltage value of the bias node to the first bias voltage value according to the n-m-th level replica signal pair in the first time interval. The output circuit is coupled to the power supply circuit through the bias node, and is configured to provide the n-th gate drive signal and the n-th replica signal according to the bias node and the corresponding external clock during the second time interval. The second time interval is behind the first time interval, and the second time interval is separated from the first time interval by a preset length of time. The bias control circuit is coupled to the bias node. The bias control circuit has a first stabilizing node. The bias control circuit is configured to increase the voltage value of the bias node from the first bias value to the second bias value in the second time interval, and provide a stabilized voltage at the first stabilized node according to the n-th stage replica signal Value to prevent voltage leakage at the bias node. The bias control circuit pulls down the voltage value of the bias node to a low bias value in a third time interval that is behind the second time interval. n and m are respectively positive integers. n-m is greater than or equal to 1.

Based on the above, in the first time interval, the nth-stage gate driving unit charges the bias node according to the n-mth-stage replica signal. In the second time interval, the n-th gate driving unit provides the n-th gate driving signal and the n-th replica signal according to the bias voltage value of the bias node and the corresponding external clock. The second time interval is behind the first time interval, and the second time interval is separated from the first time interval by a preset length of time. Therefore, the bias node can be charged at an earlier point in time. In this way, the bias node of the gate driving device can reach a sufficient voltage under low temperature conditions. The n-th stage gate driving unit also provides a regulated voltage value in the second time interval according to the n-th stage replica signal to prevent voltage leakage at the bias node. In this way, the gate driving device can prevent voltage leakage at the bias node under high temperature conditions.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Part of the embodiments of the present invention will be described in detail in conjunction with the accompanying drawings. The reference symbols in the following description will be regarded as the same or similar elements when the same symbol appears in different drawings. These embodiments are only a part of the present invention, and do not disclose all the possible implementation modes of the present invention. To be more precise, these embodiments are only examples of the devices and methods within the scope of the patent application of the present invention.

Please refer to FIG. 1, which is a schematic diagram of a gate driving device according to a first embodiment of the present invention. In this embodiment, the gate driving device 100 includes a plurality of gate driving units coupled to each other in series. For example, among the plurality of gate driving units, the gate driving unit GU(n) of the nth stage will depend on the external clock CK1, the system high voltage VDD, and the (n-8)th stage replica signal ST(n). -8) Provide the n-th gate drive signal and the n-th replica signal ST(n). The (n-8)th stage replica signal ST(n-8) comes from the (n-8)th stage gate driving unit (not shown). The (n+1)th stage gate driving unit GU(n+1) will provide the (n+1)th stage based on the external clock CK2, the system high voltage VDD, and the (n-7)th )-Level gate drive signal G(n+1) and (n+1)-level replica signal ST(n+1), (n-7)-level replica signal ST(n-7) comes from (n- 7) Stage gate drive unit (not shown). So on and so forth.

Please refer to FIG. 2, which is a schematic circuit diagram of the n-th stage gate driving unit according to the first embodiment of the present invention. In this embodiment, the n-th stage gate driving unit GU(n) includes a power supply circuit 110, an output circuit 120, and a bias control circuit 130. The power supply circuit 110 charges the low bias voltage value (for example, -15 volts) of the bias voltage node A(n) according to the (nm)-th level replica signal ST(nm) in the first time interval. To the first bias value (for example, 15 volts, the present invention is not limited to this). The output circuit 120 and the power supply circuit 110 are coupled to the bias node A(n). The output circuit 120 provides an n-th stage gate driving signal G(n) and an n-th stage replica signal ST(n) according to the second bias value of the bias node A(n) and the external clock CK1. In this embodiment, the second time interval lags the first time interval, and the second time interval is separated from the first time interval by a preset time length. In this embodiment, the time length of the second time interval may be an integer multiple of the preset time length. The present invention is not limited to the preset time length. n and m are respectively positive integers, and n-m is greater than or equal to 1. In this embodiment, m is equal to 8, and the present invention is not limited to the value of m.

Incidentally, because the second time interval lags behind the first time interval and the second time interval is separated from the first time interval by a preset length of time. That is, the bias node A(n) can be charged at an earlier point in time. In this way, the bias node A(n) of the gate driving device 100 can reach a sufficient voltage under low temperature conditions.

In this embodiment, the bias control circuit 130 is coupled to the bias node A(n). In the second time interval, the bias voltage control circuit 130 further increases the voltage value of the bias voltage node A(n) from the first bias voltage value to the second bias voltage value (for example, 30-40 volts, which is not used in the present invention). Is limited).

In the second time interval, the bias control circuit 130 receives the n-th stage replica signal ST(n) from the output circuit 120. The bias control circuit 130 provides a regulated voltage value according to the n-th replica signal ST(n) to prevent voltage leakage at the bias node A(n). In this embodiment, the bias control circuit 130 has a voltage stabilizing node B(n). In the second time interval, the bias control circuit 130 provides a regulated voltage value (for example, 15 to 30 volts) at the stabilizing node B(n) according to the n-th replica signal ST(n), and the present invention is not limited to this ). In this way, the gate driving device can prevent voltage leakage at the bias node A(n) under high temperature conditions.

In addition, in the third time interval lagging the second time interval, the bias control circuit 130 will respond to the nth stage discharge control signal DS(n) to pull down the voltage value of the bias node A(n) to low Bias value.

In this embodiment, the n-th stage gate driving unit GU(n) further includes a discharge control circuit 140. The discharge control circuit 140 is coupled to the bias node A(n). In the third time interval, the discharge control circuit 140 provides the n-th stage discharge control signal DS(n) according to the bias node A(n) and the reference clock RK1.

To further explain the circuit configuration of the gate driving unit, please refer to FIG. 3A and FIG. 3B at the same time. 3A is a schematic circuit diagram of an n-th stage gate driving unit according to a second embodiment of the present invention. 3B is a schematic circuit diagram of the (n+1)th stage gate driving unit according to the second embodiment of the present invention. In this embodiment, the n-th stage gate driving unit GU(n) includes a power supply circuit 210, an output circuit 220, a bias control circuit 230, and a discharge control circuit 240. The power supply circuit 210 includes a transistor M1. The first terminal of the transistor M1 receives the system high voltage VDD. The second end of the transistor M1 is coupled to the bias node A(n). The control terminal of the transistor M1 receives the (n-8)th level replica signal ST(n-8). When receiving the (n-8)th replica signal ST(n-8) of the high voltage level, the transistor M1 will provide the voltage value of the system high voltage VDD to the bias node A(n), thereby reducing the bias The voltage value of the voltage node A(n) is raised to the first bias voltage value. On the other hand, when receiving the (n-8)th replica signal ST(n-8) with a low voltage level, the transistor M1 will not provide the voltage value of the system high voltage VDD to the bias node A (n).

The output circuit 220 includes an output transistor M2, a replica transistor M3, and a discharge transistor M4. The first terminal of the output transistor M2 receives the external clock CK1. The control terminal of the output transistor M2 is coupled to the bias node A(n). The second terminal of the output transistor M2 outputs the n-th gate drive signal G(n). The output transistor M2 responds to the voltage level of the bias node A(n), uses the external clock CK1 as the nth gate drive signal G(n), and outputs the nth gate drive signal G(n). The first terminal of the replica transistor M3 receives the external clock CK1. The control terminal of the replica transistor M3 is coupled to the bias node A(n). The second terminal of the replica transistor M3 outputs the n-th level replica signal ST(n). The replica transistor M3 responds to the voltage level of the bias node A(n), uses the external clock CK1 as the nth level replica signal ST(n), and outputs the nth level replica signal ST(n). The first terminal of the discharge transistor M4 is coupled to the bias node A(n). The second terminal of the discharge transistor M4 is coupled to the system low voltage VSS2. The control terminal of the discharge transistor M4 receives the (n+k)-th level replica signal ST(n+k). The discharge transistor M4 pulls down the voltage value of the bias node A(n) to the system low voltage VSS2 according to the (n+k)-th replica signal ST(n+k). In this embodiment, k is equal to 9.

The bias control circuit 230 includes a capacitor C and a first voltage stabilizing and discharging circuit 231. The first terminal of the capacitor C is coupled to the bias node A(n). The second end of the capacitor C is coupled to the output circuit 220. In the second time interval, the second terminal of the capacitor C receives the n-th gate drive signal G(n), so that the n-th gate drive unit G(n) biases the node A( The voltage value of n) is raised to the second bias voltage value. In the second time interval, the first voltage stabilizing and discharging circuit 231 responds to the first voltage level (for example, the low voltage level) of the n-th stage discharge control signal DS(n) to enter the cut-off state. In the off state, the first voltage stabilizing and discharging circuit 231 responds to the voltage value of the n-th replica signal ST(n) to generate a regulated voltage value (for example, 15 volts) at the voltage stabilizing node B(n). Not limited to this).

The first voltage stabilizing and discharging circuit 231 includes voltage stabilizing transistors M5 and M6. The first terminal of the voltage stabilizing transistor M5 is coupled to the bias node A(n). The second end of the voltage stabilizing transistor M5 is coupled to the voltage stabilizing node B(n) to receive the nth level replica signal ST(n). The control terminal of the voltage stabilizing transistor M5 receives the n-th stage discharge control signal DS(n). The first end of the voltage stabilizing transistor M6 is coupled to the second end of the voltage stabilizing transistor M5. The second terminal of the voltage stabilizing transistor M6 is coupled to the system low voltage VSS1. The control terminal of the voltage stabilizing transistor M6 receives the n-th stage discharge control signal DS(n).

The first voltage stabilizing and discharging circuit 231 also includes a pull-down transistor M7. The first end of the pull-down transistor M7 is coupled to the second end of the capacitor C. The second end of the pull-down transistor M7 is coupled to the system low voltage VSS2. The control terminal of the pull-down transistor M7 receives the n-th stage discharge control signal DS(n). The system low voltage VSS1 is different from the system low voltage VSS2. In this embodiment, the system low voltage VSS1 (for example, -15 volts, the present invention is not limited to this) is lower than the system low voltage VSS2 (for example, -12 volts, the present invention is not limited to this).

In addition, the bias control circuit 230 also includes a second voltage stabilizing and discharging circuit 232. In the second time interval, the second voltage stabilizing and discharging circuit 232 enters the cut-off state in response to the first voltage level of the (n+1)th stage discharge control signal DS(n+1), and responds to the nth stage replica signal The voltage value of ST(n) is provided at the regulation node C(n) to generate a regulated voltage value. In the third time interval, the second voltage stabilizing and discharging circuit 232 reacts to the second voltage level of the (n+1)th stage discharge control signal DS(n+1) to enter the conduction state, so as to bias the node A(n ) Is pulled down to -15 volts. The (n+1)th stage discharge control signal DS(n+1) is provided by the (n+1)th stage gate driving unit GU(n+1). The second voltage stabilizing and discharging circuit 232 includes voltage stabilizing transistors M8 and M9. The first terminal of the voltage stabilizing transistor M8 is coupled to the bias node A(n). The second end of the voltage stabilizing transistor M8 is coupled to the voltage stabilizing node C(n) to receive the nth level replica signal ST(n). The control terminal of the voltage stabilizing transistor M8 receives the (n+1)th stage discharge control signal DS(n+1). The first end of the voltage stabilizing transistor M9 is coupled to the second end of the voltage stabilizing transistor M8. The second terminal of the voltage stabilizing transistor M9 is coupled to the system low voltage VSS1. The control terminal of the voltage stabilizing transistor M9 receives the (n+1)th stage discharge control signal DS(n+1).

The second voltage stabilizing and discharging circuit 232 also includes a pull-down transistor M10. The first end of the pull-down transistor M10 is coupled to the second end of the capacitor C. The second end of the pull-down transistor M10 is coupled to the system low voltage VSS2. The control terminal of the pull-down transistor M10 receives the (n+1)th stage discharge control signal DS(n+1).

In this embodiment, the discharge control circuit 240 includes transistors M11 to M16. The first terminal and the control terminal of the transistor M11 are used for receiving the first reference clock. The first end of the transistor M12 is used for receiving the first reference clock. The control terminal of the transistor M12 is coupled to the second terminal of the transistor M11. The second terminal of the transistor M12 is used as the output terminal of the discharge control circuit 240. The first end of the transistor M13 is coupled to the second end of the transistor M11. The control terminal of the transistor M13 is coupled to the bias node A(n). The second terminal of the transistor M13 is coupled to the system low voltage VSS1. The first end of the transistor M14 is coupled to the second end of the transistor M12. The control terminal of the transistor M14 is coupled to the bias node A(n). The second terminal of the transistor M14 is coupled to the system low voltage VSS1. The first end of the transistor M15 is coupled to the second end of the transistor M11. The control terminal of the transistor M15 is coupled to the bias node A(n+1) of the (n+1)th stage gate driving unit GU(n+1). The second terminal of the transistor M15 is coupled to the system low voltage VSS1. The first end of the transistor M16 is coupled to the second end of the transistor M12. The control terminal of the transistor M16 is coupled to the bias node A(n+1). The second terminal of the transistor M16 is coupled to the system low voltage VSS1.

In this embodiment, the (n+1)th stage gate driving unit GU(n+1) includes a power supply circuit 210', an output circuit 220', a bias control circuit 230', and a discharge control circuit 240'. The power supply circuit 210' includes a transistor M1'. The first terminal of the transistor M1' receives the system high voltage VDD. The second end of the transistor M1' is coupled to the bias node A(n+1). The control terminal of the transistor M1' receives the (n-7)-th level replica signal ST(n-7).

The output circuit 220' includes an output transistor M2', a replica transistor M3', and a discharge transistor M4'. The first end of the output transistor M2' receives the external clock CK2. The control terminal of the output transistor M2' is coupled to the bias node A(n+1). The second terminal of the output transistor M2' outputs the (n+1)th stage gate driving signal G(n+1). The first end of the replica transistor M3' receives the external clock CK2. The control terminal of the replica transistor M3' is coupled to the bias node A(n+1). The second terminal of the replica transistor M3' outputs the (n+1)th level replica signal ST(n+1). The first terminal of the discharge transistor M4' is coupled to the bias node A(n+1). The second terminal of the discharge transistor M4' is coupled to the system low voltage VSS2. The control terminal of the discharge transistor M4' receives the (n+10)th level replica signal ST(n+10).

The bias control circuit 230' includes a capacitor C', a first stabilizing and discharging circuit 231', and a second stabilizing and discharging circuit 232'. The first terminal of the capacitor C'is coupled to the bias node A(n+1). The second end of the capacitor C'is coupled to the output circuit 220'. The first voltage stabilizing and discharging circuit 231' includes voltage stabilizing transistors M5', M6' and pull-down transistor M7'. The first terminal of the voltage stabilizing transistor M5' is coupled to the bias node A(n+1). The second end of the voltage stabilizing transistor M5' is coupled to the voltage stabilizing node B(n+1) to receive the (n+1)th stage replica signal ST(n+1). The control terminal of the voltage stabilizing transistor M5' receives the (n+1)th stage discharge control signal DS(n+1). The first end of the voltage stabilizing transistor M6' is coupled to the second end of the voltage stabilizing transistor M5'. The second end of the voltage stabilizing transistor M6' is coupled to the system low voltage VSS1. The control terminal of the voltage stabilizing transistor M6' receives the (n+1)th stage discharge control signal DS(n+1). The first end of the pull-down transistor M7' is coupled to the second end of the capacitor C. The second end of the pull-down transistor M7' is coupled to the system low voltage VSS2. The control terminal of the pull-down transistor M7' receives the (n+1)th stage discharge control signal DS(n+1).

The second voltage stabilizing and discharging circuit 232' includes voltage stabilizing transistors M8', M9' and pull-down transistor M10'. The first terminal of the voltage stabilizing transistor M8' is coupled to the bias node A(n+1). The second end of the voltage stabilizing transistor M8' is coupled to the voltage stabilizing node C(n+1) to receive the (n+1)th stage replica signal ST(n+1). The control terminal of the voltage stabilizing transistor M8' receives the n-th stage discharge control signal DS(n). The first end of the voltage stabilizing transistor M9' is coupled to the second end of the voltage stabilizing transistor M8'. The second terminal of the voltage stabilizing transistor M9' is coupled to the system low voltage VSS1. The control terminal of the voltage stabilizing transistor M9' receives the n-th stage discharge control signal DS(n). The first end of the pull-down transistor M10' is coupled to the second end of the capacitor C'. The second end of the pull-down transistor M10' is coupled to the system low voltage VSS2. The control terminal of the pull-down transistor M10 receives the n-th stage discharge control signal DS(n).

The discharge control circuit 240' includes transistors M11' to M16'. The first terminal and the control terminal of the transistor M11' are used to receive the reference clock RK2. In this embodiment, the timing of the reference clock RK1 is opposite to the timing of the reference clock RK2. For example, the reference clocks RK1 and RK2 will transition based on at least one frame time. The first end of the transistor M12' is used to receive the first reference clock. The control terminal of the transistor M12' is coupled to the second terminal of the transistor M11'. The second terminal of the transistor M12' is used as the output terminal of the discharge control circuit 240'. The first end of the transistor M13' is coupled to the second end of the transistor M11'. The control terminal of the transistor M13' is coupled to the bias node A(n+1). The second terminal of the transistor M13' is coupled to the system low voltage VSS1. The first end of the transistor M14' is coupled to the second end of the transistor M12'. The control terminal of the transistor M14' is coupled to the bias node A(n+1). The second terminal of the transistor M14' is coupled to the system low voltage VSS1. The first end of the transistor M15' is coupled to the second end of the transistor M11'. The control terminal of the transistor M15' is coupled to the bias node A(n) of the n-th stage gate driving unit GU(n). The second terminal of the transistor M15' is coupled to the system low voltage VSS1. The first end of the transistor M16' is coupled to the second end of the transistor M12'. The control terminal of the transistor M16' is coupled to the bias node A(n). The second terminal of the transistor M16' is coupled to the system low voltage VSS1.

In this embodiment, the transistors M1, M11~M16, output transistors M2, duplicate transistors M3, discharge transistors M4, voltage stabilizing transistors M5, M6, M8, M9, and pull-down transistors M7, M10 can be implemented by any form of N-type thin film transistor (Thin-Film Transistor, TFT). Transistors M1', M11'~M16', output transistors M2', replica transistors M3', discharge transistors M4', voltage regulators inside the (n+1) gate drive unit GU(n+1) Transistors M5', M6', M8', M9' and pull-down transistors M7', M10' can be implemented by any form of N-type thin film transistors.

Please refer to FIG. 3A, FIG. 3B and FIG. 4 at the same time. FIG. 4 is a partial timing diagram of a gate driving device according to an embodiment of the present invention. In this embodiment, the time intervals T1, T2, and T3 may correspond to at least a part of the operation timing of the n-th stage gate driving unit GU(n). In the time intervals T1, T2, and T3, the voltage level of the reference clock RK1 is a high voltage level, and the voltage level of the reference clock RK2 is a low voltage level. The time interval T2 lags behind the time interval T1. The time interval T2 and the time interval T1 are separated by a preset time length TD. The time interval T3 lags behind the time interval T2. At the time point tp1 in the time interval T1, when the (n-8)th level replica signal ST(n-8) of the high voltage level is received, the transistor M1 will provide the voltage value of the system high voltage VDD to the bias voltage The node A(n) is used to raise the voltage value of the bias node A(n) to the first bias voltage value. The transistors M13 and M14 of the discharge control circuit 240 are turned on in response to the first bias voltage value of the bias node A(n), and by pulling down the voltage level of the output terminal of the discharge control circuit 240, the (n)th stage discharge control The voltage value of the signal DS(n) is at the first voltage level (low voltage level).

At the time point tp3 at the end of the time interval T1, the voltage value of the (n-8)-th stage replica signal ST(n-8) drops to a low level. Transistor M1 is disconnected. Therefore, between the time points tp3 and tp5, the voltage value of the bias node A(n) is maintained at the first bias voltage value.

In the time interval T2, between the time points tp5 and tp7, the external clock CK1 is at a high voltage level. The output transistor M2 of the output circuit 220 will respond to the voltage level of the bias node A(n), use the external clock CK1 as the nth gate drive signal G(n), and output the nth gate drive signal G(n) with a high voltage level. Level gate drive signal G(n). The replica transistor M3 will respond to the voltage level of the bias node A(n) and use the external clock CK1 as the n-th replica signal ST(n). Since the n-th gate driving signal G(n) is at a high voltage level, the bias control circuit 230 raises the voltage value of the bias node A(n) to the second bias voltage value through capacitive coupling. The transistors M13 and M14 of the discharge control circuit 240 are turned on. Therefore, the discharge control circuit 240 provides the n-th stage discharge control signal DS(n) having the first voltage level (for example, a low voltage level).

The voltage stabilizing transistors M5 and M6 of the first stabilizing and discharging circuit 231 are turned off in response to the first voltage level of the n-th stage discharge control signal DS(n), and are turned off according to the n-th stage replica signal ST(n). The voltage value (for example, 15 volts) is used to prevent voltage leakage at the bias node A(n). That is to say, in the second time interval, the first voltage stabilizing and discharging circuit 231 will further provide a regulated voltage value at the stabilizing node B(n) through the n-th replica signal ST(n) in the off state, thereby The second bias voltage value at the bias node A(n) is supported. Therefore, the first voltage stabilizing and discharging circuit 231 can prevent the voltage leakage of the bias voltage node A(n) caused by the deterioration of at least one of the voltage stabilizing transistors M5 and M6 in a high temperature environment.

Similarly, in the second time interval, the second voltage stabilizing and discharging circuit 232 is turned off according to the (n+1)th stage discharge control signal DS(n+1) with the first voltage level. The second stabilizing and discharging circuit 232 will provide a stabilizing voltage value at the stabilizing node C(n) through the n-th replica signal ST(n) in the off state, so as to support the second voltage at the bias node A(n). Bias value.

In the time interval T2, at the time point tp7, the external clock CK1 transitions from a high voltage level to a low voltage level. The n-th gate drive signal G(n) and the n-th replica signal ST(n) are at low voltage levels. Therefore, the voltage value of the bias node A(n) will drop. The voltage value of the bias node A(n) is maintained at the first bias value between the time points tp7 and tp9, for example.

In the time interval T3, at the time point tp9, the discharge transistor M4 will pull down the voltage value of the bias node A(n) to -15 volts according to the (n+k)-th replica signal ST(n+k). The crystals M13 and M14 are disconnected. Because the voltage level of the reference clock RK1 is a high voltage level. Therefore, the discharge control circuit 240 provides the n-th stage discharge control signal DS(n) with a high voltage level. The first voltage stabilizing and discharging circuit 231 will enter the on state from the off state according to the n-th stage discharge control signal DS(n) having the second voltage level (ie, the high voltage level). The voltage stabilizing transistors M5 and M6 are turned on according to the n-th stage discharge control signal DS(n) with the second voltage level. Therefore, the voltage value of the bias node A(n) is pulled down to -15 volts. In addition, the pull-down transistor M7 is also turned on according to the n-th stage discharge control signal DS(n) with the second voltage level. Therefore, the voltage value of the n-th gate drive signal G(n) is pulled down to -12 volts. In order to achieve the anti-noise effect. The second voltage stabilizing and discharging circuit 232 maintains the off state according to the (n+1)th stage discharge control signal DS(n+1) having the first voltage level (ie, low voltage level).

Incidentally, when the first voltage stabilizing and discharging circuit 231 is in the off state, the voltage value at the control terminal of the pull-down transistor M7 will be smaller than the voltage value at the second terminal of the pull-down transistor M7. Therefore, the pull-down transistor M7 will achieve negative bias compensation in the off state, so as to prevent the degradation of the pull-down transistor M7. When the second voltage stabilizing and discharging circuit 232 is in the off state, the voltage value at the control terminal of the pull-down transistor M10 will be smaller than the voltage value at the second terminal of the pull-down transistor M10. Therefore, the pull-down transistor M10 will achieve negative bias compensation in the off state, so as to prevent the degradation of the pull-down transistor M10. In the time interval T3, the voltage value at the control terminal of the output transistor M2 will be smaller than the voltage value at the second terminal of the output transistor M2. Therefore, the output transistor M2 will achieve negative bias compensation in the time interval T3, so as to prevent the output transistor M2 from being degraded.

Similarly, the operation performed by the (n+1)th gate driving unit GU(n+1) between time points tp2 and tp10 is similar to that of the nth gate driving unit GU(n) at time tp1 and The above operations performed between tp9. Because the voltage level of the reference clock RK2 is a low voltage level. Therefore, the discharge control circuit 240' of the (n+1)th stage gate driving unit GU(n+1) does not generate the (n+1)th stage discharge control signal DS(n+ 1). It should be noted that between the time points tp8 and tp10, the first voltage stabilizing and discharging circuit 231' does not pull down the voltage value of the bias node A(n+1) and the (n+1)th stage gate drive The voltage value of the signal G(n+1). Instead, the second voltage stabilizing and discharging circuit 232' pulls down the voltage value of the bias node A(n+1) and the voltage value of the (n+1)th gate drive signal. Therefore, the first voltage stabilizing and discharging circuit 231' and the transistors M11' and M12' can rest.

The same can be inferred, at other frame times, the voltage level of the reference clock RK1 is a low voltage level, and the voltage level of the reference clock RK2 is a high voltage level. Between time points tp7 and tp9, the first voltage stabilizing and discharging circuit 231 of the n-th gate driving unit GU(n) does not pull down the voltage value of the bias node A(n) and the n-th gate driving The voltage value of the signal. Instead, the second voltage stabilizing and discharging circuit 232 pulls down the voltage value of the bias node A(n) and the voltage value of the n-th gate drive signal. Therefore, the first voltage stabilizing and discharging circuit 231 and the transistors M11 and M12 can rest.

Please refer to FIG. 5, which is a schematic diagram of a gate driving device according to a second embodiment of the present invention. In this embodiment, the gate driving device 200 includes a plurality of gate driving units coupled to each other in series. For example, among the plurality of gate driving units, the n-th gate driving unit GU(n) will be based on the external clock CK1, the system high voltage VDD, the system low voltage VSS1, VSS2, and the reference clock RK1, The (n-8)-level replica signal ST(n-8) and the (n+9)-level replica signal ST(n+9) provide the n-level gate drive signal and the n-level replica signal ST(n) . The (n+9)th stage replica signal ST(n+9) comes from the (n+9)th stage gate driving unit GU(n+9). The (n+1)th level gate drive unit GU(n+1) will be based on the external clock CK2, the system high voltage VDD, the system low voltage VSS1, VSS2, the reference clock RK2, and the (n-7) level replica signal ST(n-7) and the (n+10)-level replica signal ST(n+10) to provide the (n+1)-level gate drive signal and the (n+1)-level replica signal ST(n+1) ),So on and so forth.

In summary, in the first time interval, the nth-stage gate driving unit of the present invention charges the bias node according to the (n-m)th-stage replica signal. In the second time interval, the n-th gate driving unit provides the n-th gate driving signal and the n-th replica signal according to the bias voltage value of the bias node and the corresponding external clock. The second time interval is behind the first time interval, and the second time interval is separated from the first time interval by a preset length of time. The bias node can be charged at an earlier point in time. Therefore, the bias node of the gate driving device can reach a sufficient voltage under low temperature conditions. The nth-stage gate driving unit can also provide a regulated voltage value according to the nth-stage replica signal in the second time interval to prevent voltage leakage at the bias node. In this way, the gate driving device can prevent voltage leakage at the bias node under high temperature conditions. Based on the above, the gate driving device of the present invention can have high reliability under extreme temperatures.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100, 200: Gate drive device 110, 210, 210’: Power supply circuit 120, 220, 220’: output circuit 130, 230, 230’: Bias voltage control circuit 140, 240, 240’: discharge control circuit 231, 231’: The first voltage stabilizing and discharging circuit 232, 232’: The second voltage stabilizing and discharging circuit A(n), A(n+1): bias node B(n), B(n+1), C(n), C(n+1): voltage regulator node C, C’: Capacitor CK1, CK2, CK3, CK9, CK10: external clock DS(n): nth level discharge control signal DS(n+1): (n+1)th level discharge control signal G(n): nth gate drive signal G(n+1): (n+1)th gate drive signal G(n+2): (n+2) level gate drive signal G(n+8): (n+8) level gate drive signal G(n+9): (n+9) level gate drive signal GU(n): nth gate drive unit GU(n+1): (n+1)th stage gate drive unit GU(n+2): (n+2) level gate drive unit GU(n+8): (n+8) level gate drive unit GU(n+9): (n+9) level gate drive unit M1, M1’, M11~M16, M11’~M16’: Transistor M2, M2’: output transistor M3, M3’: Duplicate transistor M4, M4’: Discharge transistor M5, M5’, M6, M6’, M8, M8’, M9, M9’: voltage stabilized transistor M7, M7’, M10, M10’: pull-down transistor RK1, RK2: reference clock ST(n): nth level replica signal ST(n-m): (n-m) level replica signal ST(n-6): (n-6) level replica signal ST(n-7): (n-7) level replica signal ST(n-8): (n-8) level replica signal ST(n+1): (n+1) level replica signal ST(n+8): (n+8) level copy signal ST(n+9): (n+9) level copy signal ST(n+10): (n+10) level copy signal ST(n+11): (n+11) level replica signal ST(n+12): (n+12) level copy signal ST(n+13): (n+13) level copy signal ST(n+k): (n+k) level replica signal T1, T2, T3: time interval TD: preset time length tp1~tp10: time point VDD: system high voltage VSS1, VSS2: system low voltage

FIG. 1 is a schematic diagram of a gate driving device according to a first embodiment of the present invention. FIG. 2 is a schematic circuit diagram of the n-th stage gate driving unit according to the first embodiment of the present invention. 3A is a schematic circuit diagram of an n-th stage gate driving unit according to a second embodiment of the present invention. 3B is a schematic circuit diagram of the (n+1)th stage gate driving unit according to the second embodiment of the present invention. FIG. 4 is a partial timing diagram of a gate driving device according to an embodiment of the invention. FIG. 5 is a schematic diagram of a gate driving device according to a second embodiment of the present invention.

110: Power supply circuit

120: output circuit

130: Bias voltage control circuit

140: discharge control circuit

A(n): Bias node

CK1: external clock

DS(n): nth level discharge control signal

G(n): nth gate drive signal

GU(n): nth gate drive unit

ST(n): nth level replica signal

ST(n-m): (n-m) level replica signal

VDD: system high voltage

Claims (13)

A gate driving device includes: a plurality of gate driving units coupled in series, wherein an n-th stage gate driving unit in the gate driving units includes: a power supply circuit configured A low bias voltage value of a bias voltage node is charged to a first bias voltage value in a first time interval according to an nm-th level replica signal; an output circuit is coupled to the power circuit through the bias voltage node , Configured to provide an n-th level gate drive signal and an n-th level replica signal in a second time interval based on the bias node and a corresponding external clock, wherein the second time interval lags behind the first Time interval, and the second time interval is separated from the first time interval by a predetermined length of time; and a bias control circuit, coupled to the bias node, has a first voltage stabilizing node, configured to: In the second time interval, the voltage value of the bias node is raised from the first bias value to a second bias value, and a stabilized voltage value is provided at the first stabilized node according to the nth level replica signal In order to prevent voltage leakage of the bias node, and in a third time interval lagging the second time interval, the voltage value of the bias node is pulled down to the low bias value, where n and m are respectively positive integers , And nm is greater than or equal to 1. The gate driving device according to claim 1, wherein: the bias control circuit includes: A capacitor, the first terminal of the capacitor is coupled to the bias node, the second terminal of the capacitor is coupled to the output circuit, and in the second time interval, the second terminal of the capacitor receives the nth stage The duplicate signal enables the nth-stage gate driving unit to raise the voltage value of the bias node to the second bias voltage value through capacitive coupling. The gate driving device according to claim 2, wherein the bias control circuit further includes: a first voltage stabilizing and discharging circuit configured to respond to an n-th stage discharge control signal in the second time interval The first voltage level enters a cut-off state, and the voltage value reflecting the nth level replica signal is provided at the first stabilizing node to generate a stabilizing voltage value, and in the third time interval, the voltage value is reflected in the first stabilizing node The second voltage level of the n-level discharge control signal enters a conductive state, so that the voltage value of the bias node is pulled down to the low bias value. The gate driving device according to claim 3, wherein the first voltage stabilizing and discharging circuit includes: a first voltage stabilizing transistor, and the first end of the first voltage stabilizing transistor is coupled to the bias node, The second end of the first voltage stabilizing transistor is coupled to the first voltage stabilizing node to receive the nth stage replica signal, and the control end of the first stabilizing transistor receives the nth stage discharge control signal; and a A second voltage-stabilizing transistor, the first end of the second voltage-stabilizing transistor is coupled to the second end of the first voltage-stabilizing transistor, and the second end of the second voltage-stabilizing transistor is coupled to a first A system has a low voltage, and the control terminal of the second voltage stabilizing transistor receives the nth stage discharge control signal. The gate driving device according to claim 4, wherein in the second time interval, the first voltage stabilizing transistor and the second voltage stabilizing transistor react to the first voltage level of the n-th stage discharge control signal Is disconnected, and according to the voltage value of the n-th level replica signal to prevent voltage leakage of the bias node. The gate driving device according to claim 5, wherein the first voltage stabilizing and discharging circuit further includes: a first pull-down transistor, and the first end of the first pull-down transistor is coupled to the first end of the capacitor At two ends, the second end of the first pull-down transistor is coupled to a second system low voltage, and the control end of the first pull-down transistor receives the nth stage discharge control signal. The gate driving device according to claim 4, wherein the bias control circuit further includes: a second voltage stabilizing and discharging circuit configured to respond to an n+1th stage discharge in the second time interval The first voltage level of the control signal enters the cut-off state, and the voltage value of the n-th level replica signal is provided to a second voltage stabilization node to generate the voltage stabilization value, and in the third time interval, the voltage value is reflected in The second voltage level of the n+1th stage discharge control signal enters the on state, so that the voltage value of the bias node is pulled down to the low bias value. The gate driving device according to claim 7, wherein the second voltage stabilizing and discharging circuit includes: A third voltage stabilizing transistor, the first end of the third voltage stabilizing transistor is coupled to the bias node, and the second end of the third voltage stabilizing transistor is coupled to the second voltage stabilizing node to receive the The n-th level replica signal, the control terminal of the third voltage-stabilizing transistor receives the n+1-th level discharge control signal; and a fourth voltage-stabilizing transistor, the first end of which is coupled to The second terminal of the third stabilized transistor, the second terminal of the fourth stabilized transistor is coupled to the first system low voltage, and the control terminal of the fourth stabilized transistor receives the n+1th stage Discharge control signal. The gate driving device according to claim 8, wherein in the second time interval, the third voltage-stabilizing transistor and the fourth voltage-stabilizing transistor react to the first voltage of the n+1th stage discharge control signal The level is turned off, and the voltage value of the n-th level replica signal is used to prevent voltage leakage at the bias node. The gate driving device according to claim 5, wherein the n-th stage gate driving unit further includes: an n-th stage discharge control circuit, coupled to the bias node, and configured to be based on the third time interval according to the The low bias voltage value of the bias node and a first reference clock provide the nth level discharge control signal. The gate driving device according to claim 10, wherein an n+1th stage gate driving unit in the gate driving units includes: an n+1th stage discharge control circuit coupled to the bias node , Configured to provide the n+1th stage discharge control signal in the third time interval according to the low bias value and a second reference clock. The gate driving device according to claim 11, wherein the timing of the first reference clock is opposite to the timing of the second reference clock. The gate driving device according to claim 1, wherein the output circuit includes: an output transistor, the first terminal of the output transistor receives the external clock, and the control terminal of the output transistor is coupled to the bias voltage Node, the second end of the output transistor outputs the nth gate drive signal; a duplicate transistor, the first end of the duplicate transistor receives the external clock, and the control end of the duplicate transistor is coupled to the A bias node, the second terminal of the replica transistor outputs the nth level replica signal; and a discharge transistor, coupled to the bias node, configured to bias the n+k level replica signal The voltage value of the node is pulled down to the low bias value, where k is a positive integer.

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