TWI742544B - Input buffer and method for biffering voltage input signal - Google Patents

Abstract

The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28nm complementary metal-oxide (CMOS) technology.

Description

Input buffer and method for buffering voltage input signal 【Priority information and related applications】

This patent application is benefited from and/or asserted by US Provisional Patent Application No. 62/393,529. Its application date is September 12, 2016, and the application name is "Input Buffer and Bootstrap Switching Circuit". This US provisional patent application is based on its entire content as a reference.

The disclosure of the present invention relates to the field of integrated circuits, and more specifically, to the input circuit of an analog-to-digital converter (ADC).

In many electronic device applications, an analog-to-digital converter (ADC) can convert an analog input signal into a digital output signal, such as for further digital signal processing or storage through digital electronic devices. Broadly speaking, analog-to-digital converters can convert phenomena representing real environments, such as using analog signals such as light, sound, temperature, electromagnetic waves, or pressure for data processing purposes. For example, in a measurement system, a sensor can measure and generate an analog signal Then, the analog signal is provided to an analog-to-digital converter as input to generate a digital output signal for further processing. In another example, a transmitter can use electromagnetic waves to generate an analog signal to carry information in the air, or a transmitter can transmit an analog signal to carry information through a cable, and the analog signal is provided to An analog-to-digital converter at a receiver is used as an input to generate a digital output signal, for example through a digital electronic device for further processing.

Because of its wide application in various applications, analog-to-digital converters exist in broadband communication systems, audio systems, receiver systems, etc. Since various applications have different requirements for performance, power, cost, and size, it is important to design an internal circuit of an analog-to-digital converter. Analog-to-digital converters can be widely used in various applications, including communications, energy, medical care, instrumentation and measurement, motor and power control, industrial automation and aerospace/defense. As applications requiring analog-to-digital converters increase, the demand for fast and accurate conversion also increases.

The present invention provides an input buffer, which includes an input, a push-pull circuit, and a first level shifter. The above-mentioned input receives the voltage input signal. The push-pull circuit outputs a voltage output signal on an output, wherein the push-pull circuit includes a first transistor of a first type and a second transistor of a second type complementary to the first type. The first level shifter is coupled to the above-mentioned input, and is used to shift the voltage level of the voltage input signal by the first voltage offset across the first level shifter, and generate the first level shift voltage The signal biases the first transistor. Quasi-biased from the first place The first voltage offset provided by the shifter is independent of the frequency of the voltage input signal.

The present invention provides a method for buffering a voltage input signal, which includes the following steps: the first voltage is shifted by a first level shifter, and the level shifts the voltage input signal to generate a first signal, wherein the first voltage The offset is independent of the frequency of the voltage input signal; the first signal is offset by the first transistor of the first type; the offset by the second signal is complementary to the second transistor of the second type of the first type , Wherein the first transistor and the second transistor system are coupled in the push-pull structure; and the first transistor and the second transistor output a voltage output signal.

The present invention provides a device including a device for receiving an input signal, a push-pull device for generating an output signal, and a passive device for generating a first signal to bias the first transistor of the push-pull device. The first signal is coupled to an input signal that spans all frequencies of the input signal.

102: input buffer

104: Transmission line

106: Sampler

MN108: Transistor

110: switch

C _S 112: sampling capacitor

104: Transmission line

200: Bootstrap switching circuit

MP202: Transistor

MP204: Transistor

MN206: Transistor

MN208: Transistor

MN210: Transistor

MN212: Transistor

MP214: Transistor

MN216: Transistor

MN218: Transistor

MN224: Transistor

302: Jump start circuit

MN404: Transistor

502: Sensing Circuit

602: step

604: step

606: step

MN702: Transistor

703: Level shifter

MP704: Transistor

705: level shifter

MN706: Transistor

707: level shifter

MP708: Transistor

709: level shifter

MN710: Transistor

711: level shifter

MP712: Transistor

713: Level Shifter

716: level shifter

1002: Step

1004: Step

1006: step

In order to provide a complete understanding of the disclosed content and technical features of the present invention, please refer to the following description and reference drawings. Similar reference numerals in the figures represent the same components: FIG. 1 is the front end of an analog-to-digital converter in the disclosed embodiment of the present invention.

FIG. 2 is a bootstrap switching circuit in the disclosed embodiment of the present invention.

FIG. 3 is a bootstrap switching circuit with accelerated startup in the disclosed embodiment of the present invention.

4A to 4B are implementation examples of a jump start circuit in the disclosed embodiment of the present invention.

5A to 5C are another example of the jump start circuit in the disclosed embodiment of the present invention An implementation example.

Fig. 6 is a flowchart of a method for accelerating the activation of a sampling circuit.

FIG. 7 is an example of an input buffer in the disclosed embodiment of the present invention.

FIG. 8 is an example of the level shifter in the disclosed embodiment of the present invention.

FIG. 9 is another example of the input buffer in the disclosed embodiment of the present invention.

FIG. 10 is a flowchart of buffering an input signal in the disclosed embodiment of the present invention.

Overview

The development of wireless communication receivers tends to receive more bandwidth to support higher processing capabilities, and directly sample radio frequency (RF) signals to provide resettable capabilities and reduce costs. Other applications, such as equipment and equipment, also require the ability to digitize broadband RF signals. An input circuit that can properly handle high-speed, wide-band radio frequency signals can be beneficial for these purposes. An input buffer and bootstrap switch are designed to provide these uses, and can be implemented in 28 nanometer (nm) complementary metal oxide semiconductor (CMOS) technology.

High-speed analog-to-digital converter

An analog-to-digital converter (ADC) is an electronic device that can convert a continuous physical quantity (physical quantity) carried by an analog signal into a digital output or number representing the amplitude of the quantity (or convert it into one that carries the digital number). Digital signal). An analog-to-digital converter can be defined by the following application requirements: its bandwidth (the frequency range in which an analog signal can be appropriately converted into a digital signal) and its resolution (the maximum analog signal can be divided into digital signals and combined in digital signals) Discrete grade numbers indicated). An analog-to-digital converter also has various specifications for quantifying the dynamic performance of the analog-to-digital converter, including signal-to-noise-to-distortion ratio (SINAD), effective number of bits (ENOB), signal to noise ratio (SNR), Total harmonic distortion (THD), total harmonic distortion plus noise (THD+N), and spurious free dynamic range (SFDR). The analog-to-digital converter has a variety of different designs, which can be selected according to application requirements and specifications.

High-speed applications are particularly important in communications and equipment. The input signal may have a frequency in the gigahertz range, and the analog-to-digital converter may need to sample in the range of 1 billion times per second. The high-frequency input signal can have various requirements for the circuit that receives the input signal, such as the "front end" circuit system of the analog-to-digital converter. The circuit must be capable of high-speed processing. In some applications, the circuit needs to meet specific performance requirements, such as SNR and SFDR. It is important to design analog-to-digital converters that meet the speed and power requirements.

FIG. 1 shows a front end of an analog-to-digital converter in the disclosed embodiment of the present invention. Generally speaking, an input signal V _IN (for example, a high-frequency input signal in the megahertz range) is provided to an input buffer 102, and the output V _{INX of} the input buffer is provided to a sampler 106, which comes from the input buffer The output of the detector and the input signal in the form of _{V INX are sampled to a sampling capacitor CS} 112.

A transistor MN108 (such as an N-type complementary metal oxide field effect (CMOS) transistor, or NMOS transistor) _{is provided so that the input signal V INX} can be provided to the sampling capacitor C _S 112. The transistor MN108 can sometimes represent the sampling switch. In the sampling operation, the transistor MN108 is turned on, and the switch 110 is turned off. The output V _INX of the input buffer can be connected to a transmission line (T-LINE) 104 of the sampler 106 from the input buffer 102. When the analog-to-digital converter has multiple parallel analog-to-digital converters (for example, the analog-to-digital converter is a time-interleaved analog-to-digital converter or a random clock interleaved analog-to-digital converter), it is provided with a plurality of parallel (mutually interleaved) analog-to-digital converters. Matching) sampler, including sampler 106. A plurality of (matching) transmission lines may be included to provide the output signal V _INX from a common input buffer 102 to each sampler. The time-interleaved analog-to-digital converter or the random time-interleaved analog-to-digital converter can sample one input signal V _{INX at a time} . In some cases, a reference analog-to-digital converter and one of the time-interleaved analog-to-digital converters sample the output signal V _INX at substantially the same time. For timing interleaved analog-to-digital converters or random timing interleaved analog-to-digital converters, when at least one sampler provides a load on the input buffer, some of the samplers can be turned off at any time. In order to reduce the degradation of SFDR, the _{back gates of the transistors (such as transistor MN108) that are coupled to receive the input signal V INX in} the samplers can be connected to a negative voltage, such as -1 V _INX , by This minimizes the nonlinearity in these transistors.

Bootstrap switching circuit

1 again, the transistor MN108 fast start-up time sufficient to V _INX is sampled onto sampling capacitor C _S 112, this point is very important, especially in high-speed lines for use. As far as the analog-to-digital converter has a sampling rate of 10 billion samples per second, the startup speed of the transistor MN108 must be fast enough for the input signal V _{INX to} be sampled to the sampling capacitor C _S 112. An interval of 100ths of a trillion seconds. The time required to activate the transistor MN108 may depend on the nature of the transistor MN108 itself, and _{the signal V BSTRP that} drives the transistor MN108 _{at the gate V INX} relative to the source signal. The examples shown here refer to signals that will rise or fall, which represent different logic levels of these signals.

FIG. 2 shows a bootstrap switching circuit 200 according to one disclosed embodiment of the present invention. The bootstrap circuit comprises a switching transistor MN108 of FIG. 1, which based its source receives the input signal V _INX, and whose drain is connected to the sampling capacitor lines (e.g. FIG. 1 of the sampling capacitor C _S 112) one of the plates . The bootstrap switching circuit also includes a bootstrap gate voltage generator (circuit) to generate a gate voltage signal V _{BSTRP for driving the} gate of the transistor MN108 (sampling switch). The bootstrap gate voltage generator activates the gate voltage V _{BSTRP in a} way that can ensure that the transistor MN108 starts quickly.

The bootstrap gate voltage generator can receive V _INX and includes a startup capacitor to generate _{a bootstrap voltage equal to V INX} +V _BOOT . The bootstrap gate voltage generator has a positive feedback loop, The positive feedback loop uses V _INX as the input of the positive feedback loop, and the positive feedback loop includes a starting capacitor in the path of the positive feedback loop. An output of the positive feedback loop generates a gate voltage signal V _{BSTRP that drives} the gate of the transistor MN108 (the sampling switch).

The positive feedback loop is used to transmit the gate voltage signal V _{BSTRP at a} high speed, which is sufficient to ensure that the transistor MN108 is started quickly. The positive feedback loop is bootstrap connected to the input signal V _INX , where the target of the positive feedback loop is to drive the gate voltage signal V _BSTRP to V _INX plus the voltage V _BOOT (V _BOOT is the voltage across the startup capacitor C _{BOOT ),} To start the transistor MN108. More specifically, the positive feedback loop drives the gate voltage signal V _BSTRP to be high enough to cause sufficient voltage V _GS across the gate and source to enable the transistor MN108. The bootstrap gate voltage generator is driven by a clock signal CLK, and CLKB is the opposite version of CLK. The bootstrap gate voltage generator can also receive a charging phase clock signal CLKB _BST , which controls the charging phase time point of _{the starting capacitor C BOOT.} Transistor MN108 is expected to start quickly when CLK rises, and transistor MN108 is expected to turn off when CLK falls.

A charging phase (when _{the BST} CLKB and CLKB are increased), the transistor transistor MN224 and MN210 (e.g. NMOS transistor) system is actuated to start charging the capacitor C _BOOT across a voltage V _BOOT (e.g. V _BOOT = V _DD -V _SS ). Turning on the transistor MN224 can connect the top plate of _{the capacitor C BOOT to V DD} . Turning on the transistor MN210 can connect the bottom plate of _{the capacitor C BOOT to V SS} . If V _SS is the ground plane, the starting capacitor C _BOOT is charged to V _DD .

Before the positive feedback loop is activated, since CLK is low in the previous phase (charging phase), the node X is at V _DD . CLK drives the gate of transistor MP214 (for example, a P-type complementary metal oxide field effect transistor (CMOS) or PMOS transistor). A lower CLK will enable the transistor MP214. When the transistor MP214 is activated, the gate (node X) of the transistor MP214 is at V _DD . When the node X is at V _DD and CLKB is high, the transistor MP202 (such as a PMOS transistor) is turned off. Here, the transistor MP202 can refer to the output transistor that outputs the V BSTRP that drives the gate (sampling switch) of the _{transistor MN108.} V _BSTRP is in a low state, such as keeping the sampling switch of transistor MN108 in the off state.

CLK rising from low (or CLKB falling from high) can start the positive feedback loop. When the CLKB that drives the gate of the transistor MP204 (such as a PMOS transistor) is lowered (such as when CLK rises), the transistor MP204 (such as a PMOS transistor) is activated, and the transistor MN208 (such as an NMOS transistor) is drained Pull up to close to V _DD (raise), and pull up the drain of transistor MN206 (such as NMOS transistor) (such as V _DD ), thereby raising the V _BSTRP electrode.

V _BSTRP drives the gates of transistors MN216 (such as NMOS transistors) and transistors MN212 (such as NMOS transistors). The transistor MN212 can refer to the input transistor, because the transistor MN212 receives the input signal V _INX . _An increase in V BSTRP can activate transistor MN216 (for example, NMOS transistor) and transistor MN212 (for example, NMOS transistor). At the same time, because CLK rises, transistor MP214 turns off. Through the activated transistors MN216 and M212, the gate of the transistor MP202, such as node X, can be effectively connected to V _INX .

In the previous phase (for example, the charging phase), the startup capacitor C _BOOT is charged to have V _BOOT across the startup capacitor. When the positive feedback loop is connected, the gate system of the transistor MP202 can have V _INX , and the source system of the transistor MP202 can have a voltage of _{V INX} + V _BOOT. Transistor MP202 is activated to increase V _BTSTRP to V _INX +V _BOOT , thereby increasing the voltage across the gate of the sampling switch (e.g. transistor MN108) and source V _{GS (e.g. V BSTRP} -V _INX =V _BOOT ) To start it. When V _BTSTRP increases, the increased V _BTSTRP loops through the transistor MN201 and the transistor MN212, thereby _{further increasing V BTSTRP} again to activate the transistor MN108. Therefore, the positive feedback loop can provide fast start-up of the transistor MN108.

In some cases, when the gate of the transistor MP202, such as node X, is connected to V _INX , the positive feedback loop is activated. The positive feedback loop helps drive the transistor MN216 and the transistor MN212 of node X. It can be started with a relatively delay, thereby greatly reducing the positive feedback loop _{when node X cannot be connected to V INX in time.}

Consider that when V _INX (for example, the source of transistor MN212) is close to V _DD at a certain moment, and when CLKB is turned on (starting means that CLKB is just falling, or CLK is just rising), transistor MN216 The gate of MN212 and the gate of transistor MN212 (for example, the V _BSTRP electrode) are also close to V _DD . It is tied to node X starts when V _DD (since CLK decreases, the node X and the V _DD line is located through the transistor MP214). In this state, all terminals of the transistor MN216 can be roughly at V _DD . Transistor MN216 and transistor MN212 may not have enough voltage (V _GS ) across the gate and source of individual transistors to be activated by this. Therefore, since there is no sufficient V _GS , the transistor MN216 and the transistor MN212 may be reluctantly/weakly activated, thus slowing down the positive feedback effect of the loop. The circuit finally starts to operate when the transistor MN216 and the transistor MN212 are more fully activated, and the node X is pulled closer to V _INX to start the transistor MP202, which allows V _INX +V _{BOOT to} pass through the transistor MP202 and move toward the electricity. The gate of crystal MN108 raises V _BSTRP .

Jump start the positive feedback loop

In order to solve the slowing down of the positive feedback loop, a jump start circuit can be implemented to quickly start the transistor MP202 (output transistor) when the positive feedback loop is activated, so that V _INX +V _BOOT can pass through the transistor MP202 more quickly. The flow to the transistor MN108 causes the V _BSTRP to increase more quickly, thereby enabling the transistor MN216 and the transistor MN212 more quickly. Therefore, a faster bootstrap switching circuit is achieved.

FIG. 3 shows a bootstrap switching circuit 300 with accelerated startup in the disclosed embodiment of the present invention. The bootstrap switching circuit 300 has a sampling switch, such as a transistor MN108, which receives a voltage input signal, such as V _INX , and a gate voltage, such as V _BTSTRP . The bootstrap switching circuit also has a bootstrap voltage generator. The bootstrap voltage generator generates the gate voltage, such as V _BTSTRP , which is provided to the sampling switch.

The bootstrap switching circuit includes a positive feedback loop to generate the gate voltage to activate the sampling switch. The positive feedback loop may include an input transistor, such as transistor MN212, to receive the voltage input signal, such as V _INX , and an output transistor, such as transistor MP202, to output the gate voltage of the sampling switch. The positive feedback loop has a startup capacitor, such as C _BOOT , which can be used to generate a startup voltage, such as V _INX +V _BOOT . Since the sampling switch, for example, the transistor MN108 has V _INX at its source, the starting voltage at the gate of the sampling switch can activate the sampling switch. In other words, the positive feedback loop activates the sampling switch, such as the transistor MN108, by _{driving the gate voltage to the startup voltage generated according to the voltage input signal V INX} and the voltage across the startup capacitor C _BOOT. The input transistor, such as transistor MN212, is coupled to a first plate of the startup capacitor. The output transistor, such as the source of the transistor MP202, is coupled to a second plate of the startup capacitor.

The operation of the positive feedback loop uses the gate voltage as a positive feedback to drive the transistors, such as the transistor MN212 and the transistor MN216 in the loop. The transistors then drive the gate voltage of the output transistor to V _INX , such as the gate voltage of the transistor MP202, and assist the output transistor, such as the transistor MP202, to pass the starting voltage or drive the gate voltage to the starting voltage . The start voltage can start the sampling switch, such as transistor MN108.

For the example of the positive feedback loop shown, the input transistor, such as transistor MN212, is driven by the gate voltage of the sampling circuit, such as the gate voltage of transistor MN108. The positive feedback loop further has a first transistor, such as transistor MN216, which is coupled to the output transistor, such as the gate of transistor MP202, and a drain of the input transistor, such as transistor MN212. The first transistor is also driven by the gate voltage of the sampling switch. After being combined with each other, the first transistor and the input transistor can drive the node X to V _INX during the active period of the positive feedback loop when the first transistor and the input transistor are activated.

The bootstrap switching circuit also includes a jump start circuit 302 to start the output transistor for a finite period during the start-up period of the output capacitor during the start-up phase of the positive feedback loop. The jump start circuit 302 is coupled to the node X, such as the gate of the transistor MP202, where the transistor MP202 is the output transistor of the positive feedback loop. In some embodiments, the jump start circuit 302 can, for example, provide/output a signal at node X to briefly start the transistor MP202 when the CLKB is lowered, so as to jump start the function of the positive feedback loop. After the finite period, the jump start circuit 302 stops starting the output transistor and enables the positive feedback loop to operate.

In other words, the jump start circuit 302 is connected to the output transistor MP202 at the beginning of the positive feedback loop function, and is separated from the output transistor MP202, so that the function of the positive feedback loop can drive the output transistor MP202 (make the positive feedback loop function to Drive node X to V _INX ). The jump start circuit 302 can help the positive feedback loop to move faster during the delayed start period (short time) of the transistor MN216 and the transistor MN212. The jump start circuit 302 can temporarily pull node X to a low logic level (such as the ground plane or some other basic voltage) due to the gate of the transistor MP202, and jump start the positive feedback loop function, so that the transistor MP202 starts, and allows V _INX +V _BOOT (for example, the _{top plate voltage of the starting capacitor C BOOT} ) to flow faster to the gate of transistor MN108 through the output transistor MP202, so that V _BSTRP rises faster.

It should be noted that the jump start circuit 302 only temporarily pulls the node X to a low logic level, but it is better to prevent the node X from completely reaching the ground plane or the low logic level. Pulling node X completely to the ground plane may cause unexpected pressure on transistor MP202, because the source of transistor MP202 will contact V _INX +V _BOOT . Furthermore, the jump start circuit 302 quickly "releases" node X (or stops pulling node X to a low logic level), so that the positive feedback loop can be operated, and preferably is connected to transistor MN216 and transistor MN212 Fully connect node X _{before V INX} to "release". The time point of the jump start circuit 302 can be changed according to the implementation.

During the startup phase of the positive feedback loop and before CLKB is lowered, the node X is at V _DD to keep the output transistor MP202 off when the startup capacitor C _{BOOT is charged, and keep V BSTRTP} low. However, when node X starts to be at V _DD during the activation phase of the positive feedback loop, node X will slow down the feedback mechanism. The jump start circuit 302 quickly starts the transistor MP202 by pulling the node X to an appropriate logic level. Therefore, when the node X starts at V _DD , it will no longer hinder the speed of the feedback loop.

In some cases, the gate of an additional transistor MN218 (such as an N-type new oxygen semiconductor transistor) can be connected to CLK, and its source can be connected to an input transistor such as the drain of transistor MN212 (and the transistor The source of MN216) and its drain are connected to node X (for example, the gate of the output transistor MP202), so as to help connect node X to V _INX during the operation of the positive feedback loop. The additional transistor system is controlled by a clock signal that can drive the positive feedback loop, such as CLK. When the CLK rises during the startup phase, the transistor MN218 is activated to assist in connecting the node X to V _INX in an attempt to overcome the delayed startup of the transistor MN216. The operation of the jump start circuit 302 is different from that of the additional transistor MN218, and the jump start circuit 302 can provide the bootstrap switching circuit with a larger speed increase than the additional transistor MN218 alone.

The time point when node X is pulled down to a low logic level and released quickly must be considered or based on factors such as the circuit design, circuit manufacturing process, and parasitic properties in the bootstrap switching circuit. The time point can be determined by the simulation or test operation of the circuit. This point in time is variable or controllable. In some cases, the time point may depend on at least one voltage level or signal in the bootstrap circuit, which may indicate when the jump start circuit 302 should start the pull-down action and/or stop the Pull down the effect.

If the transistor MP202 is a PMOS transistor (in a complementary/equivalent implementation), the jump start circuit 302 can provide a temporary pull-up function to quickly jump start the feedback loop.

Jump start circuit implementation example

4A to 4B show an implementation example of a jump start circuit according to the disclosed embodiment of the present invention. In the example shown in FIG. 4A, the jump start circuit includes a transistor MN404 (for example, an NMOS). The transistor MN404 receives CLKB at the source (used to activate the positive feedback loop, presented in the form of CLK and CLKB) and receives CLKB _DEL at the gate. CLKB decreases during the start-up phase of the positive feedback loop. CLKB _DEL is a delayed version of CLKB, so when CLKB decreases, CLKB _DEL remains high for a short period of time. During this period, when CLKB is low and CLKB _{DEL is} high, transistor MN404 can be activated and node X can be pulled to the low logic level of CLBK (for example, the ground plane). When the delay period is over, CLKB _{DEL is} lowered to turn off transistor MN404. This jump start circuit can effectively pull node X to a low logic level, and quickly release node X, so that the positive feedback loop continues its operation. In other words, the transistor system is activated by a delayed version of the clock signal to output the clock signal, thereby activating the output transistor for a finite period of time.

As shown in FIG. 4B, the jump start circuit may include two inverters for generating the delayed version of the clock signal CLKB _DEL according to the clock signal CLKB. Therefore, CLKB _DEL can have the same polarity as CLKB, but with two inverter delays. _{Other embodiments for generating a CLKB DEL} with a desired delay amount can be known through the disclosure, including the use of a gate, a resistor-capacitor delay circuit, and so on. The embodiment shown in FIG. 4B is not for limitation purposes.

5A to 5C show another implementation example of the jump start circuit according to the disclosed embodiment of the present invention. In the example shown in FIG. 5A, the jump start circuit includes a switch 501, which is controlled by the control signal CTRL. The switch 501 connects a gate of the output transistor (such as the transistor MP202) to a bias voltage V _{ON to} activate the output transistor. The control signal can have a pulse to turn off the switch 501. The pulse system can jump start the output transistor for a finite period of time (pull the gate to the bias voltage and release the gate so that the positive feedback loop can be operated). Figure 5B shows an example waveform of the control signal CTRL, which has a short pulse to close the switch and pull node X to the bias voltage V _ON and quickly release node X (open the switch and set node X from V _ON Cut off the connection), so that the positive feedback loop can continue its operation. The voltage V _ON can be a suitable bias voltage for starting the transistor MP202, such as a ground plane, or other suitable voltage levels. The switch 501 can be implemented using a transistor.

In some embodiments, the jump start circuit includes a sensing circuit 502 (as shown in FIG. 5C), so a closed loop delay can be implemented. The sensing circuit activates the jump start circuit according to at least one state of the bootstrap switching circuit indicating the start phase of the positive feedback loop. A closed loop delay means that the time point at which the control signal CTRL or the jump start circuit pulls the node X to a low logic level and/or releases the node X depends on at least one state of the bootstrap switching circuit. Preferably, the at least one state indicates the start phase of the positive feedback loop. The sensing circuit 502 can sense a voltage V _SENSE and generate the control signal CTRL accordingly. The voltage V _SENSE can represent a voltage of any applicable node in the bootstrap switching circuit. The node system can be a node in the positive feedback loop.

In an example, the sensing circuit 502 includes a comparator coupled to the source of the transistor MP202 to compare the voltage of the source of the transistor MP202 to a predefined threshold or to the positive feedback loop Compare with another node. The voltage that crosses the predefined threshold can indicate the start state of the positive feedback loop. If the voltage (for example, the source of the transistor) rises above the predefined threshold (indicating that the positive feedback loop starts its operation), the output of the comparator can drive the control signal CTRL to turn off the jump start function accordingly .

Method of accelerating activation of a sampling switch

Fig. 6 is a flowchart showing the method of accelerating the activation of a sampling switch. In step 602, one of the output transistors in a positive feedback loop (for example, transistor MP202 in FIG. 3) outputs an output voltage of a bootstrap voltage generator (for example, V _{BSTRP in} FIG. 3) to drive the Sampling switch (such as transistor MN108 in Figure 3). In some embodiments, the sample-on relationship receives a voltage input signal (for example, the sampled V _INX ). The positive feedback loop can receive a voltage input signal _{output by the output transistor and driven by the output voltage (for example, V BSTRP in} FIG. 3) at an input transistor (for example, transistor MN212 in FIG. 3). The positive feedback loop can generate a bootstrap voltage signal (such as the bootstrap voltage of V _INX + V _BOOT ) as the output voltage of the bootstrap voltage generator based on the voltage input signal, so that when the positive feedback circuit is connected Activate the sampling switch.

In step 604, a jump start circuit can pull a gate voltage of the output transistor (for example, node X in FIG. 3) to a start voltage level, so as to start the output circuit after the positive feedback loop is started. The crystal lasts for a period of time. In some embodiments, adjusting the gate voltage of the output transistor includes changing the gate voltage from a shutdown voltage level to a startup voltage level. Before the positive feedback function is connected, the gate voltage can be at V _DD , as shown in Figures 2 and 3, which is regarded as one of the "off voltage levels" of the transistor MP202. The jump start circuit can temporarily pull the gate voltage to a "start voltage level", such as a logic low voltage level, to start the output transistor for a short period of time.

In step 606, the jump start voltage can be stopped or interrupted to adjust the gate voltage after a period of time. For example, the jump start circuit can release the gate voltage of the output transistor back to a voltage delivered by the positive feedback loop after a period of time. For example, the jump start circuit can operate the positive feedback loop and drive the gate voltage close to the input signal V _INX to be sampled. In some embodiments, suspending the adjustment of the gate voltage or releasing the gate voltage of the output transistor after a period includes enabling the positive feedback loop to drive the gate voltage to the bootstrap voltage generator And a voltage level of the voltage input signal (for example, V _INX ) of the sampling switch.

In some embodiments, the sensing circuit (such as the sensing circuit 502 of FIG. 5C) can sense at least one state indicating that the positive feedback loop has been activated. The sensing circuit can generate a control signal in response to the sensing of the at least one state. The control signal can drive the gate voltage of the output transistor to be adjusted.

A device for accelerating the activation of a sampling switch

In order to accelerate the activation of a sampling switch, a device may include a sampling means (for example, transistor MN108 in FIG. 3), which receives an input signal to be sampled (for example, V _{INX in} FIG. 3), and enables and disables the sampling means A control signal (for example, V _{BSTRP in} Figure 3). The device may further include means (such as transistors MN210, C _BOOT, and transistor MN224 in FIG. 3) for generating a boosted voltage signal based on the input signal (such as _{the bootstrap voltage of V INX} + V _BOOT). The device may include an output means for outputting the control signal (for example, the transistor MP202 in FIG. 3). The device may include a means for bringing the control signal to the boost voltage through the positive feedback effect of the control signal, as shown in FIGS. 2 and 3. The device may include means for activating the output means for a finite period of time during the activation phase of the positive feedback effect (for example, the jumper activation circuit 302 of FIG. 3 and related examples of FIGS. 4A to 4B and 5A to 5C).

Input buffer

The CMOS input buffer (single-ended) may include a stack of NMOS transistors and a current source. The voltage input to the input buffer can be directly connected to a gate of the NMOS transistor (the source of which is connected to the current source), and the source of the NMOS transistor is the output. In this type of input buffer, the output is shifted by a voltage, the voltage V _GS crosses the gate and the source downward, and the NMOS transistor buffers the input voltage from its gate input to its The voltage of the source (such as the output). The voltage offset from input to output represents that the range of the output voltage depends on the input voltage range. In other words, there is an offset between the input voltage and the output voltage. If the input buffer is driving a circuit that requires a specific voltage range, this bias is an undesirable or problem to be solved in the circuit design.

FIG. 7 shows an example of the input buffer of the disclosed embodiment of the present invention. The input buffer can be used as shown in Figure 1. The input buffer has an input V _IN for receiving a voltage input signal. The voltage input signal may be a high-frequency data signal to be converted by a data converter, such as a high-speed analog-to-digital converter. The input buffer includes a push-pull circuit, which outputs a voltage output signal _{on an output V INX.} The push-pull circuit has a first transistor of a first type, and a second transistor of a second type complementary to the first type. For example, the first transistor system may be an NMOS transistor MN702 (such as an NMOS transistor), and the second transistor system may be a PMOS transistor MP704 (such as a PMOS transistor). The sources of the two transistors are coupled to each other, and the sources also serve as the output V _{INX of} the output buffer to provide an output signal V _INX .

For this input buffer, the NMOS transistor MN702 and the PMOS transistor MP704 are not directly connected to the input V _IN , but the gate of the NMOS transistor MN702 is connected to the input V _IN through the level shifter 703, and The gate of the PMOS transistor MP704 is connected to the input V _IN through the level shifter 705. In some embodiments, the input buffer may include a first level shifter, which is coupled to the input to shift a first voltage across the first level shifter The amount shifts the voltage level of the voltage input signal and generates a first level offset voltage signal to bias the first transistor. _{For example, the level shifter 703 can shift V IN} by crossing a first voltage offset (for example, the voltage is increased) across the level shifter 703, and generate a first level The voltage V _{1 is} offset to bias the first transistor, such as transistor MN702. In some embodiments, the input buffer may include a second level shifter, which is coupled to the input to shift a second voltage across the second level shifter The amount shifts the voltage level of the voltage input signal and generates a second level shift voltage signal to bias the second transistor. _{For example, the level shifter 705 can shift V IN} by a second voltage offset (for example, the voltage is reduced) across the level shifter 705, and generate a second level shift The voltage V _{2 is} shifted to bias the second transistor, such as PMOS transistor MP704.

In the input buffer of FIG. 7, the input buffer has a push-pull structure. The push-pull architecture has at least one NMOS transistor MN702 and PMOS transistor MP704, the source of which is connected to the source of a PMOS transistor MP704. The sources are coupled to each other and form the output V _INX . As far as the 28nm CMOS process is concerned, PMOS and NMOS are complementary in performance such as bandwidth, permittivity, and transconductance per unit current. In some other manufacturing processes, the performance of PMOS transistors and NMOS transistors may be very different. This complementary push-pull architecture uses NMOS transistors on one side and PMOS transistors on the other. It is possible to make a complementary buffer on one side of PMOS and NMOS in a 28nm CMOS semiconductor manufacturing process. One side has the same performance. No matter from which side the current is supplied to the output V _INX to drive the load, the structure can provide symmetrical pull-up and pull-down properties. The lengths of the two sides are equal, so symmetrical pull-up and pull-down effects can be achieved. In terms of distortion, the complementary structure means that there may be less even-order distortion (for example, to reduce second-harmonic distortion).

In addition to the symmetrical performance, the input buffer has high efficiency, because when a certain amount of current passes through the transistor, the NMOS transistor MN702 and the PMOS transistor MP704 can effectively double the transconductance of the input buffer. For the same amount of current, NMOS transistor MN702 and PMOS transistor MP704 can make the input buffer achieve two parallel mutual conductance.

For this input buffer, it is impossible to connect the gates of NMOS transistor MN702 and PMOS transistor MP704 to each other. The reason is that when the gates of NMOS transistor MN702 and PMOS transistor MP704 are short-circuited, there will be no Any voltage across the source of any one of these transistors (V _{GS is} insufficient), so both transistors cannot be activated. Therefore, at least one of the two quasi-shifters 703 and 705 is disposed between the gates of the NMOS transistor MN702 and the PMOS transistor MP704. The level shifters pull the gates of the two transistors apart from each other, so that the voltage across the gate and the source has a sufficient difference to keep the transistors activated.

The level shifter 703 and the level shifter 705 connected to V _IN are regarded as (programmable) voltage shifts and bias the NMOS transistors MN702 and PMOS transistors MP704 at the gates of individual transistors. . In other words, the first voltage offset is programmable, and the second voltage offset is also programmable. In this way, the level shifter is a circuit that can shift a voltage level input to the level shifter by a certain amount to generate a bit at the output of the level shifter Quasi-offset voltage level.

For biasing NMOS transistor MN702 and PMOS transistor MP704, for example, it is important to _{set appropriate voltages V 1} and V _2. If the two gates are too separated, too much current may flow through the two transistors. However, if the two gates are too far apart (the two transistors do not have sufficient V _GS , for example, less than two V _GS ), the transistors cannot be fully activated. Preferably, an ideal amount of current flows through the transistors. In order to ensure that these transistors can have ideal current flow, a copy bias device can be used to set the voltage of the level shifter 703 and the level shifter 705 to ensure that the NMOS transistor MN702 and the PMOS transistor MP704 can be used. With ideal current.

Are preferred, the voltage difference between the transistor MN702 and PMOS transistor MP704 gate must be at least two V _GS, for example, the threshold voltage V _GS of transistor MN702 threshold voltage V _GS of the NMOS and the PMOS transistor MP704, and set to Ensure that an ideal amount of current flows through the NMOS transistor MN702 and the PMOS transistor MP704. In some embodiments, the sum of the first voltage offset (for example, the level shifter 703) and the second voltage offset (for example, the level shifter 705) is at least the first voltage offset The sum of a first threshold voltage of a crystal (such as NMOS transistor MN702) and a second threshold voltage of the second transistor (such as PMOS transistor MP704).

Input to output bias and design considerations of these level shifters

Based on the result of the level shifter, the input V _IN and the output V _INX are independent, and the voltage range of the input and the voltage range of the output no longer depend on each other or must be the same. Any offset between the input and the output can be selected by implementing an appropriate level shifter (for example, implementing the level shifters 703 and 705 appropriately). By selecting appropriate first voltage offset and second voltage offset, _{the voltage output signal at V INX} can be biased or have a bias from the voltage input signal V _INX . In an example, the voltage input signal may be concentrated at 0.5 volts, and the voltage input signal may be concentrated at 0.25 volts. The input buffer has greater flexibility.

In some cases, the input voltage _{at V IN and the output voltage at V INX} may be roughly the same voltage. For example, V _IN rises through the level shifter 703, and drops a gate-to-source voltage of a PMOS transistor MP704 _{at the output V INX.} V _IN decreases with the level shifter 705, and the gate-to-source voltage of one of the PMOS transistor MP704 rises _{at the output V INX.} If an appropriate level shifter is used, there is no input to output bias. This feature does not exist in other input buffers that implement unitary elements and followers.

However, the input-to-output bias is not necessarily zero. With the two-digit quasi-shifter, it means that _{the voltage range of the input V IN} can be different from the voltage range of the output V _INX . With the two-position quasi-shifter, as long as there is an appropriate voltage difference between the gate of the NMOS transistor MN702 and the gate of the PMOS transistor MP704 (for example, bias the transistors so that ideal current flows through them, etc.) ), the input to output voltage can be adjusted to suit the application (for example, when the bias system is ideal.)

The input to output bias system is variable. As described in this way, variable means that it varies over time or between various uses. The voltage offset provided by the level shifters is also variable (and vice versa). A certain degree of freedom of the input buffer is that the level shifters 703 and 705 are adjustable Adjustment, so as to have a specific output voltage range or voltage level.

In some embodiments, the level shifters 703 and 705 (and other level shifters disclosed herein) are variable or programmable. In some embodiments, the voltage offset generated by the level shifter may be different from another voltage offset generated by the input buffer for another level shifter. The voltage offset can be adjusted by the user and/or can be controlled by the chip. The voltage offset can be optimized based on other factors, such as distortion, electrostatic discharge (ESD), and so on.

In some cases, one of the level shifters 703 and 705 can be completely omitted, wherein the voltage of the gate of the NMOS transistor MN702 or the voltage of the PMOS transistor MP704 is shifted by the level , In order to achieve the proper voltage difference between the gates of the two transistors.

Implement a quasi-shifter

One aspect of the level shifter is related to its ability to provide a voltage offset from the input to the transistor gates. It has an independent input frequency or can be up to DC (such as a smart frequency or a constant input V _IN ) And other properties. In other words, the level shift signal can be coupled with the input V _IN across all frequencies of the output. Some other level shifters cannot have such a frequency response.

The level shifter can be implemented in different ways. For example, the level shifter may include at least one of the following: at least one current source, at least one resistor, at least one transistor, at least one diode, at least one transistor in the form of a diode, at least one A capacitor, at least one battery, and at least one nonlinear resistor. In some embodiments, the level shifter includes a means to provide a voltage shift that is controlled by the amount of current flowing through the level shifter and can be independent of Outside the input frequency. For example, a diode-type transistor system can provide a voltage level offset that depends on the current flowing through the diode-type transistor (the current system can be provided by at least one current source). In some embodiments, the level shifter may include a switched capacitor circuit. Preferably, a passive circuit component (as opposed to an active component that includes a complementary transistor as a follower, which shifts up and down from the input) is used to implement a level shifter. Passive circuit components use less current, have lower noise, and are more linear than active circuit components. Passive circuit components may include transistors in the form of diodes, resistors, capacitors, circuits, and appropriate combinations thereof.

FIG. 8 shows an implementation example of the level shifter in the disclosed embodiment of the present invention. The level shifter example includes current sources, and has a resistor and a capacitor in parallel between the current sources. For example, a level shifter mentioned here may include at least one current source (such as I ₁ and I ₂ ), and a resistor (or resistive element, such as R) and a resistor connected in parallel The capacitor (or capacitive element, such as C). The resistor and the capacitor connected in parallel with the resistor are between the current sources I ₁ and I ₂ . Other configurations of these circuit elements can be known from this disclosure. Any current provided by these current sources will flow through the parallel resistors and capacitors. The resistance and the amount of current flowing through the resistance can be set to cross the level shifter for the voltage offset (the voltage offset can be equivalent to the amount of current amplified by the impedance). In other words, the amount of current flowing through the resistor and provided by the current sources can be set to a voltage across the level shifter. For a programmable level shifter, the amount of current is programmable, or the resistance of the resistor is programmable. Any of these level shifters can be implemented using the methods described and shown here. According to the specific use of the level shifter, the values of the different components in the level shifters may vary.

Bootstrap the gate after connecting these main transistors

For an input buffer, it is important to achieve high performance, such as achieving good linearity. In some embodiments, a first back gate of the first transistor (eg, transistor MN702) and a second back gate of the second transistor are coupled to the output V _INX or follower _{The signal V INX} is output at this voltage. For example, the back gate (body) of the NMOS transistor MN702-level PMOS transistor MP704 is directly connected to the output V _INX , for example, the back gates are bootstrapped connected to the output node V _INX . If the NMOS transistor MN702 and the PMOS transistor MP704 are connected to some fixed voltage, such as ground and V _DD , when the input V _IN changes, the V _{GS of} the two transistors will also change. The voltage change between the source and the back gate will change the V _{GS of the} transistors. This change will also adjust the voltage V _GS and the capacitance of the transistor. This change may cause distortion. To avoid this problem, the back gate NMOS transistor MN702 and PMOS transistor MP604 are connected or bootstrapped to the output V _INX . For the input signal V _IN (and the V _{INX of the coupled V IN} ), the voltage between the gate and the source of the transistors is zero. When the input signal V _IN changes, V _GS does not change anymore. The capacitance of the transistor may be short. The performance system has improved. The input buffer shown in FIG. 7 and at least some of the features described so far can reduce some non-linearity or variation (once).

Minimize capacitance to improve performance

When the input buffer drives a high-frequency input signal V _IN , it is better to minimize the relative capacitance, or at least keep the capacitance constant. Or if the capacitance is about to change, it is better to reverse bias the contact as much as possible to make the capacitance change smaller, or at least make the voltage constant across the capacitance to reduce the change. Reverse biasing the contact as much as possible, for example, relying on the voltage of the contact capacitance, can make the capacitance smaller and reduce its non-linearity.

Connecting the rear gate to the source (and output V _INX ) of the transistor MN702 can create capacitance between the rear gate and the deep N-well. The N-type well system has a fixed potential, and the rear gate system moves around the signal. The NMOS transistor MN702 can be placed in its independent P-type well (rear gate), and it can be placed in an independent region of a deep N-type well. A back gate of a first transistor (e.g., transistor MN702) and a capacitance between an N-well can be reverse biased. For example, the deep N-row well system can be connected to a high potential, so that the capacitance between the gate (P) and the deep N-well (N) is subject to strong reverse bias as much as possible (the reason is as described above) . Therefore, the non-ideal influence of the capacitor can be reduced (for example, its linearity can be improved). The input buffer shown in FIG. 7 and the aforementioned at least part of the features can reduce some non-linearities or variables (once).

Bootstrap stacking to improve performance

If the input buffer is made with 28nm CMOS technology, the output conductivity, or the _{ratio of the conductivity G DS} to the transconductance G _M , is small, or highly nonlinear. This may make the drain of NMOS transistor MN702 and PMOS transistor MP704 connected to a fixed supply is not ideal, because when the signal V _IN or V _INX moves up or down, it will change the voltage across the transistor. , For example, move V _DS (drain to source voltage) up and down. This may cause distortion of, for example, 25 to 40 dBs. One method of correcting this distortion is to bootstrap the drain of the NMOS transistor MN702 to the drain of the PMOS transistor MP704 (for example, the input V _IN or the output V _INX ) so that it is no longer fixed to certain supply voltages.

FIG. 9 shows another example of the input buffer of the disclosed embodiment of the present invention. The push-pull circuit of the input buffer further includes a first-type third transistor (for example, transistor MN706) arranged in overlap with the first transistor (for example, transistor MN702), and a second transistor (for example, transistor MN706). Transistor MP704) is stacked with a second-type fourth transistor (for example, transistor MP708). At least one bootstrap stacking configuration, such as a transistor stacking with the first/second transistors, can be configured to increase the effective output impedance, thereby affecting the spurious-free dynamic range (SFDR). These stacked arrangements may need to utilize a high supply voltage to improve the performance of the input buffer. Additional overlapping settings can further improve performance.

The first stack is a transistor MN706 (such as an NMOS transistor), which is another follower _{connected to the input V IN.} The gate of the transistor MN706 can be connected to the output V _IN through the level shifter 707 and the level shifter 703 connected in series (as shown in the figure). In some embodiments, the level shifter 707 can be directly coupled to the output V _IN . The level shifter 707 or the serially connected level shifters 707 and 703 can be set as a third level shifter, which is coupled to the output V _{IN so} as to shift by crossing the third level The voltage level of the voltage input signal generated by the third voltage offset of one of the devices is offset, and a third level offset voltage signal V _{3 is} generated to bias the third transistor, such as transistor MN706. The gate of the first stacked structure MN706 is driven by the input V _IN (which fluctuates up and down). The first stacked structure MN706 has a specific level shifter 707, so the input voltage (the source of MN706) Pole) can provide sufficient V _DS to the transistor MN702 to operate in the saturation state of all states. Transistor MN706 is bootstrap connected to the input V _IN to isolate the transistor MN702 from _{changes in V DS.} If the source of the transistor MN706 (exactly) is coupled to the input or output, V _DS will be substantially constant (no change).

Depending on the allowable distortion level, more overlapping structures can be added to provide this function, such as a transistor MN710 (such as an NMOS transistor). Each stacking system can provide an extra 20dB in performance. Since the input buffer has a complementary design, the overlapping structure added to the NMOS side is also added to the PMOS side. Accordingly, a transistor MP708 (such as a PMOS transistor) can be added to bootstrap to connect and fix the V _{DS of the} transistor MP704. The gate of the transistor MP708 can be connected to the input V _IN through the level shifter 709 and the level shifter 705 connected in series. In some embodiments, the level shifter 709 can be directly coupled to the input V _IN . The level shifter 709 or the serially connected level shifters 709 and 705 can be configured as a fourth level shifter, which is coupled to the input V _IN to shift by crossing the fourth level A fourth voltage offset of the device shifts the voltage level of the voltage input signal and generates a fourth level offset voltage signal V ₄ to bias the fourth transistor, such as transistor MP708.

In the example shown, the push-pull circuit of the input buffer further includes a first-type fourth transistor (for example, transistor MN710) arranged in overlap with the third transistor (for example, transistor MN706), and with the third transistor (for example, transistor MN706). The fourth transistor (for example, the transistor MP708) is stacked with a second-type sixth transistor (for example, the transistor MP712). In other words, the second stacked structure on the NMOS side, such as transistor MN710, is finally connected to the supply. In addition, a second stacked structure on the PMOS side, such as a transistor MP712 (such as a PMOS transistor), is finally connected to the supply.

The gate of the uppermost stacked structure MN710 is driven from the source of the first stacked structure on the NMOS side, for example, driven by the level shifter 711. The level shifter 711 can be a fifth level shifter, which is coupled to a source of the third transistor (for example, transistor 706) to pass through the fifth level shifter A fifth voltage offset offsets a voltage of the source of the third transistor, and generates a fifth level offset voltage signal V ₅ to bias the fifth transistor (for example, transistor MN710). The lowermost stacked structure MP712 is driven from the source of the first stacked structure on the PMOS side, for example, driven by the level shifter 713. The level shifter 716 can be a sixth level shifter, which is coupled to a source of the fourth transistor (for example, transistor MP708) to pass through the A sixth voltage offset is offset from a voltage of the source of the fourth transistor, and a sixth level offset voltage signal V _{6 is} generated to bias the sixth transistor (for example, transistor MN710). This bootstrap structure (e.g. bootstrap connected to the source of the third/fourth transistor and the drain of the first/second transistor) can be self-connected to the non-self-connecting structure of the superimposed structure on the supply. The lifted gate-to-source capacitance unloads the buffer input and output (the two are options for bootstrap connection sources), and the supply is a major source of distortion.

In the examples shown in FIGS. 7 and 9, the bootstrap structure is mainly accomplished by connecting the gates of the transistors to the output (or some other node coupled to the output). This feature is used to reduce possible ringing, which may be caused by the bootstrap gate connection to the output. Since the bootstrap connection to the output may carry the output and add additional parasitics, input buffers that are less affected by ringing may be preferred for high-speed applications. Although there may be ringing from the upper stacking structure because it is bootstrapped connected to the source of the first stacking structure, compared to other solutions when it bootstrapped to the input or output, the upper As far as the distortion of the source of the stacked structure may cause the distortion of the input V _IN and the output V _INX , the ringing is still within the tolerable range.

Furthermore, the gates of different stacked transistors in the input buffer are bootstrapped structures as shown in FIG. 9 to improve SFDR. Similar to the descriptions of the back gates of transistors MN702 and MP704, the gates after these overlapping structures are preferably bootstrapped structures (for example, voltage changes across the back gate and source are not expected). Unfortunately, in some embodiments, V _SS is negative, which means that the drain of the transistor MP708 is a negative swing. In the 28nm CMOS process technology, the N-well of the PMOS transistor is located in the substrate, and the substrate is at 0 volts. If the N-type well system is negative, it will cause the P substrate (at 0 volts) and all the N-type wells (diode cathodes) to generate a bias voltage. If the N terminal is located below the ground plane, the diode will be biased and cause distortion. Connecting the gate electrode of the overlapped structure on the PMOS side to the source of each opposing overlapped structure (the same overlapped structure) means that it may cause distortion. The solution is to connect the gates to each other after these stacked structures, for example, after an NMOS stacked structure, connect the gates to the source of the corresponding/complementary PMOS stacked structure, and vice versa. The sources are coupled to the output, so connecting them to each other helps to bootstrap the gates (to the output) after connecting the stacked structures. _As indicated by V BGN1, a rear gate of the third transistor (for example, transistor MN706) is coupled to a source of the fourth transistor (for example, transistor MP708). _Denoted by V BGP1, a rear gate of the fourth transistor (e.g., transistor MP708) is coupled to a source of the third transistor (e.g., transistor MN706). _As indicated by V BGN2, a rear gate of the fifth transistor (for example, transistor MN710) is coupled to a source of the sixth transistor (for example, transistor MP712). _As indicated by V BGP2, a rear gate of the sixth transistor (for example, transistor MP712) is coupled to a source of the fifth transistor (for example, transistor MN710).

Connecting the rear gate to the output is less ideal because it will load a non-linear capacitance. Due to the existing large voltage across this junction, the linearity has been improved. Since the overlapped structure on the NMOS side can connect the back gates to their respective sources, and the back gates are connected to the complementary design of the source of the complementary overlapped structure, a complementary design is achieved. Complementary design and equivalent load for symmetrical pull-up or pull-down are ideal.

Method of buffering a voltage input signal

FIG. 10 is a flowchart of buffering an input signal according to an embodiment of the present invention. In step 1002, a first voltage offset set by a first level shifter (of at least one current source) is to offset the voltage input signal to generate a first signal. In step 1002, a second voltage offset set by a second level shifter (of at least one voltage source) is to offset the voltage input signal to generate a second signal. The first voltage offset and the second voltage offset can represent the level shifters 703 and 705 in FIGS. 7 and 9. The first signal and the second signal can represent V ₁ and V ₂ in FIGS. 7 and 9. The first signal is offset by a first type first transistor. In step 1004, the second signal bias is complementary to a second type second transistor of the first type. The first transistor and the second transistor system are coupled in a push-pull structure, as shown in the transistor MN702 and the transistor MP704 in FIGS. 7 and 9. In step 1006, the first transistor and the second transistor output a voltage output signal, such as V _{INX in} FIGS. 7 and 9.

In some embodiments, a first stacked transistor is coupled to the first transistor according to a third signal bias. The third signal can be coupled to the voltage input signal. In some embodiments, a second stacked transistor is coupled to the second transistor according to a fourth signal bias. The fourth signal can be coupled to the voltage input signal. For example, the third/fourth signal can be the signal V ₃ or V ₄ shown in FIG. 9.

In some embodiments, a third stacked transistor is coupled to the first stacked transistor according to a fifth signal bias. The fifth signal can be coupled to the voltage input signal. In some embodiments, a sixth signal bias is coupled to a fourth stacked transistor of the first stacked transistor. The sixth signal can also be coupled to the voltage input signal. For example, the fifth/sixth signal can be the signal V ₅ or V ₆ shown in FIG. 9.

Device for buffering an input signal

The device for buffering an input signal can be included in the implementation of the method described herein. In some embodiments, the device includes means for receiving an input signal. For example, there may be an input node to receive an input signal (such as V _IN shown in FIG. 1, FIG. 7 and FIG. 9), for example, a high frequency signal to be converted by a data converter. The device may further include push-pull means to generate an output signal. The push-pull representative can include the push-pull circuit and the push-pull structure described herein (such as the transistor seen in FIGS. 7 and 9). The device may further include a means for generating a first signal for biasing a first transistor of the push-pull means. The first signal is coupled to the input signal across all frequencies of the input signal. It may include further means to generate other signals to bias other transistors of the push-pull means. The means for generating the signal for the bias crystal may include the relative level shifter shown in FIGS. 7-9.

The signal generating means used for the bias crystals (bootstrap connecting the transistors to the input) can be distinguished from other circuits, which generate a bias signal based on a fixed/pre-defined bias voltage. These used for the bias crystal The signal generation means is coupled to the input signal or connected to the input signal across all frequencies of the input signal via bootstrap, for example, up to direct current (DC). Conversely, the other circuits that generate a bias signal based on a fixed/predefined bias voltage are not coupled to the input signal that spans all frequencies of the input signal.

For other circuits, the signal used for the bias crystal can be generated by using a fixed bias voltage and a resistor, and a capacitor in series with the input. The signals used for the bias crystal are not buffered or coupled to the input signal at a low frequency because the capacitor is controlled by a high impedance and resistance at a low frequency. Therefore, the non-bootstrap bias signal can be set by the fixed bias voltage and resistance at low frequencies (and does not respond to the input signal). On the contrary, the level shifter described here as a means of generating a bias crystal (bootstrap) signal can respond to the input signal across all frequencies (at low and high frequencies). This is because the level shifters described here have different frequency responses.

example

Example 1 is an input buffer that has: an input that receives a voltage input signal; a push-pull circuit that outputs a voltage output signal to an output, wherein the push-pull circuit has a first type first transistor, A second type second transistor complementary to the first type; and a first level shifter coupled to the input for crossing a first voltage of the first level shifter The offset shifts a voltage level of the voltage input signal, and generates a first level offset voltage signal to bias the first transistor, wherein the first level shifter provided by the first level shifter The first voltage offset is independent of a frequency of the voltage input signal.

In case 2, case 1 can further include a second level offset A shifter, coupled to the input, for shifting the voltage level of the voltage input signal by crossing a second voltage offset of the second level shifter, and generating a second level offset The voltage signal is shifted to bias the second transistor.

In example 3, example 1 or 2 may further include that the first voltage offset is programmable.

In Example 4, any one of Examples 1 to 3 may further include a current flowing through a resistive element and provided by at least one current source to set the first level shifter across the The first voltage offset.

In Example 5, any one of Examples 1 to 4 may further include that the sum of the first voltage offset and the second voltage offset is at least a first threshold voltage of the first transistor and the The second transistor is the sum of the second threshold voltage.

In Example 6, any one of Examples 1 to 5 may further include that the first voltage offset is different from the second voltage offset.

In Example 7, any one of Examples 1 to 6 may further include that the voltage output signal is biased from the voltage input signal.

In Example 8, any one of Examples 1 to 7 may further include a first back gate of the first transistor and a second back gate of the second transistor coupled to the output or follower The signal is output at this voltage.

In Example 9, any one of Examples 1 to 8 may further include a capacitor between a rear gate and a deep N-well of a first transistor that is reverse biased.

In Example 10, any one of Examples 1 to 9 may include, the push-pull circuit further has: a first-type third transistor overlapped with the first transistor And a second-type fourth transistor, which is overlapped with the second transistor.

In Example 11, any one of Examples 1 to 10 may further include a third level shifter coupled to the output for shifting by a third voltage across the third level shifter , Offset the voltage level of the voltage input signal, and generate a third-level offset voltage signal to bias the third transistor.

In Example 12, any one of Examples 1 to 11 may further include: the push-pull circuit further has: a first-type fifth transistor, which is overlapped with the third transistor; and a second-type sixth transistor The crystal is arranged in overlap with the fourth transistor.

In Example 13, any one of Examples 1 to 12 may further include a fourth level shifter, which is coupled to a source of the third transistor to pass across the fourth level shifter A fourth voltage offset offsets a voltage of the source of the third transistor and generates a fourth level offset voltage signal to bias the fifth transistor.

In Example 14, any one of Examples 1 to 13 may further include: a back gate of the third transistor is coupled to a source of the fourth transistor; and a back gate of the fourth transistor The pole is coupled to a source of the third transistor.

In Example 15, any one of Examples 1 to 14 may further include: a rear gate of the fifth transistor is coupled to a source of the sixth transistor; and a rear gate of the sixth transistor The electrode system is coupled to a source electrode of the fifth transistor.

Example 16 is a method of buffering a voltage input signal. The method includes: offsetting the voltage input signal by a first voltage offset level of a first level shifter to generate a first signal. The first voltage offset is independent of a frequency of the voltage input signal; the first signal offsets a first Type first transistor; a second type second transistor that complements the first type by a second signal offset, wherein the first transistor and the second transistor system are coupled in a push-pull structure In; and output a voltage output signal by the first transistor and the second transistor.

In Example 17, Example 16 may further include a second voltage offset set by a second level shifter to shift the level of the voltage input signal to generate the second signal.

In Example 18, Examples 16 or 17 may further include a first stacked transistor coupled to the first transistor by a third signal offset, wherein the third signal is coupled to the voltage input Signal.

In Example 19, any one of Examples 16 to 18 may further include coupling a second stacked transistor to one of the first stacked transistors by a fourth signal offset, wherein the fourth signal follows Coupled to the voltage input signal.

Example 20 is a device that includes: a means for receiving an input signal, a push-pull means for generating an output signal; and a first transistor for generating a first signal to bias the push-pull means ( Passive) means, wherein the first signal is coupled to the input signal across all frequencies of the input signal.

Example 21 is a device that includes means to implement/execute any of the methods described in Examples 16-19.

Example 101 is a bootstrap switching circuit that can accelerate startup. It includes: a sampling switch that receives a voltage input signal and a gate voltage; a bootstrap voltage generator that includes a positive feedback loop to generate the The gate voltage is used to activate the sampling switch. The positive feedback loop includes an input transistor, receives the voltage input signal, and outputs one of the gate voltages of the sampling switch. Body; and a jump start circuit for starting the output transistor for a finite period of time when the input transistor is started during the start-up phase of the positive feedback loop.

In Example 102, Example 101 may further include that the jump start circuit is coupled to a gate of the output transistor.

In Example 103, Examples 101 to 102 may further include that the jump start circuit stops starting the output transistor after the finite period of time, and enables the positive feedback loop to operate.

In Example 104, any one of Examples 101 to 103 may further include: the jump start circuit has a transistor for receiving a clock signal used to start the positive feedback loop; and the transistor system uses a delayed version of the The clock signal is activated to output the clock signal to activate the output transistor for the finite period.

In Example 105, any one of Examples 101 to 104 may further include that the jump start circuit further has two inverters to generate the delayed version of the clock signal according to the clock signal.

In Example 106, any one of Examples 101 to 105 may further include: the jump start circuit has a switch to connect a gate of the output transistor to a bias voltage to start the output transistor, and The open relationship is controlled by a control signal having a pulse, thereby closing the switch.

In Example 107, any one of Examples 101 to 106 may further include that the jump start circuit has a sensing circuit to start the jump start according to at least one state of the bootstrap switching circuit indicating the start phase of the positive feedback loop Circuit.

In Example 108, any one of Examples 101 to 107 can be further Including, the sensing circuit senses a voltage, and the voltage represents a voltage level at a node in the bootstrap switching circuit.

In Example 109, any one of Examples 101 to 108 may further include that the node is located at a node in the positive feedback loop.

In Example 110, any one of Examples 101 to 109 may further include that the sensing circuit has a comparator that compares the voltage with a predefined threshold value indicating the activation state of the positive feedback loop.

In Example 111, any one of Examples 101 to 110 may further include: the positive feedback loop has a startup capacitor; and the positive feedback loop drives the gate voltage to a voltage based on the voltage input signal and across the startup capacitor A starting voltage is generated to activate the sampling switch.

In Example 112, any one of Examples 101 to 111 may further include: the input transistor system is coupled to a first plate of the startup capacitor; and the output transistor system is coupled to a second plate of the startup capacitor Pole plate.

In Example 113, any one of Examples 101 to 112 may further include: the input transistor system is driven by the gate voltage of the sampling switch; and the positive feedback loop further has a first transistor coupled to the output A gate of the transistor and a drain of the input transistor, wherein the first transistor system is driven by the gate voltage of the sampling switch.

In Example 114, any one of Examples 101 to 113 may further include: the positive feedback loop further has: an additional transistor coupled to a gate of the output transistor and a drain of the input transistor, The additional transistor system is controlled by a clock signal that drives the positive feedback loop.

Example 115 is an accelerated start method of a sampling switch, which includes Including: outputting an output voltage of a bootstrap voltage generator through an output transistor of a positive feedback loop to drive the sampling switch; pulling a gate voltage of the output transistor to a starting voltage level to After the positive feedback loop is activated, the output transistor is activated for a period; and after the period, the gate voltage adjustment is stopped.

In Example 116, Example 115 may further include: the sampling switch receives a voltage input signal; and the positive feedback loop receives the voltage input signal from an input transistor driven by the output voltage of the output transistor, and according to the The voltage input signal generates a bootstrap voltage signal as the output voltage of the bootstrap voltage generator to activate the sampling switch when the positive feedback loop is connected.

In Example 117, Example 115 or 116 may further include adjusting the gate voltage of the output transistor, which includes changing the gate voltage from a shutdown voltage level to a startup voltage level.

In Example 118, any one of Examples 115 to 117 may further include: enabling the positive feedback loop to drive the gate voltage to a voltage level of a voltage input signal after the period, and the voltage input signal is provided to the self Lifting type voltage generator and the sampling switch.

In Example 119, any one of Examples 115 to 118 may further include: sensing only at least one state in which the positive feedback loop has been activated; and generating a control signal in response to the sensing of the at least one state, wherein the control The signal can drive the adjustment of the gate voltage of the output transistor.

Example 120 is a device that includes: sampling means, receiving an input signal to be sampled, and a control signal for enabling and disabling one of the sampling means; means for generating a bootstrap voltage based on the input signal; output means, output The control signal; the control signal is driven by the positive feedback effect of the control signal Means to activate the output means for a limited period of time during the start-up phase of the positive feedback function.

Example 121 is a device that includes means for implementing/executing the method of any one of Examples 115 to 119.

Change and implementation

A transistor, such as a metal oxide semiconductor field-effect transistor (MOSFET), has a source where the charge carrier enters the channel of the transistor. A drain of the transistor is the position where the charge carriers leave the channel. In some cases, the source and the drain may be two terminals of the transistor. A gate of a transistor can be regarded as a control terminal of the transistor, because the gate can control the conductivity of the channel (for example, the amount of current passing through a transistor). A rear gate (body) of a transistor can also be regarded as a control terminal of the transistor. The gate and the back gate can be used as terminals for biasing a transistor.

It should be noted that the activities described above with reference to the diagram can be applied to any integrated circuit that participates in processing analog signals and uses at least one analog-to-digital converter (ADC) to convert the analog signals into digital data. In a specific context, the features discussed here are generally related to analog-to-digital converters, such as various analog-to-digital converters, including pipeline analog-to-digital converters (pipeline ADC) and Delta-Sigma analog-to-digital converters (Delta-Sigma ADC) 、Successive approximation register ADC, multi-stage ADC, time-interleaved ADC, randomized time-interleaved ADC (randomized time-interleaved ADC) and so on. These features are particularly beneficial for high-speed analog-to-digital converters, whose input frequency is relatively high. Located in the gigahertz range. This analog-to-digital converter can be applied to medical systems, scientific instruments, wireless and wired communication systems (especially systems that require high sampling rates), radar, industrial process control, audio/video equipment, instrumentation and other applications that use analog-to-digital conversion The system of the device. The performance level provided by the high-speed analog-to-digital converter is suitable for the current market needs such as high-speed communication, medical imaging, synthetic aperture radar, digital dial-to-line communication systems, broadband communication systems, high-performance imaging, and advanced test/measurement systems ( Oscilloscope) is particularly beneficial.

The contents disclosed in this case cover devices that can perform various contents described herein. These devices may include circuit systems as shown and shown here. The components of different devices may include electronic circuits to perform the functions described herein. The circuit system can be operated in analog domain, digital domain or mixed signal domain. In some cases, at least one component of the device may be provided by a processor specially configured to perform the functions described herein (for example, control-related functions, time-related functions). In some cases, the processor may be an on-chip processor with the analog-to-digital converter. The processor may include at least one specific purpose component, or may include programmable logic gates configured to implement the functions described herein. In some examples, the processor may be configured to implement the functions described herein through instructions stored on a non-transitory computer medium.

In the discussion of the embodiments, the components and elements can be replaced, replaced or modified in other ways to meet the requirements of specific circuit systems. Furthermore, it should be noted that the use of complementary electronic devices, hardware, etc. can provide equivalent available options to implement the teachings disclosed herein. For example, the complementary arrangement of using PMOS transistors (P-type MOS transistors) to replace NMOS transistors (N-type MOS transistors), or vice versa, can be disclosed in this disclosure The content is known. For example, the scope of the disclosure/patent application covers the implementation of replacing all NMOS devices with PMOS devices, or vice versa. The connection relationship and the circuit system can be reset to achieve the same function. These implementations are equivalent to implementations using complementary transistor devices, because these implementations can achieve substantially the same functions or achieve substantially the same results in substantially the same way. Those skilled in the art will understand that a transistor device can generally be a device with three (main) terminals. In addition, those skilled in the field understand that a switch, transistor, or transistor device can have transistor characteristics corresponding to devices such as NMOS, PMOS devices (and any other equivalent transistor devices) in operation. effect.

In an exemplary embodiment, any number of components in the drawing can be implemented on a board of an associated electronic device. The circuit board can be a general circuit board, which can contain various components of the internal electronic system of the electronic device, and can further provide connectors for other peripheral devices. More specifically, the circuit board can provide electrical connections so that other components of the system can communicate with each other. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.) can be appropriately coupled to the circuit board based on specific configuration requirements, processing requirements, computer design, etc. Other components such as external storage, additional sensors, controllers for audio/video displays, and peripheral devices can be used as plug-in cards to be attached to the circuit board via cables, or integrated into the The circuit board itself. In various embodiments, the functionality described herein can be implemented in a simulated form as software or software running in at least one configurable (eg, programmable) component provided in a structure that supports these functions. Hardware. The software or firmware that provides the emulation can be set to include to allow a processor to perform the functions Non-transitory computer readable media capable of commanding.

In another exemplary embodiment, the components in the drawings can be implemented as independent modules (eg, a device in a circuit system with associated components and configurations to perform a specific application or function) or implemented as an electronic device. The plug-in module in the specific hardware of the device. It is worth noting that the specific embodiments disclosed in the present invention can be easily included in a system on chip (SOC) package in part or in whole. A system-on-chip means an integrated circuit (IC) that integrates the components of a computer or other electronic system into a single chip. It can include digital, analog, mixed signal and common radio frequency functions: these functions can all be arranged on a single chip substrate. Other embodiments may include a multi-chip-module (MCM), which has a plurality of individual integrated circuits, which are located in a single electronic package and are arranged to closely interact with each other through the electronic package effect. In various other embodiments, the error correction functionality can be used in at least one of Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA), and other semiconductor chips. Implemented in silicon cores.

It should be noted that all specifications, dimensions and relationships (such as the number of processors, logical operations, etc.) described herein are only provided for illustration and teaching purposes. This information can be changed considerably without departing from the spirit of the present invention and the scope of the patent application or (if applicable) the scope of the embodiments described herein. These specifications only apply to a non-limiting example, so they should be interpreted accordingly. As mentioned above, the exemplary embodiments have been described with reference to specific processor and/or component configurations. Without departing from the scope of the patent application of the present invention or (if applicable) here Under the scope of the described embodiments, various modifications and changes can be made to these embodiments. Therefore, the embodiments and drawings are for illustrative purposes only and not for limitation.

It should be noted that in the multiple examples provided here, two, three, four or more electronic components or parts can be used to describe their interaction. However, this is only used for clarity and exemplary purposes. It should be understood that the system can be enhanced in any suitable way. With reference to similar design alternatives, any of the components, modules, blocks, and components shown in the drawings can be combined in various possible settings, and these settings clearly fall within the scope of this specification. In some cases, it may be easier to describe one or more functions of a given set of streams only by referring to a limited number of electronic components. It should be understood that the circuit and its teaching system in the diagram can be easily adjusted and can be adapted to a larger number of components and more complex/precise configurations and settings. Therefore, the examples provided here should not be used to limit the scope or inhibit the potential application of this circuit to the extensive teaching of countless other architectures.

It should be noted that in this specification, regarding "one embodiment", "exemplary embodiment", "one embodiment", "another embodiment", "certain embodiments", "various embodiments", and "other embodiments" Various features (eg, elements, structures, modules, components, steps, operations, characteristics, etc.) included in "alternative embodiments", etc. mean any of these features included in at least one embodiment of the present invention , May or may not be combined in the same embodiment. It should still be noted that the functions described here only show part of the possible functions that can be performed by the system/circuit shown in the diagram. Some parts of these operations can be deleted or removed under appropriate circumstances, or these operations can be modified or changed without departing from the scope of the disclosure. In addition, the timing of these operations can be changed considerably. The above operation flow is provided for illustration and discussion purposes only. Examples described here It provides substantial flexibility and can have any appropriate configuration, chronologies, settings, and timing mechanisms without departing from the teachings disclosed in the present invention. A number of other changes, substitutions, changes, alterations and modifications can be established by those of ordinary knowledge in the technical field described in the present invention, and all such changes, substitutions, changes, alterations and modifications fall within the scope of the patent application of the present invention Scope or (if applicable) within the embodiments described here. It is worth noting that all the optional features of the above-mentioned devices can also be implemented with respect to the methods or processes described herein, and the details in these examples can be used anywhere in at least one embodiment.

Although the present invention has been disclosed as above in the preferred embodiment, it is not intended to limit the present invention. Anyone who is familiar with the art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to the scope of the attached patent application.

MN 108: Transistor

200: Bootstrap switching circuit

MP 202: Transistor

MP 204: Transistor

MN 206: Transistor

MN 208: Transistor

MN 210: Transistor

MN 212: Transistor

MP 214: Transistor

MN 216: Transistor

MN 224: Transistor

Claims (20)

An input buffer comprising: an input for receiving a voltage input signal; a first transistor of a first type; a second transistor of a second type complementary to the first type, wherein the second transistor The source of the transistor is coupled to the source of the first transistor; an output is located at the source of the first transistor and the source of the second transistor; and a first level shifter, according to The voltage input signal generates a first level offset voltage, and a voltage difference set between the gate of the first transistor and the gate of the second transistor, wherein the first level is offset The voltage is coupled to the voltage input signal across all frequencies of the voltage input signal. According to the input buffer described in claim 1, wherein at least the first level shifter biases the first transistor and the second transistor to generate a certain amount of current flowing through The first transistor and the second transistor. The input buffer described in claim 1, wherein the first level offset voltage biases the gate of the first transistor. According to the input buffer described in claim 1, wherein the first level shifter shifts the input voltage signal by a first voltage shift amount. The input buffer according to claim 4, wherein the first voltage offset is sufficient to keep the first transistor and the second transistor activated. The input buffer described in item 1 of the scope of patent application further includes: A second level shifter generates a second level shift voltage according to the voltage input signal. The input buffer as described in item 6 of the scope of patent application, wherein the second level offset voltage biases the gate of the second transistor. The input buffer described in item 1 of the scope of the patent application further includes: a copy bias element for the first level shifter to set the flow through the first transistor and the second transistor An amount of current. The input buffer according to claim 1, wherein the voltage difference is at least the sum of a threshold gate-source voltage of the first transistor and a threshold gate-source voltage of the second transistor . In the input buffer described in claim 1, wherein a voltage offset caused by the first level shifter is programmable. According to the input buffer described in claim 1, wherein the voltage difference is set at a certain offset of a voltage output signal at the output with respect to the voltage input signal. The input buffer described in claim 11, wherein the determination offset is non-zero. The input buffer described in item 1 of the scope of the patent application further includes: a third transistor of the first type, which is arranged overlapping the first transistor. The input buffer described in item 13 of the scope of patent application further includes: a third level shifter, which generates a third level offset voltage according to the voltage input signal and biases the third transistor . The input buffer described in item 1 of the scope of the patent application further includes: a fourth transistor of the second type, which is arranged overlapping the second transistor. The input buffer described in item 15 of the scope of patent application further includes: a fourth level shifter, which generates a fourth level shift voltage according to the voltage input signal and biases the fourth transistor . A method for buffering a voltage input signal includes: generating a first voltage offset signal according to the voltage input signal; biasing a first transistor of a first type according to the first voltage offset signal; The voltage input signal biases a second transistor of a second type, wherein the second type is complementary to the first type; and the source of the first transistor and the source of the second transistor A voltage output signal is output. The method for buffering a voltage input signal as described in item 17 of the scope of patent application further comprises: setting a voltage difference between the gate of the first transistor and the gate of the second transistor to at least the first The sum of a threshold gate-source voltage of a transistor and a threshold gate-source voltage of the second transistor. For example, the method for buffering a voltage input signal as described in the scope of patent application, further includes: biasing a stacked transistor coupled to the second transistor with a third signal, wherein the third signal It is coupled to the voltage input signal. An input buffer comprising: an input for receiving a voltage input signal; a first transistor of a first type; a second transistor of a second type complementary to the first type, wherein the first transistor The source of the two transistors is coupled to the source of the first transistor; an output is located at the source of the first transistor and the source of the second transistor; the second type is a third transistor , Stacked with the second transistor; a first level shifter, which generates a first level shift voltage according to the voltage input signal; and a second level shifter, which generates a first level shift voltage according to the voltage input signal A second level offset voltage is generated; wherein the first level offset voltage biases the first transistor, and the second level offset voltage biases the third transistor.

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