TWI638401B - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor component and a method of fabricating the same, wherein the semiconductor component comprises a substrate having a recess and an etch stop layer. The etch stop layer is located in the substrate, surrounding the bottom surface of the cladding recess and a portion of the sidewall.

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

As the size of semiconductor components has been gradually reduced, processes for embedding three-dimensional memories in deep trenches of substrates have been developed. However, the uniformity of the depth of each groove is difficult to control due to the load effect. The uneven groove depth will cause the Wafer acceptance test (WAT) to fail and result in a drop in yield.

Embodiments of the present invention provide a method of fabricating a semiconductor device, which can effectively improve the uniformity of the depth of the deep groove.

Embodiments of the present invention provide a semiconductor device including a substrate having a recess and an etch stop layer. The etch stop layer is located in the substrate, surrounding the bottom surface of the cladding recess and a portion of the sidewall.

In some embodiments of the invention, the etch stop layer described above includes a first doped layer, and the removal rate of the first doped layer is less than the removal rate of the substrate.

In some embodiments of the invention, the etch stop layer is a multilayer structure, and further includes a second doped layer in the first doped layer. Wherein the removal rate of the second doped layer is less than the removal rate of the first doped layer.

In some embodiments of the present invention, the second doped layer and the first doped layer comprise the same dopant, and the doping concentration of the second doped layer is higher than the doping of the first doped layer. concentration.

In some embodiments of the invention, the second doped layer and the first doped layer comprise different dopants.

In some embodiments of the invention, the dopant of the etch stop layer described above includes a boron atom, a nitrogen atom, a carbon atom, or a combination thereof.

The present invention provides a semiconductor device including a substrate having a recess and a doping structure. The doped structure is located in the substrate and is located on both sides of the groove to cover at least a portion of the sidewall of the groove.

In some embodiments of the invention, the removal rate of the doped structure described above is greater than the removal rate of the substrate.

In some embodiments of the present invention, the semiconductor component further includes a three-dimensional memory disposed in the recess.

Embodiments of the present invention provide a method of fabricating a semiconductor device, comprising providing a substrate and forming an etch control layer in the substrate. The removal rate of the etch control layer from the substrate is different. A removal process is performed to form a recess in the substrate, and at least a portion of the sidewalls of the recess are surrounded by the etch control layer. The process in which the removal process is performed to etch the control layer and the removal rate in the substrate is smaller is an etch stop layer.

Based on the above, the present invention forms an etch control layer in the substrate before forming the recess, which can control the removal rate of the removal process, thereby improving the groove depth uniformity.

The above described features and advantages of the invention will be apparent from the following description.

1A to 1F are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a first embodiment of the present invention.

Referring to Figure 1A, a substrate 10 is provided. Substrate 10 is a semiconductor substrate, such as a doped germanium substrate, an undoped germanium substrate, or an insulator overlying (SOI) substrate. The dopant doped with the ruthenium substrate may be a P-type dopant, an N-type dopant, or a combination thereof. The substrate 10 has a first region 11a and a second region 11b. In some embodiments, the first region 11a is a memory cell region; the second region 11b is a peripheral region. A deep well region 30 may be formed in the substrate 10 of the second zone 11b. In some exemplary embodiments, substrate 10 is a P-type crucible substrate and deep well region 30 is an N-type deep well region. However, the invention is not limited thereto, and in other exemplary embodiments, the substrate 10 is, for example, an N-type crucible substrate, and the deep well region 30 is, for example, a P-type deep well region. The depth range of the deep well region 30 is, for example, 1.5 μm to 2 μm. The method of forming the deep well region 30 is, for example, an ion implantation process.

With continued reference to FIG. 1A, a patterned mask layer 17 is then formed on the substrate 10. The patterned mask layer 17 has an opening 12 that exposes a portion of the substrate 10 of the first region 11a. The material of the patterned mask layer 17 is, for example, a photoresist.

Referring to FIG. 1B, an etch control layer is formed in the substrate 10 of the first region 11a. In some embodiments, the etch control layer is an etch stop layer 16. The etch stop layer 16 can be a single layer or a multilayer structure. In some embodiments, the etch stop layer 16 is a single layer structure that includes a first doped layer 13. The doping of the first doped layer 13 is such that the removal rate of the first doped layer 13 is less than the removal rate of the substrate 10 in a subsequent removal process. In some embodiments, the etch selectivity ratio of the substrate 10 to the first doped layer 13 ranges from 10:1 to 100:1.

6A and 6B are examples of concentration change graphs of the etch stop layer 16 (first doped layer 13) of FIG. 1B. Referring to the curve G1 in FIG. 6A, in some embodiments, the dopant concentration of the etch stop layer 16 may be unevenly distributed, for example, a Gaussian distribution from top to bottom along the first direction D1. Referring to the curve G0 in FIG. 6B, in other embodiments, the dopant concentration of the etch stop layer 16 (the first doped layer 13) may be substantially uniformly distributed from top to bottom along the first direction D1. The dopant concentration of the etch stop layer 16 (first doped layer 13) ranges from 10 ¹⁸ to 10 ²³ atoms/cm ³ .

The method of forming the etch stop layer 16 includes performing a doping process on the substrate 10 exposed by the opening 12 with the patterned mask layer 17 as a mask. The doping process includes an ion implantation process. The etch stop layer 16 can be formed by performing a single or multiple ion implantation process. In some embodiments, the ion implantation process uses energy in the range of 1.3 MeV to 3.25 MeV, and in other embodiments, the ion implantation process uses energy in the range of 1.2 MeV to 1.3 MeV. In some embodiments, after the ion implantation process, a post-implant anneal is further included to cause the ion implanted dopant to further diffuse.

Doping implanted dopants includes the removal of decelerating atoms, such as boron atoms, nitrogen atoms, carbon atoms, or combinations thereof. Removing the decelerating atom means that the atom causes the removal rate of the etch stop layer 16 to be less than the removal rate of the substrate 10.

The first doped layer 13 is located in the substrate 10 below the opening 12, and the width W1 of the first doped layer 13 is greater than the width W2 of the opening 12 because the post-implant annealing process causes the dopant to diffuse. In some exemplary embodiments, the distance H between the top surface of the first doping layer 13 and the top surface of the substrate 10 ranges from 1.7 μm to 2.7 μm. In other exemplary embodiments, the distance H ranges from 2.7 μm to 3.7 μm. The thickness T1 of the first doping layer 13 is, for example, in the range of 0.02 μm to 0.4 μm.

Referring to FIG. 1B and FIG. 1C , the patterned mask layer 17 is used as a mask, and the first doping layer 13 is used as the etch stop layer 16 to perform a removal process to form the recess 21 . The patterned mask layer 17 is then removed. The way to remove includes etching. The etching is, for example, dry etching, wet etching, or a combination thereof. In some embodiments in which the mode of removal is dry etching, the etching gas used in the etching process is, for example, tetrafluoromethane (CF ₄ ), trifluoromethane (CHF ₃ ), sulfur hexafluoride (SF ₆ ), or a combination thereof. In some embodiments in which the removal is wet etching, the etchant used in the etching process is, for example, potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrophthalic acid. Ethylene diamine pyrochatecol (EPP) or a combination thereof.

The depth H1 of the groove 21 is, for example, 1.7 μm to 3.7 μm; the width W3 of the groove 21 is, for example, 8 mm to 25 mm. In some embodiments, the removal process is stopped in the etch stop layer 16, that is, the substrate 10 exposed by the process removal opening 12 and a portion of the etch stop layer 16 thereunder are removed.

Referring to FIG. 1C, the bottom surface and a portion of the sidewall of the recess 21 are surrounded by the etch stop layer 16. Specifically, the etch stop layer 16 after the removal process has a bottom portion 18 and a protrusion 19 on the bottom portion 18. The convex portion 19 includes a first convex portion 19a and a second convex portion 19b. The first convex portion 19a and the second convex portion 19b are respectively located on edges of both sides of the bottom portion 18. In other words, the groove 21 is located between the first convex portion 19a and the second convex portion 19b. The bottom surface of the recess 21 exposes a portion of the top surface of the bottom portion 18; the sidewall of the recess 21 exposes the first convex portion 19a, the second convex portion 19b, and a portion of the substrate 10. The thickness L of the etch stop layer 16 to be removed is the thickness of the convex portion 19. In some embodiments, the thickness L of the etch stop layer 16 that is removed ranges from 0.01 μm to 0.4 μm. The sum (S1+S2) of the width S1 of the first convex portion 19a and the width S2 of the second convex portion 19b is the difference in width (W1-W3) between the first doping layer 13 and the groove 21. In some embodiments, the width S1 of the first convex portion 19a ranges from 0.1 μm to 20 μm. The width S2 of the second convex portion 19b ranges from 0.1 μm to 20 μm. The width S1 of the first convex portion 19a and the width S2 of the second convex portion 19b may be the same or different.

In other embodiments, the removal process is stopped until the etch stop layer 16 is barely exposed (not shown). That is, the removal process removes only a portion of the substrate 10 above the etch stop layer 16 without removing the etch stop layer 16. In other words, the etch stop layer 16 is almost completely retained. The recess 21 is located on the etch stop layer 16, and the bottom surface of the recess 21 exposes a portion of the top surface of the etch stop layer 16, and the sidewalls only expose the substrate 10.

Referring to FIG. 1D, a dielectric layer 36 is formed on the substrate 10. The dielectric layer 36 is filled into the recess 21 to cover the bottom surface and the side walls of the recess 21 and to cover the top surface of the substrate 10. The material of the dielectric layer 36 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, a low dielectric constant material having a dielectric constant of less than 4, or a combination thereof. In some embodiments, the dielectric layer 36 is, for example, a bottom oxide layer (BOX). The thickness of the dielectric layer 36 ranges, for example, from 500 angstroms to 3,000 angstroms. The method of forming the dielectric layer 36 is, for example, a thermal oxidation method, a chemical vapor deposition method, or a combination thereof. A layer of stacked structural material 39 is then formed on the dielectric layer 36. A layer of stacked structural material 39 is filled into the recess 21 and covers the top surface of the substrate 10. In some embodiments, the stacked structural material layer 39 includes a plurality of layers of insulating material 37 and a plurality of layers of semiconductor material 38 that are alternately stacked one upon another. The number of layers of the stacked structural material layer 39 can be adjusted according to the needs of the process. In some embodiments, the number of layers of stacked structural material layer 39 is, for example, 19 layers, 32 layers, or the number of layers required for any other process. The insulating material layer 37 may be a dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride, a low dielectric constant material having a dielectric constant of less than 4, or a combination thereof. The material of the layer of semiconductor material 38 is, for example, undoped polysilicon or doped polysilicon. The method of forming the stacked structural material layer 39 is, for example, a chemical vapor deposition method.

With continued reference to FIG. 1D, a patterned mask layer 40 is then formed over the substrate 10 of the first region 11a to cover a portion of the stacked structural material layer 39 in the recess 21. The patterned mask layer 40 is, for example, a photoresist.

Referring to FIG. 1D and FIG. 1E, the patterned mask layer 40 is used as a mask to remove a portion of the stacked structural material layer 39 and the underlying layer that are not covered by the patterned mask layer 40, for example, by etching. Electrical layer 36. The patterned mask layer 40 is then removed.

In some embodiments, after the foregoing processes are performed, a stacked structure 39a, a stacked structure 39b, a dielectric layer 36a, a dielectric layer 36b, and a gap 41 are formed in the recess 21. The stacked structure 39b and the dielectric layer 36b together form a spacer 48. The stacked structure 39a is located in the recess 21, covering a portion of the top surface of the bottom 18 of the etch stop layer 16. The stacked structure 39a includes a plurality of insulating layers 37a and a plurality of semiconductor layers 38a alternately stacked one upon another. The thickness of each of the insulating layers 37a is, for example, but not limited to, 200 angstroms to 500 angstroms. The thickness of each of the insulating layers 37a may be the same or different. The thickness of the semiconductor layer 38a is, for example, but not limited to, 200 angstroms to 500 angstroms. The thickness of each of the semiconductor layers 38a may be the same or different. The thickness and the number of layers of the insulating layer 37a and the semiconductor layer 38a are not limited to the above and the drawings, and can be adjusted according to actual needs. The top surface of the stacked structure 39a is substantially flush with the top surface of the substrate 10. In some embodiments, the stack structure 39a can optionally further include a cap layer (not shown) formed on a top surface thereof. The cap layer may be a single layer or a multilayer structure. The material of the cap layer may be a dielectric material such as hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof. In some embodiments, the material of the cap layer is different from the material of the insulating layer 37a, and the thickness of the cap layer is greater than the thickness of the insulating layer 37a. The formation method of the cap layer is, for example, a chemical vapor deposition method.

Referring to FIG. 1E, the spacers 48 are located on both sides of the stacked structure 39a to cover the sidewalls of the recesses 21. There is a gap 41 between the spacer 48 and the stacked structure 39a. In some embodiments, the cross-section of the gap 41 is an inverted trapezoid, an inverted triangle, a vase, or a combination thereof. In some embodiments, the bottom of the gap 41 exposes a portion of the top surface (not shown) of the bottom 18 of the etch stop layer 16.

In other embodiments, after the foregoing process is performed, in addition to forming the stacked structure 39a, the spacers 48, the dielectric layer 36a, and the gap 41 in the recess 21, a dielectric layer 36c is left at the bottom of the gap 41.

Referring to FIG. 1E, a dielectric structure 42 is formed in the gap 41. The dielectric structure 42 can be a single layer structure or a multilayer structure. The material of the dielectric structure 42 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride or a combination thereof. In some embodiments, the dielectric structure 42 is a two-layer structure including a dielectric layer 42a and a dielectric layer 42b. The top surface of the dielectric structure 42 is substantially flush with the top surface of the stacked structure 39a and the top surface of the substrate 10.

Referring to FIG. 1F, a subsequent process is performed on the first region 11a and the second region 11b of the substrate 10 to form a three-dimensional memory 50 in the first region 11a. The three-dimensional memory 50 includes a flash memory, and the flash memory is, for example, It is NAND flash memory or NOR flash memory. The MOS elements 35a/35b/35c are formed in the second region 11b. The details are as follows.

Referring to FIG. 1F, the stacked structure 39a is patterned to form a patterned stacked structure 39c. The patterned stacked structure 39c includes a plurality of insulating layers 37b and a plurality of semiconductor layers 38b alternately stacked with each other. Patterning methods include lithography and etching processes. In some embodiments, the patterned stack structure 39c is in the shape of a comb that includes a plurality of stacked patterns 39d. A plurality of trenches 43 are formed between the plurality of stacked patterns 39d, and a portion of the etch stop layer 16 or the dielectric layer 36c is exposed. The cross section of the trench 43 may be any shape, for example, a V-shape, a U-shape, a diamond shape, or a combination thereof, but the invention is not limited thereto.

Referring to FIG. 1F, a charge storage layer 44 is then formed to cover the top surface and sidewalls of the patterned stacked structure 39c and the bottom surface of the trench 43. The material of the charge storage layer 44 includes a dielectric material such as tantalum nitride, tantalum oxide or a combination thereof. The charge storage layer 44 can be a single layer or a multilayer structure. In some embodiments, the charge storage layer 44 is, for example, a single layer of hafnium oxide layer or a single layer of tantalum nitride layer. In other embodiments, the charge storage layer 44 includes a stack structure of a hafnium oxide layer, a tantalum nitride layer, and an yttrium oxide layer (ONO). The thickness of the charge storage layer 44 is, for example, between 100 angstroms and 400 angstroms. The method of forming the charge storage layer 44 is, for example, a chemical vapor deposition method.

A conductor structure 47 is then formed on the charge storage layer 44. The conductor structure 47 can be a single layer or a multilayer structure. In some embodiments, the conductor structure 47 is a two-layer structure including a first conductor layer 45 and a second conductor layer 46. The first conductor layer 45 is filled in the plurality of trenches 43 and covers the top surface of the substrate 10 of the first region 11a. The material of the first conductor layer 45 is, for example, undoped polysilicon or doped polysilicon. The method of forming the first conductor layer 45 is, for example, a chemical vapor deposition method. The second conductor layer 46 is formed on the first conductor layer 45. The material of the second conductor layer 46 includes a metal, a metal alloy, a metal halide, or a combination thereof. The metal or metal alloy is, for example, copper, aluminum, tungsten or an alloy thereof. The metal halide is, for example, tungsten telluride. The formation method of the second conductor layer 46 is, for example, a chemical vapor deposition method or a physical vapor deposition method.

So far, the three-dimensional memory 50 has been formed, which includes a patterned stacked structure 39c, a charge storage layer 44, and a conductor structure 47. In some embodiments, the conductor structure 47 acts as a word line of the three-dimensional memory 50. Each of the semiconductor layers 38b in the patterned stacked structure 39c serves as a bit line of the three-dimensional memory 50, and thus the patterned stacked structure 39c is also referred to as a bit line stacked structure. In other embodiments, the conductor structure 47 acts as a bit line of the three dimensional memory 50. Each of the semiconductor layers 38b in the patterned stacked structure 39c serves as a word line of the three-dimensional memory 50.

Referring to FIG. 1F, a first well region 31a, a second well region 31b, and a third well region 31c are formed in the substrate 10 of the second region 11b. In some embodiments, the first well region 31a is formed in the deep well region 30. The first well region 31a, the second well region 31b, and the third well region 31c have a depth ranging from 100 angstroms to 20,000 angstroms. In some embodiments in which the deep well zone 30 is an N-type well zone, the first well zone 31a is a P-type well zone, the second well zone 31b is an N-type well zone, and the third well zone 31c is a P-type well zone. The first well region 31a, the second well region 31b, and the third well region 31c may be formed separately or simultaneously by an ion implantation process.

An isolation structure 27 is then formed between each well region 31a/31b/31c. The method of forming the isolation structure 27 is, for example, a shallow trench isolation method. Thereafter, a first MOS element 35a is formed in the first well region 31a, a second MOS device 35b is formed in the second well region 31b, and a third MOS device 35c is formed in the third well region 31c. The first MOS device 35a includes a gate dielectric layer 33a, a conductor layer 34a, and a source and drain region 32a. The second MOS device 35b includes a gate dielectric layer 33b, a conductor layer 34b, and a source and drain region 32b. The third MOS device 35c includes a gate dielectric layer 33c, a conductor layer 34c, and a source and drain region 32c. In the deep well area 30 is an N-type well area, the first well area 31a is a P-type well area, the second well area 31b is an N-type well area, and the third well area 31c is a P-type well area, in the embodiment, the first MOS The element 35a, the second MOS element 35b, and the third MOS element 35c are NMOS, PMOS, and NMOS elements, respectively.

Continuing to refer to FIG. 1F, the process of forming the three-dimensional memory 50 in the first region 11a and the process of forming the respective components in the second region 11b may be performed simultaneously or sequentially. Thereafter, the components of the three-dimensional memory 50 and the second region 11b of the first region 11a can be electrically connected by a metal interconnection, and then, subsequent processes are performed.

In the first embodiment, since the etch stop layer 16 is doped with the removal of the decelerating atoms, the substrate 10 has a high etching selectivity ratio to the etch stop layer 16 when the removal process forming recess 21 is performed, and thus, when When the removal rate of each area of the circle is uneven, the etch stop layer 16 is formed in the substrate 10, which can improve the uniformity of removal of each area of the wafer, reduce the load effect, and thereby improve the plurality of grooves formed on the wafer. The uniformity of depth.

2A to 2E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the etch stop layer 116 of the present embodiment has a two-layer structure including a first doped layer 13 and a second doped layer 14.

Referring to FIG. 1B and FIG. 2A, after the first doping process is performed on the substrate 10 to form the first doping layer 13 in FIG. 1B, the patterned mask layer 17 is used as a mask, and the corresponding position below the opening 12 is first. The doping layer 13 performs a second doping process to form the second doping layer 14 in the first doping layer 13. The first doped layer 13 and the second doped layer 14 together form an etch stop layer 116. The second doping layer 14 is located in the first doping layer 13 , and the height difference H2 from the top surface to the top surface of the first doping layer 13 ranges from 0.01 μm to 0.2 μm. The thickness T2 of the second doped layer 14 ranges from 0.02 μm to 0.39 μm.

The first doping process and the second doping process may be ion implantation processes having different process conditions that are continuously or discontinuously performed. The dopant implanted in the second doping process is to remove the decelerating atoms. In some embodiments, the dopant doped by the second doping process is the same as the dopant implanted by the first doping process, and the dopant concentration of the second doping layer 14 is higher than the first doping. The concentration of the dopant of layer 13. In some embodiments, the doping concentration of the etch stop layer 116 from top to bottom in the first direction D1 is changed from the first doped layer 13 to the second doped layer 14 from low to high, and then from the second doped layer 14 . The first doped layer 13 is changed from high to low.

FIG. 7 is a graph showing the concentration change of the etch stop layer 116 from top to bottom in the first direction D1 of FIG. 2A. Referring to FIG. 7 , in some exemplary embodiments, the concentration curves of the first doping process and the second doping process implant dopant are G1 and G2, respectively. The dopant concentration change curve of the entire etch stop layer 116 is G3. The curve G1, the curve G2, and the curve G3 all have a Gaussian distribution. The peak value and the kurtosis coefficient of the curve G1, the curve G2, and the curve G3 are sequentially increased. The peak value of the curve G3 is approximately equal to the sum of the peak values of the curve G1 and the curve G2.

Since the dopant of the etch stop layer 116 is to remove the decelerating atoms, the higher the dopant concentration, the smaller the removal rate. That is, in the subsequent removal process, the removal rate of the second doping layer 14 is smaller than the removal rate of the first doping layer 13.

In some embodiments, the dopant doped by the second doping process is different from the dopant implanted by the first doping process, and the removal rate of the second doping layer 14 is smaller than that of the first doping layer 13 The rate of removal. That is, the removal rate of the intermediate position of the etch stop layer 116 is smaller than the removal rate of the upper and lower sides thereof. In some exemplary embodiments, the dopant of the first doped region 13 is, for example, boron or nitrogen; the dopant of the second doped region 14 is, for example, carbon.

Referring to FIG. 2A and FIG. 2B , the patterned mask layer 17 is used as a mask, and the first doping layer 13 and the second doping layer 14 are collectively used as an etch stop layer 116 to perform a removal process for opening. A groove 21 is formed in the exposed substrate 10. The patterned mask layer 17 is then removed. In some embodiments, the removal process stops at the second doped layer 14 in the etch stop layer 116, that is, the substrate 10 exposed by the process removal opening 12 and a portion of the first doped layer 13 thereunder are removed. And a portion of the second doped layer 14. However, the present invention is not limited thereto, and the removal process may stop at the etch stop layer 116 just bare or stop at any position in the etch stop layer 116.

With continued reference to FIG. 2B, the etch stop layer 116 after the removal process has a bottom portion 18 and a raised portion 19. The convex portion 19 includes a first convex portion 19a and a second convex portion 19b. The structural features of the bottom portion 18 and the convex portion 19 of the etch stop layer 116 and their positional relationship with the groove 21 are substantially the same as those of the first embodiment, and will not be described herein. Different from the first embodiment, the bottom portion 18 and the convex portion 19 of the present embodiment may be a single layer structure or a multilayer structure, respectively, depending on the position at which the removal process is stopped.

Referring to FIG. 2C to FIG. 2E, substantially the same process as the first embodiment is performed to form a three-dimensional memory 50 in the first region 11a, and a well region 31a/31b/31c in the second region 11b, and in each The well regions 31a/31b/31c form MOS elements 35a/35b/35c, respectively.

3A to 3E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a third embodiment of the present invention. The embodiment is different from the previous embodiment in that the etch stop layer 216 of the present embodiment has a three-layer structure including a first doped layer 13, a second doped layer 14, and a third doped layer 15.

Referring to FIG. 2A and FIG. 3A, after the second doping layer 14 is formed in the first doping layer 13 in FIG. 2A, the second doping layer 14 is performed with the patterned mask layer 17 as a mask. A doping process is performed to form a third doped layer 15 in the second doped layer 14. The first doped layer 13, the second doped layer 14 and the third doped layer 15 together form an etch stop layer 216. The third doped layer 15 is located in the second doped layer 14. In some embodiments, the height difference H3 from the top surface of the third doped layer 15 to the top surface of the second doped layer 14 is 0.01 μm. 0.2 μm. The thickness T3 of the third doped layer 15 ranges from 0.02 μm to 0.38 μm.

The first doping process, the second doping process, and the third doping process may be ion implantation processes having different process conditions that are continuously or discontinuously performed. In some embodiments in which the first doped layer 13 and the second doped layer 14 comprise the same dopant, and the doping concentration of the second doped layer 14 is higher than the doping concentration of the first doped layer 13 The third doped layer 15 includes a different dopant than the first doped layer 13 and the second doped layer 14 such that the removal rate of the third doped layer 15 is less than the removal rate of the second doped layer 14 . In some exemplary embodiments, the dopants of the first doped layer 13 and the second doped layer 14 are, for example, boron or nitrogen, and the dopant of the third doped layer 15 is, for example, carbon. In other embodiments, the first doped layer 13, the second doped layer 14, and the third doped layer 15 comprise the same dopant, and the third dopant layer 15 has a higher dopant concentration than the second doping layer. The concentration of the dopant of the impurity layer 14 is such that the removal rate of the third doping layer 15 is less than the removal rate of the second doping layer 14. It should be noted that the above are examples of different concentrations or different dopants of the doped layers, but the invention is not limited thereto. Each doped layer can change the removal rate of the first doped layer 13, the second doped layer 14, and the third doped layer 15 sequentially by adjusting the concentration of the dopant or doping the different dopants. small. That is, the removal rate of the etch stop layer 216 is first decreased from top to bottom in the first direction D1 and then incremented, that is, the doping layer removal rate at the upper intermediate position of the etch stop layer 216 is the smallest.

Referring to FIG. 3B , the patterned mask layer 17 is used as a mask, and the first doping layer 13 , the second doping layer 14 , and the third doping layer 15 are collectively used as an etch stop layer 216 to perform a removal process. To form the groove 21. The removal process may stop when the etch stop layer 216 is bare exposed or stop at any of the etch stop layers 216.

With continued reference to FIG. 3B, in some embodiments in which the removal process is stopped in the etch stop layer 216, the etch stop layer 216 after the removal process includes the bottom 18 and the protrusions 19. The convex portion 19 includes a first convex portion 19a and a second convex portion 19b. The structural features of the bottom portion 18 and the convex portion 19 and their positional relationship with the groove 21 are similar to those of the previous embodiment, and will not be described herein. The bottom portion 18 and the convex portion 19 of the present embodiment may be a single layer structure or a multilayer structure, respectively, depending on the position at which the removal process is stopped.

Referring to FIG. 3C to FIG. 3E, a process substantially the same as that of the first embodiment is performed to form a three-dimensional memory 50 in the first region 11a, and a well region 31a/31b/31c in the second region 11b, and in each The well regions 31a/31b/31c form MOS elements 35a/35b/35c, respectively.

In the above embodiments, the etch stop layer 16/116/216 is a single layer or a two layer or a three layer structure, but the invention is not limited thereto. The etch stop layer 16/116/216 may include three or more layers of doped layers, and the etch stop layer 16/116/216 is located from the top to the bottom of the etch stop layer by adjusting the concentration and dopant of each doped layer. The removal rate of the doped layer at the location is minimal. In other words, the substrate 10 has the highest etch selectivity ratio for the doped layer located intermediate the etch stop layer 16/116/216.

In the second and third embodiments, since the etch stop layer 116/216 is a multi-layer structure and the doping layer removal rate at the middle position is the lowest, the removal rate of each region of the wafer can be better improved. Sexuality, which in turn improves the uniformity of different deep trenches on the wafer.

4A to 4E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a fourth embodiment of the present invention. This embodiment differs from the previous embodiment in that the dopant of the etch control layer of the present invention removes the acceleration atoms such that the removal rate of the etch control layer is higher than the removal rate of the substrate 10 during the removal process.

Referring to FIG. 1A and FIG. 4A , after the patterned mask layer 17 is formed on the substrate 10 in FIG. 1A , the patterned mask layer 17 is used as a mask to dope the substrate 10 exposed by the opening 12 . A doping structure 26 is formed in the substrate 10. The doped structure 26 can be a single layer structure or a multilayer structure. In some embodiments, the doping structure 26 is a single layer structure that includes a first doped layer 23. The doping process includes an ion implantation process, an ion diffusion process, or a combination thereof. The doped structure 26 can serve as an etch control layer, the dopant of which includes the removal of an accelerating atom, such as a phosphorus atom. In some embodiments, the doping of the doped structure 26 has a concentration ranging from 10 ¹⁸ to 10 ²⁰ atoms per cubic centimeter (atom/cm ³ ).

Removing the accelerated atom means that the atom causes the removal rate of the doped structure 26 to be greater than the removal rate of the substrate 10 during subsequent removal processes. In some embodiments, the first doping layer 23 has an etch selectivity ratio to the substrate 10 ranging from 5:1 to 10:1.

The doped structure 26 is located in the substrate 10 below the opening 12 and has a width W11 that is greater than the width W12 of the opening 12. In some embodiments, the top surface of the doped structure 26 is substantially flush with the top surface of the substrate 10. The thickness T11 of the doped structure 26 ranges from 0.1 μm to 3.7 μm.

Referring to FIG. 4B, with the patterned mask layer 17 as a mask, a removal process is performed to remove the doped structure 26 exposed by the opening 12 and a portion of the substrate 10 therebelow to form a recess 121 in the substrate 10. . The patterned mask layer 17 is then removed. The way to remove includes etching. The etching is, for example, dry etching, wet etching, or a combination thereof. In some embodiments where the removal is dry etching, the etching gas used in the etching process is, for example, CF4. In some embodiments where the removal is wet etching, the etchant used in the etching process is, for example, KOH. The removal process is performed as the etch stop layer with the doping structure 26 (etch control layer) and the substrate 10 having a lower removal rate. That is, in this embodiment, the removal process is based on the substrate 10 underlying the doped structure 26 as an etch stop layer. In some embodiments, the removal process is stopped in the substrate 10 below the doped structure 26. However, the present invention is not limited thereto. In other embodiments, the removal process may also stop when the substrate 10 is barely exposed.

With continued reference to FIG. 4B, in some embodiments, the bottom of the recess 121 exposes the substrate 10; and its sidewalls expose the doped structure 26. In other embodiments, the bottom of the recess 121 exposes the substrate 10; and its sidewalls expose the doped structure 26 and the substrate 10. The depth H11 of the groove 121 is, for example, 1.7 μm to 3.7 μm; and the width W13 of the groove 121 is, for example, 8 mm to 25 mm. The doped structure 26 after the removal process includes a first portion 26a and a second portion 26b, respectively located on opposite sides of the recess 121, covering at least a portion of the sidewalls of the recess 121. The sum (S1+S2) of the width S11 of the first portion 26a and the width S12 of the second portion 26b is the difference in width (W11-W13) between the doping structure 26 and the groove 121.

4C to 4E, a process substantially the same as that of the first embodiment is performed to form a three-dimensional memory 50 in the first region 11a, and a well region 31a/31b/31c in the second region 11b, and in each The well regions 31a/31b/31c form MOS elements 35a/35b/35c, respectively.

5A to 5E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a fifth embodiment of the present invention. The present embodiment is different from the fourth embodiment in that, in the embodiment, the doping structure 126 is a multi-layered structure including a first doping layer 123, a second doping layer 24, and a third doping layer 25.

Referring to FIG. 5A, the patterned mask layer 17 is used as a mask, and the substrate 10 exposed by the opening 12 is doped to form a first contact with each other in the substrate 10 from the top to the bottom in the first direction D1. The doped layer 123, the second doped layer 24, and the third doped layer 25. The first doped layer 123, the second doped layer 24, and the third doped layer 25 together form a doped structure 126. The top surface of the first doped layer 123 is substantially flush with the top surface of the substrate 10 and has a thickness ranging from 0.1 μm to 3.7 μm. The thickness of the second doping layer 24 ranges from 0.1 μm to 3.7 μm. The thickness of the third doping layer 25 ranges from 0.1 μm to 3.7 μm. The thickness of each doped layer may be the same or different. Each doping process includes an ion diffusion process, an ion implantation process, or a combination thereof. As with the fourth embodiment, the doping structure 126 acts as an etch control layer whose doping includes removal of the accelerating atoms. The concentration of each doped layer 123/24/25 in the doped structure 126 is sequentially increased from top to bottom along the first direction D1. In other words, the removal rates of the first doping layer 123, the second doping layer 24, and the third doping layer 25 in the doping structure 126 in the subsequent removal process are sequentially increased.

Referring to FIG. 5A and FIG. 5B, the masking layer 17 is used as a mask to perform a removal process, and the doped structure 126 exposed by the opening 12 and a portion of the substrate 10 under the opening 12 are removed to form in the substrate 10. Groove 121. The patterned mask layer 17 is then removed. As in the fourth embodiment, in the removal process, the substrate 10 having a smaller removal rate is used as an etch stop layer. The removal process stops just before the substrate 10 under the doped structure 126 is exposed, or a portion of the substrate 10 that stops below the doped structure 126 is removed. The doped structure 126 after removal includes a first portion 126a and a second portion 126b. The first portion 126a and the second portion 126b are both multi-layered structures. The structural features of the recess 121 and its positional relationship with the doped structure 126 are similar to those of the fourth embodiment and will not be described again.

Referring to FIG. 5C to FIG. 5E, substantially the same process as the first embodiment is performed to form a three-dimensional memory 50 in the first region 11a, and a well region 31a/31b/31c in the second region 11b, and in each The well regions 31a/31b/31c form MOS elements 35a/35b/35c, respectively.

The fourth embodiment and the fifth embodiment are examples in which the doping structures 26/126 are respectively a single layer structure or a three layer structure. However, the present invention is not limited thereto, and the doping structure 26/126 may also be a two-layer structure or a multi-layer structure of more than three layers. When the doped structure 26/126 is a multi-layer structure, the concentration of the doped layers of each layer is sequentially increased from top to bottom, so that the removal rate of the doped layers of each layer is sequentially increased. In some embodiments, the concentration of the doped layers of each layer gradually increases from top to bottom in a gradient, and the removal rate of the doped layers of each layer also gradually decreases with a gradient change.

In the above embodiment, since the stacked structure 39a is formed in the recess 21/121 and its top surface is substantially flush with the top surface of the substrate 10, the depth H1/H11 of the recess 21/121 depends on the stacked structure 39a. The number of layers. That is, the more the number of layers of the stacked structure 39a, the deeper the depth H1/H11 of the grooves 21/121. It should be noted that the distance H between the top surface of the etch stop layer 16/116/216 and the top surface of the substrate 10 and its thickness and the thickness of the doped structure 26/126 may be as required by the depth of the groove 21/121 H1/H11. And adjust accordingly. In addition, the above embodiment is an example in which the three-dimensional memory 50 is formed in the recess 21/121, but the invention is not limited thereto, and the manufacturing method of controlling the uniformity of the groove by etching the control layer and the obtained concave The trench structure can also be applied to the fabrication of other semiconductor components.

In summary, the present invention controls the uniformity (U%) of the groove depth by doping the substrate to form an etch control layer. In some embodiments, the uniformity can be increased by 90%. Specifically, the first to third embodiments form an etch stop layer in the substrate. The etch stop layer formed in the substrate can reduce the removal rate difference of different regions of the wafer, that is, reduce the load effect of the wafer, thereby improving the uniformity of the depth of each groove. The fourth to fifth embodiments form an etch accelerating layer in the substrate, which also reduces the load effect, thereby improving the uniformity of the groove depth in different regions.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Base

11a‧‧‧First District

11b‧‧‧Second District

12‧‧‧ openings

13/23/123‧‧‧First doped layer

14/24‧‧‧Second doped layer

15/25‧‧‧ third doped layer

16‧‧‧etch stop layer

17‧‧‧ patterned mask layer

18‧‧‧ bottom

19‧‧‧ convex

19a‧‧‧First convex

19b‧‧‧second convex

21/121‧‧‧ Groove

26‧‧‧Doped structure

27‧‧‧Isolation structure

30‧‧‧Shenjing District

31a/31b/31c‧‧‧ Well Area

32a/32b/32c‧‧‧ source and bungee

33a/33b/33c‧‧‧ gate dielectric layer

34a/34b/34c‧‧‧ conductor layer

35a/35b/35c‧‧‧ gate structure

36‧‧‧Dielectric layer

37‧‧‧Insulation layer

37a/37b‧‧‧Insulation

38‧‧‧Semiconductor material layer

38a/38b‧‧‧Semiconductor layer

39‧‧‧Stacked structural material layer

39a‧‧‧Stack structure

39b‧‧‧ spacer

39c‧‧‧ patterned stacking structure

39d‧‧‧Stacking pattern

40‧‧‧ patterned mask layer

41‧‧‧ gap

42‧‧‧Dielectric structure

42a/42b‧‧‧ dielectric layer

43‧‧‧ Ditch

44‧‧‧Charge storage layer

45/46‧‧‧ conductor layer

47‧‧‧Conductor structure

48‧‧‧ spacer

50‧‧‧Three-dimensional memory

D1‧‧‧ first direction

W1, W2, W3, W11, W12, W13, S1, S2, S11, S12‧‧ Width

T1, T2, T3, T11, L‧‧‧ thickness

H‧‧‧ distance

H1, H2, H3, H11‧‧ depth

G0, G1, G2, G3‧‧‧ curves

1A to 1F are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a first embodiment of the present invention. 2A to 2E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention. 3A to 3E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a third embodiment of the present invention. 4A to 4E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a fourth embodiment of the present invention. 5A to 5E are cross-sectional views showing the flow of a method of fabricating a semiconductor device in accordance with a fifth embodiment of the present invention. 6A to 6B are graphs showing changes in concentration of the etch stop layer in Fig. 1B. Fig. 7 is a graph showing the concentration change of the etch stop layer in Fig. 2A.

Claims (10)

A semiconductor device comprising: a substrate having a recess therein; and an etch stop layer disposed in the substrate surrounding a bottom surface and a portion sidewall of the recess, wherein the recess exposes the etch Stop at least a portion of the layer. The semiconductor device of claim 1, wherein the etch stop layer comprises a first doped layer, and a removal rate of the first doped layer is less than a removal rate of the substrate. The semiconductor device of claim 2, wherein the etch stop layer is a multilayer structure, further comprising a second doped layer in the first doped layer, wherein the second doped layer The removal rate is less than the removal rate of the first doped layer. The semiconductor device of claim 3, wherein the second doped layer and the first doped layer comprise the same dopant, and the second doped layer has a higher dopant concentration than The concentration of the dopant of the first doped layer. The semiconductor device of claim 3, wherein the second doped layer and the first doped layer comprise different dopants. The semiconductor device according to any one of claims 1 to 5, wherein the dopant of the etch stop layer comprises a boron atom, a nitrogen atom, a carbon atom or a combination thereof. A semiconductor component comprising: a substrate having a recess therein; and a doping structure located in the substrate and located on both sides of the recess covering at least a portion of the sidewall of the recess, wherein a sidewall of the recess is exposed The doped structure, the bottom of the recess exposes the substrate. The semiconductor device of claim 7, wherein the removal rate of the doped structure is greater than the removal rate of the substrate. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device further includes a three-dimensional memory disposed in the recess. A method of fabricating a semiconductor device, comprising: providing a substrate; forming an etch control layer in the substrate, wherein a rate of removal of the etch control layer from the substrate is different; and performing a removal process to form a recess In the substrate, at least a portion of sidewalls of the recess are surrounded by the etch control layer, wherein the removal process is an etch stop layer with a lower removal rate of the etch control layer and the substrate.