TWI638443B - Semiconductor device, semiconductor device manufacturing method and overlay error measurement method for semiconductor device - Google Patents

Abstract

A method for measuring a coverage error of a semiconductor device, comprising: performing a diffraction-based overlay error measurement on a first test target of the substrate to obtain a first diffraction intensity difference of the first stacked structure corresponding to the first test target a value, and a second diffraction intensity difference of the second stacked structure corresponding to the first test target; and obtaining a corresponding first test according to an average value of the first diffraction intensity difference and the second diffraction intensity difference The third diffraction intensity difference of the target.

Description

Semiconductor device, semiconductor device manufacturing method, and measurement method of coverage error of semiconductor device

Embodiments of the present invention relate to a coverage error measurement, and more particularly to a coverage error measurement of a semiconductor device.

In general, a semiconductor integrated circuit (IC) is formed in a plurality of material layers of a semiconductor substrate (or semiconductor wafer). In order to properly manufacture the above semiconductor integrated circuit, each material layer in the above substrate needs to be aligned with the previous material layer. To achieve this, the test error (or alignment mark) formed in the above substrate can be used to measure the overlay error.

The test object described above may include a plurality of gratings and utilize the configuration of the gratings described above to measure overlay errors between different layers of material of the substrate. Although the existing test objectives have met the above general purpose, they still cannot satisfy all aspects.

Embodiments of the present invention provide a semiconductor device including a substrate. The substrate includes a first material layer and a second material layer stacked on each other. The first material layer includes: a first grating and a second grating, arranged side by side in the first direction And in the first rectangular area of the test area; and the third grating and the fourth grating are arranged side by side in the first direction in the second rectangular area of the test area. The second material layer includes: a fifth grating overlapping the first grating and having a first positional offset from the first grating in a second direction perpendicular to the first direction; and a sixth grating, The third grating is superposed and has a first positional offset between the third grating and the second grating. The first position offset consists of a predetermined position offset and a coverage error.

Embodiments of the present invention provide a method for measuring a coverage error of a semiconductor device. The method includes: performing a diffraction-based overlay error measurement on a first test target of the substrate to obtain a first diffraction intensity difference corresponding to the first stacked structure of the first test target, and obtaining a corresponding first test target a second diffraction intensity difference of the second stacked structure; and obtaining a third diffraction intensity difference corresponding to the first test target according to an average of the first diffraction intensity difference and the second diffraction intensity difference .

Embodiments of the present invention provide a method of fabricating a semiconductor device. The manufacturing method includes: forming, in a first material layer of the substrate, a first grating and a second grating disposed side by side in a first rectangular region of the test region in a first direction; and forming a first layer in the first material layer a third grating and a fourth grating disposed side by side in a second rectangular region of the test region in one direction; in the second material layer of the substrate, formed to overlap the first grating and in a direction perpendicular to the first direction a fifth grating having a first positional offset between the first grating and the first grating; and in the second material layer, formed to overlap the third grating and having a second grating along the second direction The sixth grating offset by the first position. The first position offset consists of a predetermined position offset and a coverage error.

100‧‧‧Overlay error measurement system

101‧‧‧Light source

102‧‧‧Optical device

103‧‧‧Base

104‧‧‧Semiconductor device

LI, LR‧‧‧ rays

105‧‧‧Photodetection circuit

106‧‧‧ Processor

201-204‧‧‧Stacked structure

M1, M2‧‧‧ material layer

G1-G4‧‧‧ grating

D‧‧‧predetermined position offset

Dt1, dt2‧‧‧ position offset

D1, D2‧‧‧ direction

S1, S2‧‧‧ area

H1‧‧‧ distance

Dt3, dt4‧‧‧ position offset

D3, D4‧‧ Direction

P‧‧‧ position offset

A, A1-A2, A10-A20‧‧‧Diffraction intensity difference

E‧‧‧error value

OT1-OT8‧‧‧Overlay structure

+X, -X, +Y, -Y‧‧ Direction

RT‧‧‧ test area

R1-R4‧‧‧ rectangular area

G41-G48, G51-G58‧‧ ‧ grating

L1-L8‧‧‧raster parts

Dt51, dt52, dt61, dt62‧‧‧ position offset

P1, P2‧‧‧ position offset

AX1-AX4, AY1-AY4, AS1-AS4‧‧‧Diffraction intensity difference

E1-E4‧‧‧ difference

101-103, 111-113, 121-124‧‧‧ operations

1 is a schematic diagram of a coverage error measurement system in accordance with an embodiment of the present invention.

2A, 2B are cross-sectional views of a stacked structure in accordance with an embodiment of the present invention.

Figure 3A is a schematic illustration of a substrate in accordance with an embodiment of the present invention.

Figure 3B is a cross-sectional view of a stacked structure in accordance with an embodiment of the present invention.

Figure 3C is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

Figure 3D is a graph of the relationship between positional offset and diffraction intensity difference in accordance with an embodiment of the present invention.

4A and 4B are schematic views of a semiconductor device in accordance with an embodiment of the present invention.

5A-5D are cross-sectional views of a stacked structure in accordance with an embodiment of the present invention.

Figure 6 is a graph showing the relationship between the positional shift and the diffraction intensity difference in accordance with an embodiment of the present invention.

7A-7D are cross-sectional views of a stacked structure in accordance with an embodiment of the present invention.

Figure 8 is a graph showing the relationship between the positional shift and the diffraction intensity difference in accordance with an embodiment of the present invention.

9A and 9B are schematic views of a semiconductor device in accordance with an embodiment of the present invention.

Figure 10 is a diagram showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

Figure 11 is a measurement method of the overlay error of the semiconductor device in accordance with an embodiment of the present invention.

Fig. 12 is a view showing a measurement method of a cover error of a semiconductor device according to an embodiment of the present invention.

The following disclosure provides many different embodiments or examples to implement various features of the present invention. The following disclosure sets forth specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if a first feature is formed on or above a second feature, it may mean that the first feature is directly in contact with the second feature, and may include additional features. Formed between the first feature and the second feature described above such that the first feature and the second feature are not in direct contact with each other.

Spatially related terms used in the following, such as "below", "below", "lower", "above", "higher" and the like, are used to facilitate the description of one element in the illustration. Or the relationship between a feature and another component or feature(s). In addition to the orientation depicted in the drawings, these spatially relative terms are also meant to refer to devices that may be used in different orientations or in operation.

The same component numbers and/or characters may be repeated in the following various embodiments, which are for the purpose of simplicity and clarity, and are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

The vocabulary of the first and second terms used hereinafter is for illustrative purposes only and is not intended to limit or limit the scope of the patent. In addition, the first feature and the second feature are not limited to the same or different features.

In the drawings, the shape or thickness of the structure may be enlarged to simplify or facilitate the marking. It is to be understood that elements not specifically described or illustrated may be in various forms well known to those skilled in the art.

Figure 1 is an overlay error (overlay) in accordance with an embodiment of the present invention. Error) A schematic diagram of the measurement system 100. The overlay error measurement system 100 includes a light source 101, an optical device 102, a substrate 103, a light detecting circuit 105, and a processor 106. In some embodiments, substrate 103 includes a semiconductor device 104 and substrate 103 can be a wafer. In some embodiments, substrate 103 includes a plurality of material layers, and semiconductor device 104 includes a grating structure formed on layers of different materials and stacked on one another.

In some embodiments, overlay error measurement system 100 can perform a Diffraction-based overlay (DBO) based on semiconductor device 104. For example, light source 101 is configured to provide light to optical device 102, while optical device 102 is configured to cause light LI to illuminate semiconductor device 104. In turn, the light ray LI illuminates the semiconductor device 104 to produce light LR, and the light LR includes at least one primary diffracted light having a different diffraction about the light ray LI. The light detecting circuit 105 is configured to detect the light LR, and the processor 106 is configured to receive the data of the light detector 105 (for example, the image data formed by the light LR in the light detecting circuit 105), and analyze the data to The overlay error between the gratings of the different material layers of the semiconductor device 104 is determined.

In some embodiments, the processor 106 can be configured to analyze the difference in light intensity of the diffracted light of the different diffractions detected by the light detecting circuit 105, thereby analyzing and determining the grating of the different material layers of the semiconductor device 104. Coverage error. In some embodiments, the above-described diffraction-based overlay error measurement is performed after a lithography process.

In some embodiments, the semiconductor device 104 includes a stacked structure 201 and a stacked structure 202. FIG. 2A depicts a schematic diagram of a partially stacked structure 201 and a partially stacked structure 202. The stacked structure 201 comprises a layer of material M1, M2 The gratings G1, G2, and the grating members of the gratings G1, G2 are individually arranged along the direction D1 and have a predetermined positional offset d in the direction D1. The stacked structure 202 includes gratings G3, G4 formed in the material layers M1, M2, and the grating members of the gratings G3, G4 are individually arranged along the direction D2 (opposite to the direction D1) and have a predetermined positional offset in the direction D2 d. In some embodiments, the predetermined position offset d is a pre-designed parameter. The processor 106 can determine the overlay error between the gratings G1, G2 or the gratings G3, G4 of the semiconductor device 104 based on the predetermined position offset d.

For example, in some embodiments, the semiconductor device 104 has a overlay error between the material layer M1 and the material layer M2 during the fabrication (eg, lithography process), such as the stacked structure 203 shown in FIG. 2B. And the stacked structure 204.

FIG. 2B depicts a schematic diagram of a partially stacked structure 203 and a partially stacked structure 204. When the gratings G1, G2 of the stacked structure 203 are formed on the semiconductor device 104, the gratings G1, G2 have a predetermined positional offset d and a positional deviation dt1 formed by the overlay error de in the direction D1. The gratings G3, G4 of the stacked structure 204 have a predetermined positional offset d and a positional deviation dt2 formed by the overlay error de in the direction D2. If the direction D1 is defined as the positive direction and the direction D2 is defined as the negative direction, the positional deviations dt1 and dt2 are as shown in the equations (1) and (2). In some embodiments, the direction of the overlay error de may be direction D1 or direction D2.

(1) dt1=d+de

(2) dt2=-d+de

In some embodiments, the light ray LI generates light LR based on the stacked structure 203 having the positional shift dt1 and the stacked structure 204 having the positional shift dt2, and the light ray LR is detected by the photodetector 105. The processor 106 determines a first diffraction intensity difference (ASY1) of the corresponding stacked structure 203 based on the data of the photodetector 105. And a second diffraction intensity difference (ASY2) corresponding to the stacked structure 204, and further determining the coverage error by the equation (3). In some embodiments, the first diffraction intensity difference ASY1 may be a light intensity difference of the +1st order diffraction and the -1st order diffraction of the corresponding stacked structure 203, and the second diffraction intensity difference ASY2 may be In order to correspond to the light intensity difference between the +1st order diffraction and the -1st order diffraction of the stacked structure 204, the embodiment of the present invention is not limited thereto.

FIG. 3A depicts a top view of a portion of the substrate 103 in accordance with an embodiment of the present invention. In this embodiment, the substrate 103 includes a region S1 and a region S2, and the semiconductor device 104 is formed in the region S1 and the region S2. FIG. 3B depicts a cross-sectional view of a portion of the semiconductor device 104 in region S1 and region S2, respectively, in accordance with an embodiment of the present invention. In FIG. 3B, the gratings G1, G2 in the region S1 have a predetermined positional offset in the direction D3 and a positional deviation dt3 formed by a covering error (for example, a positional shift corresponding to the equation (1)), On the other hand, the gratings G3 and G4 in the region S2 have the above-described predetermined positional shift and the positional deviation dt4 formed by the above-mentioned overlay error in the direction D4 (opposite to the direction D3) (for example, the positional shift corresponding to the equation (2)) .

In some embodiments, when the grating distances in the regions S1 and S2 are both the distance H1 and the distribution is uniform (as shown in FIG. 3B), the light LR generated by the light ray LI irradiating the gratings G1 and G2 in the region S1 has a winding. The intensity difference A10 is emitted, and the light LR generated by the gratings G3, G4 irradiated by the light ray LI in the region S2 has a diffraction intensity difference A20. The processor 106 can generate a correct overlay error based on the diffraction intensity differences A10, A20 and the predetermined position offset described above (eg, generated by Equation (3)).

In some embodiments, the thickness of each material layer of the substrate 103 has It may change, causing a change in the distance between layers of different materials, as shown in Figure 3C. Figure 3C is a cross-sectional view of a semiconductor device 104 in accordance with an embodiment of the present invention. In this embodiment, since the thickness of the substrate 103 is not uniform, the light ray LI illuminates between the light LR generated by the gratings G1, G2 of the region S1 and the light LR emitted by the light ray LI at the gratings G3, G4 of the region S2. Additional diffracted light deviations (eg, deviations in diffraction intensity differences) may result from different thicknesses of the substrate 103, causing the processor 106 to determine coverage between the gratings G1, G2 or gratings G3, G4 of the semiconductor device 104. An error occurs in the error.

For example, when the thickness distribution of the regions S1, S2 is as shown in FIG. 3C, the light LR generated by the gratings G1, G2 irradiated by the light ray LI in the region S1 has a diffraction intensity difference A1, and the light ray LI is irradiated in the region. The light LR generated by the gratings G3, G4 of S2 has a diffraction intensity difference A2 as shown in Fig. 3D. Figure 3D is a plot of positional offset P versus diffraction intensity difference A (e.g., +1 order diffraction versus -1 order diffracted light intensity difference) in accordance with an embodiment of the present invention. The diffraction intensity differences A1, A2 produce additional diffracted light deviations based on the thickness variation of the substrate 103, and thus differ from the diffraction intensity differences A10, A20 by an error value E, respectively. In this case, when the diffraction intensity differences A1, A2 and the predetermined position offset are brought into the equation (3), the generated overlay error will have an error value.

Embodiments of the present invention provide an implementation of a plurality of semiconductor devices, such as semiconductor device 104, thereby reducing the effect of thickness variations of the substrate on overlay error measurements.

4A is a schematic diagram of a semiconductor device 104 in accordance with an embodiment of the present invention. The semiconductor device 104 includes a stacked structure OT1 to a stacked structure OT8. In some embodiments, the stacked structure OT1~the stacked structure OT8 individually includes a base formed Two gratings of different material layers of the bottom 103. In this embodiment, the direction +X and the direction +Y are perpendicular to each other; the direction +X and the direction -X are opposite to each other; and the direction +Y and the direction -Y are opposite to each other.

In some embodiments, the arrangement of the semiconductor device 104 of FIG. 4A in one of the first material layers of the substrate 103 is as shown in FIG. 4B. Referring to the content of FIG. 4B, the grating G41 of the stacked structure OT1, the grating G42 of the stacked structure OT2, the grating G43 of the stacked structure OT3, the grating G44 of the stacked structure OT4, the grating G45 of the stacked structure OT5, and the stacked structure A grating G46 of the OT6, a grating G47 of the stacked structure OT7, and a grating G48 of the stacked structure OT8 are formed in the test area RT. In some embodiments, overlay error measurement system 100 causes light LI to simultaneously illuminate test area RT of semiconductor device 104 when performing diffraction-based overlay error measurements. In some embodiments, the gratings G41 to G44 are used to measure the overlay error in the direction +X (or the direction -X), and the gratings G45 to G48 are used to measure the direction +Y (or the direction -Y). Coverage error.

According to the content of FIG. 4B, the grating G41 and the grating G42 are arranged side by side in the rectangular region R1 of the test region RT in the direction +Y (or the direction -Y), and the grating member L1 of the grating G41 and the grating member L2 of the grating G42 are individually arranged. Arrange along the direction +X (or direction -X). The grating G43 and the grating G44 are arranged side by side in the rectangular region R3 of the test region RT in the direction +Y (or the direction -Y), and the grating member L3 of the grating G43 and the grating member L4 of the grating G44 are individually in the direction +X (or direction) -X) Arrange. The grating G45 and the grating G46 are arranged side by side in the rectangular region R2 of the test region RT in the direction +X (or the direction -X), and the grating member L5 of the grating G45 and the grating member L6 of the grating G46 are individually in the direction +Y (or direction) -Y) Arrange. The grating G47 and the grating G48 are arranged side by side in the direction +X (or the direction -X) at the moment of the test area RT In the shaped region R4, the grating member L7 of the grating G47 and the grating member L8 of the grating G48 are individually arranged in the direction +Y (or the direction -Y).

In some embodiments, the arrangement of the stacked structure OT1~the stacked structure OT4 on the first material layer of the substrate 103 is as shown in FIG. 4B, and the stacked structure OT1~the stacked structure OT4 is at the first of the substrate 103. The arrangement in the material layer and a second material layer (overlying the first material layer described above) is as shown in Figures 5A-5D.

Figure 5A depicts a cross-sectional view of a partially stacked structure OT1. The stacked structure OT1 includes a grating G41 formed on the first material layer and a grating G51 formed on the second material layer. The grating G51 and the grating G41 are superposed on each other, and the grating G51 has a positional shift dt51 between the grating + G41 along the direction +X. The positional shift dt51 is composed of a predetermined positional shift (d0) and a coverage error (OVL1), such as the content shown in the above formula (1) or (2).

Figure 5B depicts a cross-sectional view of a partially stacked structure OT3. The stacked structure OT3 includes a grating G43 formed on the first material layer and a grating G53 formed on the second material layer. The grating G53 and the grating G43 are superposed on each other, and the grating G53 has a positional shift dt51 between the direction +X and the grating G43.

Figure 5C depicts a cross-sectional view of a partially stacked structure OT2. The stacked structure OT2 includes a grating G42 formed on the first material layer and a grating G52 formed on the second material layer. The grating G52 and the grating G42 are superposed on each other, and the grating G52 has a positional shift dt52 between the grating G42 along the direction -X. The positional shift dt52 is composed of the above-described predetermined positional shift (d0) and the above-described overlay error (OVL1). In some embodiments, if the positional offset dt51 corresponds to the above formula (1), the positional offset dt52 corresponds to the above formula (2); if the positional deviation dt51 corresponds to the above formula (2), the positional deviation The shift dt52 corresponds to the above formula (1).

Figure 5D depicts a cross-sectional view of a partially stacked structure OT4. The stacked structure OT4 includes a grating G44 formed on the first material layer and a grating G54 formed on the second material layer. The grating G54 and the grating G44 are superposed on each other, and the grating G54 has a positional shift dt52 between the grating G44 along the direction -X.

In some embodiments, the first material layer of FIGS. 5A-5D may be below the second material layer.

In some embodiments, overlay error measurement system 100 performs diffraction-based overlay error measurements on semiconductor device 104 of FIG. 4A. For example, light source 101 is configured to provide light to optical device 102, while optical device 102 is configured to cause light LI to illuminate semiconductor device 104 of FIG. 4A. In turn, the light ray LI illuminates the semiconductor device 104 of FIG. 4A to produce light LR, and the light LR includes at least one primary diffracted light having a different diffraction about the light ray LI. The light LR is detected by the light detecting circuit 105, and the processor 106 is configured to receive the data detected by the light detector 105.

Fig. 6 is a graph showing the relationship between the positional shift P1 and the diffraction intensity difference A (e.g., the light intensity difference of the +1st order diffraction and the -1st order diffraction) according to an embodiment of the present invention. In some embodiments, if the thickness of the substrate 103 at the position corresponding to the rectangular regions R1, R3 is uniform and flat (that is, the distance between the first material layer and the second material layer is maintained at a specific distance), the corresponding overlay The diffraction intensity difference of the structure OT1 (or the stacked structure OT3) is AS1, and the diffraction intensity difference of the corresponding stacked structure OT2 (or the stacked structure OT4) is AS2, as shown in FIG. In some embodiments, the processor 106 can determine the semiconductor device 104 of FIG. 4A in the +X direction (or -X based on the diffraction intensity differences AS1, AS2 of the stacked structures OT1, OT4 or stacked structures OT3, OT2). The above coverage error (OVL1) of the direction, ie:

In some embodiments, the positional offset between the gratings G41, G51 of the stacked structure OT1 is also dt51 (in the direction +X) and the positional offset between the gratings G44, G54 of the stacked structure OT4 is also dt52 ( In the direction -X), but the thickness of the substrate 103 at the position corresponding to the rectangular regions R1, R3 is uneven and has a variation (that is, the distance between the first material layer and the second material layer is not maintained at a specific distance). In this embodiment, the thickness of the substrate 103 at the position corresponding to the rectangular regions R1, R3 varies, causing the diffraction intensity difference of the corresponding stacked structure OT1 to decrease from the diffraction intensity difference AS1 to the diffraction intensity difference AX1 (decreasing The difference E1), and the diffraction intensity difference corresponding to the stacked structure OT4 is increased from the diffraction intensity difference AS2 to the diffraction intensity difference AX4 (rise difference E1), as shown in FIG. Therefore, the overlay error that processor 106 determines based on the diffraction intensity differences AX1, AX4 will have additional offset values.

In some embodiments, the positional offset between the gratings G43, G53 of the stacked structure OT3 is also dt51 (in the direction +X) and the positional offset between the gratings G42, G52 of the stacked structure OT2 is also dt52 ( Along the direction -X). Since the stacked structure OT2 is formed in the rectangular region R1 as well as the stacked structure OT1, and the stacked structure OT3 is formed in the rectangular region R3 as well as the stacked structure OT4, the above-mentioned thickness of the substrate 103 at the position corresponding to the rectangular regions R1, R3 The change has a similar effect on the stacked structures OT1, OT4 and the stacked structures OT2, OT3. For example, when the diffraction intensity difference AX1 of the corresponding stacked structure OT1 falls by the difference E1 and the diffraction intensity difference AX4 of the stacked structure OT4 rises by the difference E1, the diffraction intensity difference of the corresponding stacked structure OT2 The value AX2 falls by the difference E2 and corresponds to the diffraction intensity difference AX3 of the stacked structure OT3 rising by the difference E2, as shown in FIG.

In some embodiments, the difference E1 is the same as the difference E2. In this case, the processor 106 averages the diffraction intensity differences AX1, AX3 to generate a diffraction intensity difference AS1; the processor 106 averages the diffraction intensity differences AX2, AX4 to generate a diffraction intensity difference AS2. . In turn, processor 106 can generate a overlay error that excludes or reduces the bias caused by the thickness variation of substrate 103 based on the diffraction intensity differences AS1, AS2.

In some embodiments, the difference E2 approximates the difference E1 (eg, the difference between the difference E2 and the difference E1 is less than 10% of the difference E1, but the embodiment of the present invention is not limited thereto). In this case, the processor 106 averages the diffracted intensity differences AX1, AX3 to produce a first average diffractive intensity difference that approximates the diffractive intensity difference AS1; the processor 106 sets the diffracted intensity difference AX2. AX4 averaging produces a second average diffraction intensity difference that approximates the diffraction intensity difference AS2. In turn, the processor 106 can generate a overlay error that reduces the bias caused by the thickness variation of the substrate 103 based on the first and second average diffraction intensity differences.

In some embodiments, the stacked structures OT1, OT3 belong to the same test target in the above-described diffraction-based overlay error measurement, and the diffraction intensity difference AS1 (or the first average diffraction intensity difference) is the above test. The difference in diffraction intensity of the target. In some embodiments, the stacked structures OT2, OT4 belong to the same test target in the above-described diffraction-based overlay error measurement, and the diffraction intensity difference AS2 (or the second average diffraction intensity difference) is the above test. The difference in diffraction intensity of the target.

Based on the above embodiment, even if the thickness of the substrate 103 at the position corresponding to the rectangular regions R1, R3 is uneven and has a variation, the semiconductor device 104 (for example, the content shown in FIG. 4A) provided by the embodiment of the present invention can provide the same bit. a set of stacked structures (eg, stacked structures OT1, OT3 or stacked structures OT2, OT4) that are offset and affected by the opposite thickness, thereby enabling the overlay error measurement system 100 to measure the set of stacked structures and obtain Diffraction intensity difference (e.g., diffraction intensity difference AS1 or AS2) that is not affected by the thickness of the substrate 103 or a diffraction intensity difference that is less affected by the thickness of the substrate 103 (e.g., the first and second average diffraction intensity differences described above) value). In turn, the processor 106 can generate a coverage error that excludes or reduces the deviation caused by the thickness variation of the substrate 103 based on the diffraction intensity differences AS1, AS2; or the processor 106 can be based on the first and second average diffraction intensities The difference produces a coverage error that reduces the deviation caused by the thickness variation of the substrate 103.

In some embodiments, the arrangement of the stacked structure OT5~the stacked structure OT8 on the first material layer of the substrate 103 is as shown in FIG. 4B, and the stacked structure OT5~the stacked structure OT8 is at the first of the substrate 103. The arrangement of the material layer and the above second material layer is as shown in Figs. 7A to 7D.

Figure 7A depicts a cross-sectional view of a partially stacked structure OT5. The stacked structure OT5 includes a grating G45 formed on the first material layer and a grating G55 formed on the second material layer. The grating G55 and the grating G45 are superposed on each other, and the grating G55 has a positional shift dt61 between the grating + G45 along the direction +Y. The positional shift dt61 is composed of a predetermined positional shift (d10) and a coverage error (OVL2), such as the content shown in the above formula (1) or (2).

Figure 7B depicts a cross-sectional view of a partially stacked structure OT7. The stacked structure OT7 includes a grating G47 formed on the first material layer and a grating G57 formed on the second material layer. The grating G57 and the grating G47 are superposed on each other, and the grating G57 has a positional shift dt61 between the grating + G47 along the direction +Y.

Figure 7C depicts a cross-sectional view of a partially stacked structure OT6. Stacked structure The OT 6 includes a grating G46 formed on the first material layer and a grating G56 formed on the second material layer. The grating G56 and the grating G46 are superposed on each other, and the grating G56 has a positional shift dt62 between the grating G46 along the direction -Y. The positional shift dt62 is composed of the above-described predetermined positional shift (d10) and the above-described overlay error (OVL2). In some embodiments, if the positional deviation dt61 corresponds to the above formula (1), the positional deviation dt62 corresponds to the above formula (2); and if the positional deviation dt61 corresponds to the above formula (2), the positional deviation The shift dt62 corresponds to the above formula (1).

Figure 7D depicts a cross-sectional view of a partially stacked structure OT8. The stacked structure OT8 includes a grating G48 formed on the first material layer and a grating G58 formed on the second material layer. The grating G58 and the grating G48 are superposed on each other, and the grating G58 has a positional shift dt62 between the grating G48 along the direction -Y.

In some embodiments, the first material layer of FIGS. 7A-7D may be below the second material layer.

In some embodiments, the overlay error measurement system 100 performs a diffraction-based overlay error measurement on the semiconductor device 104 of FIG. 4A, and the processor 106 in turn obtains the data as shown in FIG. Figure 8 is a graph showing the relationship between the positional shift P2 and the diffraction intensity difference A (e.g., the light intensity difference of the +1st order diffraction and the -1st order diffraction) according to an embodiment of the present invention. In some embodiments, if the thickness of the substrate 103 at the position corresponding to the rectangular regions R2, R4 is uniform and flat (that is, the distance between the first material layer and the second material layer is maintained at a specific distance), the corresponding overlay The diffraction intensity difference of the structure OT5 (or the stacked structure OT7) is AS3, and the diffraction intensity difference of the corresponding stacked structure OT6 (or the stacked structure OT8) is AS4, as shown in FIG. In some embodiments, the processor 106 can determine the semiconductor device 104 of FIG. 4A in the +Y direction (or -Y based on the diffraction intensity differences AS3, AS4 of the stacked structures OT5, OT8 or stacked structures OT7, OT6). The above coverage error (OVL2) of the direction, ie:

In some embodiments, the positional offset between the gratings G45, G55 of the stacked structure OT5 is also dt61 (in the direction +Y) and the positional offset between the gratings G48, G58 of the stacked structure OT8 is also dt62 ( In the direction -Y), but the thickness of the substrate 103 at the position corresponding to the rectangular regions R2, R4 is uneven and has a variation (that is, the distance between the first material layer and the second material layer is not maintained at a specific distance). In this embodiment, the thickness of the substrate 103 at the position corresponding to the rectangular regions R2, R4 changes, causing the difference in the diffraction intensity of the corresponding stacked structure OT5 to decrease from the diffraction intensity difference AS3 to the diffraction intensity difference AY5 (decreased The difference E3), and the diffraction intensity difference corresponding to the stacked structure OT8 is increased from the diffraction intensity difference AS4 to the diffraction intensity difference AY8 (rise difference E3), as shown in FIG. Therefore, the overlay error that processor 106 determines based on the diffraction intensity differences AY5, AY8 will have additional offset values.

In some embodiments, the positional offset between the gratings G47, G57 of the stacked structure OT7 is also dt61 (in the direction +Y) and the positional offset between the gratings G46, G56 of the stacked structure OT6 is also dt62 ( Along the direction -Y). Since the stacked structure OT6 is formed in the rectangular region R2 as well as the stacked structure OT5, and the stacked structure OT7 and the stacked structure OT8 are formed in the rectangular region R4, the thickness of the substrate 103 at the position corresponding to the rectangular regions R2, R4 The change will have a similar effect on the stacked structures OT5, OT8 and the stacked structures OT6, OT7. For example, when the diffraction intensity difference AY5 of the corresponding stacked structure OT5 falls by the difference E3 and the diffraction intensity difference AY8 of the stacked structure OT8 rises by the difference E3, the corresponding stacked structure The diffraction intensity difference AY6 of OT6 falls by the difference E4 and the diffraction intensity difference AY7 of the stacked structure OT7 rises by the difference E4, as shown in Fig. 8.

In some embodiments, the difference E3 is the same as the difference E4. In this case, the processor 106 averages the diffraction intensity differences AY5, AY7 to generate a diffraction intensity difference AS3; the processor 106 averages the diffraction intensity differences AY6, AY8 to generate a diffraction intensity difference AS4. . In turn, the processor 106 can generate a coverage error that excludes or reduces the deviation caused by the thickness variation of the substrate 103 based on the diffraction intensity differences AS4, AS4.

In some embodiments, the difference E4 approximates the difference E3 (eg, the difference between the difference E4 and the difference E3 is less than 10% of the difference E3, but the embodiment of the present invention is not limited thereto). In this case, the processor 106 averages the diffraction intensity differences AY5, AY7 to generate a first average diffraction intensity difference of the approximate diffraction intensity difference AS3; the processor 106 sets the diffraction intensity difference AY6, AY8 averaging produces a second average diffraction intensity difference that approximates the diffraction intensity difference AS4. In turn, the processor 106 can generate a overlay error that reduces the bias caused by the thickness variation of the substrate 103 based on the first and second average diffraction intensity differences.

In some embodiments, the stacked structures OT5, OT7 belong to the same test target in the above-described diffraction-based overlay error measurement, and the diffraction intensity difference AS3 (or the first average diffraction intensity difference) is the above test. The difference in diffraction intensity of the target. In some embodiments, the stacked structures OT6, OT8 belong to the same test target in the above-described diffraction-based overlay error measurement, and the diffraction intensity difference AS4 (or the second average diffraction intensity difference) is the above test. The difference in diffraction intensity of the target.

Based on the above embodiment, even if the substrate 103 is in a corresponding rectangular area The thicknesses of the locations of R2 and R4 are non-uniform and vary, and the semiconductor device 104 (such as shown in FIG. 4A) provided by the embodiments of the present invention can provide a stack of stacks having the same positional offset and being affected by the opposite thickness. The structure (eg, the stacked structures OT5, OT7 or stacked structures OT6, OT8), such that the overlay error measurement system 100 can measure the set of stacked structures and obtain a diffraction intensity difference that is not affected by the thickness of the substrate 103 ( For example, the diffraction intensity difference AS3 or AS4) or the diffraction intensity difference (for example, the first and second average diffraction intensity differences described above) that is less affected by the thickness of the substrate 103. In turn, the processor 106 can generate a coverage error that excludes or reduces the deviation caused by the thickness variation of the substrate 103 based on the diffraction intensity differences AS3, AS4; or the processor 106 can be based on the first and second average diffraction intensities The difference produces a coverage error that reduces the deviation caused by the thickness variation of the substrate 103.

In some embodiments, the greater the difference E1 or the difference E2, the greater the thickness variation of the substrate 103 at the locations of the corresponding rectangular regions R1, R3. Therefore, the processor 106 can determine the thickness variation of the substrate 103 at the position of the corresponding rectangular regions R1, R3 based on the magnitude of the value of at least one of the differences E1, E2. In some embodiments, the greater the difference E3 or the difference E4, the greater the thickness variation of the substrate 103 at the locations of the corresponding rectangular regions R2, R4. Therefore, the processor 106 can determine the thickness variation of the substrate 103 at the position of the corresponding rectangular regions R2, R4 based on the magnitude of the value of at least one of the differences E3, E4.

In some embodiments, processor 106 may generate overlay errors corresponding to different stacked structures based on diffraction intensity differences AS1, AS2, AX1 - AX4. For example, processor 106 can generate the following overlay errors.

The overlay error (OVL01) corresponds to the stacked structures OT1 and OT2; the overlay error (OVL02) corresponds to the stacked structures OT1 and OT4; the overlay error (OVL03) corresponds to the stacked structures OT2 and OT3; and the overlay error (OVL04) corresponds to the stacked structure OT3 , OT4. In some embodiments, the greater the standard deviation of at least one of the overlay error (OVL01), the overlay error (OVL02), the overlay error (OVL03), the overlay error (OVL04) and the overlay error (OVL1), the representative substrate 103 is The thickness variation corresponding to the position of the rectangular regions R1, R3 is larger. Therefore, the processor 106 can determine the thickness variation of the substrate 103 at the position of the corresponding rectangular regions R1, R3 based on the above-described standard deviation.

In some embodiments, processor 106 may generate overlay errors corresponding to different stacked structures based on diffraction intensity differences AS3, AS4, AY5~AY8. For example, processor 106 can generate the following overlay errors.

Coverage error (OVL05) corresponds to overlay structure OT5, OT6; overlay error (OVL06) corresponds to overlay structure OT5, OT8; overlay error (OVL07) corresponds The stacked structures OT6, OT7; and the overlay error (OVL08) correspond to the stacked structures OT7, OT8. In some embodiments, the larger the standard deviation of at least one of the overlay error (OVL05), the overlay error (OVL06), the overlay error (OVL07), and the overlay error (OVL08) and the overlay error (OVL2), the representative substrate 103 is The thickness variation corresponding to the position of the rectangular regions R2, R4 is larger. Therefore, the processor 106 can determine the thickness variation of the substrate 103 at the position of the corresponding rectangular regions R2, R4 based on the above-described standard deviation.

In some embodiments, the configuration of the stacked structure OT1~the stacked structure OT8 of the semiconductor device 104 can be as shown in FIGS. 9A and 9B. In FIG. 9A, the relative positions of the stacked structures OT1 and OT2 are opposite to the positions of the stacked structures OT1 and OT2 of FIG. 4A; the relative positions of the stacked structures OT3 and OT4 and the stacked structures of FIG. 4A are OT3 and OT4. The position of the stacked structures OT5 and OT6 is opposite to that of the stacked structures OT5 and OT6 of FIG. 4A; the relative positions of the stacked structures OT7 and OT8 and the positions of the stacked structures OT7 and OT8 of FIG. 4A in contrast. In FIG. 9B, the relative positions of the stacked structures OT3 and OT4 are opposite to the positions of the stacked structures OT3 and OT4 of FIG. 4A; the relative positions of the stacked structures OT7 and OT8 and the stacked structures of the 4AA are OT7 and OT8. The opposite position. In some embodiments, the areas of the rectangular area R1 to the rectangular area R4 in the test area RT may not be equal.

Figure 10 is a diagram of a method of fabricating a semiconductor device (e.g., semiconductor device 104) in accordance with an embodiment of the present invention, the method including operations 101-103. In operation 101, in a first material layer of a substrate, a first grating and a second grating are disposed side by side in a first rectangular region of one of the test regions in a first direction; a third grating and a first grating disposed in the first rectangular direction and disposed in the second rectangular region of one of the test regions The fourth grating.

In operation 102, in a second material layer of the substrate, a first grating is stacked on the first grating and a first direction is formed in a second direction perpendicular to the first direction and the first grating a fifth grating having a positional shift (e.g., positional offset dt51); and in the second material layer, formed to overlap the third grating and between the second grating and the third grating a sixth grating having the first positional offset described above.

In operation 103, in the second material layer, a second positional offset (eg, a positional offset dt52) is formed between the second grating and the second grating. a seventh grating; and in the second material layer, forming an eighth grating overlapping the fourth grating and having the second positional offset between the third direction and the fourth grating .

In some embodiments, the third direction is opposite to the second direction. In some embodiments, the first positional offset is comprised of a predetermined position offset and a coverage error. In some embodiments, the second position offset is composed of the predetermined position offset and the overlay error (eg, the first position offset and the second position offset respectively correspond to Equations (1) and (2). ), or respectively correspond to the formula (2) and the formula (1)).

In some embodiments, the operation 101 further includes forming, in the first material layer, a ninth grating and a tenth grating disposed side by side in the second rectangular area of one of the test areas in the second direction; In the first material layer, an eleventh grating and a twelfth grating which are arranged side by side in the fourth rectangular region of the test region in the second direction are formed. In some implementations In an example, operation 102 and operation 103 can be performed simultaneously.

Figure 11 is a measurement method of overlay error of a semiconductor device (e.g., semiconductor device 104) in accordance with an embodiment of the present invention, the method including operations 111-113. In operation 111, diffraction-based coverage is performed on one of the first test targets of a substrate (eg, stacked structures OT1, OT3, stacked structures OT2, OT4, stacked structures OT5, OT7, or stacked structures OT6, OT8) Error measurement. In operation 112, a first diffraction intensity difference corresponding to the first stacked structure of the first test target is obtained, and a second diffraction intensity corresponding to the second overlapping structure of the first test target is obtained. Difference. In operation 113, a third diffraction intensity difference corresponding to the first test target is obtained according to the average value of the first diffraction intensity difference and the second diffraction intensity difference.

Figure 12 is a diagram showing a method of measuring the overlay error of a semiconductor device (e.g., semiconductor device 104) in accordance with an embodiment of the present invention, the method including operations 121-124. In operation 121, one of the first test targets (for example, the stacked structures OT1, OT3 or the stacked structures OT5, OT7) and a second test target (for example, the stacked structure OT2, the OT4 or the stacked structure OT6, OT8) Performs a diffraction-based overlay error measurement.

In operation 122, a first diffraction intensity difference (eg, a diffraction intensity difference AX1) corresponding to one of the first test targets (eg, the stacked structure OT1) is obtained; a third diffraction intensity difference (eg, a diffraction intensity difference AX3) of one of the second overlapping structures (eg, the stacked structure OT3) of the test target; obtaining a third stacked structure corresponding to one of the second test targets ( For example, a second diffraction intensity difference (for example, a diffraction intensity difference AX2) of the stacked structure OT2) and a fourth overlapping structure corresponding to the second test target (for example) A fourth diffraction intensity difference (eg, a diffraction intensity difference AX4) of the stacked structure OT4).

In operation 123, a fifth diffraction intensity difference corresponding to the first test target is obtained according to the average value of the first diffraction intensity difference and the third diffraction intensity difference; and the second winding according to the second winding And an average value of the difference between the intensity of the radiation intensity and the fourth diffraction intensity is obtained as a sixth diffraction intensity difference corresponding to the second test target.

In operation 124, a coverage error (eg, overlay error (OVL1) is generated based on the fifth diffraction intensity difference, the sixth diffraction intensity difference, and a predetermined position offset (eg, a predetermined position offset (d0)). ).

In some embodiments, the predetermined positional offset described above is a pre-designed parameter. In some embodiments, the method for measuring the overlay error of the semiconductor device of FIG. 12 further includes: generating the fifth diffraction intensity difference and the first diffraction intensity difference (or the third diffraction intensity difference) a first difference; and determining a thickness variation of the substrate based on the first difference. For example, if the first difference is larger, the thickness variation of the substrate is larger. In some embodiments, the method for measuring a coverage error of the semiconductor device of FIG. 12 further includes: generating the sixth diffraction intensity difference and the second diffraction intensity difference (or the fourth diffraction intensity difference) a second difference; and determining a thickness variation of the substrate based on the second difference. For example, if the second difference is larger, the thickness variation of the substrate is larger.

In some embodiments, the method for measuring a coverage error of the semiconductor device of FIG. 12 further includes: generating a first based on the first diffraction intensity difference, the fourth diffraction intensity difference, and the predetermined position offset Coverage error; The thickness variation of the substrate is determined based on the first coverage error and a standard deviation of the overlay error. For example, the greater the standard deviation described above, the greater the variation in thickness of the substrate.

Embodiments of the present invention provide a method of measuring a coverage error of a semiconductor device (eg, semiconductor device 104), which is based on averaging diffraction intensity differences of different stacked structures to obtain an unaffected (or less) substrate (eg, a substrate) 103) The average diffraction intensity difference of the thickness influence (for example, the diffraction intensity difference AS1 or AS2). Then, based on the average diffraction intensity difference described above, a coverage error that eliminates or reduces the deviation caused by the thickness variation of the substrate can be generated.

The foregoing summary of the invention is inferred by the claims It will be understood by those of ordinary skill in the art, and other processes and structures may be readily designed or modified on the basis of the present disclosure, and thus achieve the same objectives and/or achieve the same embodiments as those described herein. The advantages. Those of ordinary skill in the art should also understand that such equivalent structures are not departing from the spirit and scope of the invention. Various changes, permutations, or alterations may be made in the present disclosure without departing from the spirit and scope of the invention.

Claims (10)

A semiconductor device comprising: a substrate comprising a first material layer and a second material layer stacked on each other; wherein the first material layer comprises: a first grating and a second grating, in a first side Arranged side by side in a first rectangular area of one of the test areas; and a third grating and a fourth grating disposed side by side in the first direction in a second rectangular area of the test area; wherein the first The two material layers include: a fifth grating superposed on the first grating and having a first positional offset from the first grating in a second direction perpendicular to the first direction; a sixth grating overlapping the third grating and having the first positional offset between the third grating and the third grating; wherein the first positional offset is offset by a predetermined position The shift consists of a cover error. The semiconductor device of claim 1, wherein the second material layer further comprises: a seventh grating, stacked on the second grating, and along a third direction and the second grating Having a second positional offset; and an eighth grating overlapping the fourth grating and having the second positional offset between the third and third gratings; wherein The two position offset consists of the predetermined position offset and the overlay error; Wherein the third direction is opposite to the second direction. The semiconductor device of claim 2, wherein the first material layer further comprises: a ninth grating and a tenth grating, and the third rectangle is arranged side by side in the second direction in the second direction And an eleventh grating and a twelfth grating disposed side by side in the second direction in a fourth rectangular region of the test region; wherein the second material layer comprises: a thirteenth grating And the ninth grating is overlapped, and has a third positional offset between the ninth grating and the ninth grating; and a fourteenth grating, overlapping the eleventh grating, and Having the third positional offset between the first and second elliptical gratings; wherein the third positional offset is comprised of a second predetermined positional offset and a second overlay error; wherein The third rectangular region has a pair of adjacent sides, one of the pair of adjacent sides is in contact with one of the sides of the first rectangular area, and the other of the pair of adjacent sides is in contact with one of the sides of the second rectangular area. The semiconductor device of claim 3, wherein the second material layer further comprises: a fifteenth grating, overlapping the tenth grating, and the tenth along a fourth direction Having a fourth positional offset between the gratings; and a sixteenth grating overlapping the twelfth grating and having the fourth positional offset between the twelfth grating along the fourth direction Shifting; wherein the fourth position offset is offset from the second predetermined position by the second The cover error is composed; wherein the fourth direction is opposite to the first direction. A method for measuring a coverage error of a semiconductor device, comprising: performing a diffraction-based overlay error measurement on a first test target of a substrate to obtain a first overlay structure corresponding to one of the first test targets a diffracted intensity difference and a second diffractive intensity difference corresponding to the second superposed structure of the first test target; and a difference between the first diffracted intensity difference and the second diffracted intensity The average value is obtained by a third diffraction intensity difference corresponding to the first test target to generate a coverage error. The method for measuring a coverage error of a semiconductor device according to claim 5, further comprising: performing a diffraction-based overlay error measurement on a second test target of the substrate to obtain a corresponding second test target a fourth diffraction intensity difference of the third stacked structure and a fifth diffraction intensity difference corresponding to the fourth stacked structure of the second test target; according to the fourth diffraction intensity difference An average value of the difference from the fifth diffraction intensity is obtained as a sixth diffraction intensity difference corresponding to the second test target; and based on the third diffraction intensity difference, the sixth diffraction intensity difference This overlay error is generated by offsetting from a predetermined position. The method for measuring a coverage error of a semiconductor device according to claim 5, further comprising: generating a first difference between the third diffraction intensity difference and the first diffraction intensity a difference; and determining a thickness variation of the substrate based on the first difference. The method for measuring a coverage error of a semiconductor device according to claim 6, further comprising: generating a first based on the first diffraction intensity difference, the fifth diffraction intensity difference, and the predetermined position offset a coverage error; and determining a thickness variation of the substrate based on the first coverage error and a standard deviation of the overlay error. A semiconductor device manufacturing method comprising: forming a first grating and a second grating disposed in a first direction of a first test area in a first direction in a first material layer; Forming, in the first material layer, a third grating and a fourth grating disposed side by side in the second rectangular region of one of the test regions in the first direction; in a second material layer of the substrate, Forming a fifth grating overlapping the first grating and having a first positional offset from the first grating in a second direction perpendicular to the first direction; and the second material Forming, in the layer, a sixth grating overlapping the third grating and having the first positional offset between the third grating and the third grating; wherein the first positional offset is The predetermined position offset is composed of a cover error. The method for manufacturing a semiconductor device according to claim 9, further comprising: Forming, in the second material layer, a seventh grating overlapping the second grating and having a second positional offset between the third grating and the second grating; and the second material Forming, in the layer, an eighth grating overlapping the fourth grating and having the second positional offset between the third grating and the fourth grating; wherein the second positional offset is determined by the predetermined The position offset is comprised of the overlay error; wherein the third direction is opposite the second direction.