TWI631565B - Methods for garbage collection in a flash memory and apparatuses using the same - Google Patents

Abstract

Embodiments of the present invention provide a method of collecting a flash memory, which is executed by a processing unit and includes the following steps. The valid data of n*m pages is read from a plurality of storage subunits, where n represents the number of storage subunits sharing one channel, and m represents the minimum number of write pages per storage subunit. A loop is repeatedly executed to drive the storage sub-units one by one to write valid data of m pages until the storage sub-units are in a busy state.

Description

Scrap memory waste collection method and device using the same

The present invention relates to a flash memory device, and more particularly to a method of collecting waste material for a flash memory and a device using the same.

Flash memory devices are generally classified into NOR flash devices and NAND flash devices. The NOR flash device is a random access device, and any address can be provided at the address pin to access the host of the NOR flash device and timely by the data foot of the NOR flash device. The data stored on the address is obtained on the bit. Conversely, NAND flash devices are not random access, but sequential access. The NAND flash device cannot access any random address like the NOR flash device. Instead, the master device needs to write the value of the byte of the sequence to the NAND flash device to define the request command (command). Type (eg, read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest data block of a write job in flash memory) or a block (the smallest data block of an erase job in flash memory). In fact, NAND flash devices typically read or write complete pages of data from memory cells. When a full page of data is read from the array into a buffer in the device, the main unit can be bitwise or word by sequentially clocking out the content using a strobe signal. A group of words access data.

If the data of some pages in the block is not needed (also known as the expired page), the pages in the block where the valid data is stored are read and rewritten to another previously erased empty block. These released blocks can then be used to write new data after the erase operation. The above process is called garbage collection (GC, Garbage Collection). The waste collection process involves reading and rewriting data to the flash memory, which means that the entire block needs to be read before a new write. However, waste collection takes a lot of time. Therefore, there is a need for a flash memory collection method and apparatus using the same to reduce access time.

Embodiments of the present invention provide a method of collecting a flash memory, which is executed by a processing unit and includes the following steps. Read valid data of n*m pages from multiple storage subunits. A loop is repeatedly executed to drive the storage sub-units one by one to write valid data of m pages until the storage sub-units are in a busy state.

The embodiment of the present invention further provides a method for collecting waste of a flash memory, which is executed by a processing unit, and includes the following steps. Schedule multiple read commands for valid data for n*m pages. In addition to receiving the valid data corresponding to the last read command and the physical address, the next data read command and the entity bit are transmitted before receiving the valid data corresponding to each transmitted data read command and the physical address. The address is assigned to the next one in the storage subunit. The storage subunit is driven to write valid data for n*m pages.

Embodiments of the present invention provide a waste collection device for a flash memory, comprising at least a channel and a processing unit. The channel is coupled to the plurality of storage sub-sheets And the processing unit is coupled to the channel. The processing unit reads the valid data of the n*m pages from the storage subunit; and repeatedly executes a loop for driving the storage subunits one by one to write the valid data of the m pages until the storage subunits are busy until.

Embodiments of the present invention further provide a waste collection device for a flash memory, comprising at least a channel and a processing unit. The channel is coupled to the plurality of storage subunits, and the processing unit is coupled to the channel. The processing unit schedules a plurality of read commands of the valid data of the n*m pages; in addition to receiving the valid data corresponding to the last read command and the physical address, the receiving is corresponding to each transmitted data. Before the valid data of the command and the physical address is taken, the next data read command and the physical address are transmitted to the designated next one in the storage subunit; and the storage subunit is driven to write the valid data of the n*m pages.

Where n represents the number of storage subunits sharing a channel, and m represents the minimum number of written pages per storage subunit.

10‧‧‧System

110‧‧‧Processing unit

130‧‧‧Dynamic random access memory

150‧‧‧Access interface

160‧‧‧Main device

170‧‧‧Access interface

170_0~170_j‧‧‧Access subinterface

180‧‧‧ storage unit

180_0_0~180_j_i‧‧‧Storage subunit

210‧‧‧Memory cell array

220‧‧‧ line decoding unit

230‧‧‧ column coding unit

240‧‧‧ address unit

250‧‧‧ data buffer

410_0‧‧‧Information line

420_0_0~420_0_i‧‧‧ Chip enable control signal

CE0~CE4‧‧‧ storage subunit

R0‧‧‧Time when receiving information from CE0

R1‧‧‧Time when receiving information from CE1

R2‧‧‧Time to receive information from CE2

R3‧‧‧Time to receive information from CE3

S511~S557‧‧‧ method steps

S711~S791‧‧‧ method steps

S911~S977‧‧‧ method steps

Time interval for reading data from T61‧‧

T63‧‧‧ Time interval for writing data

T81‧‧‧ Time interval for reading data

T83‧‧‧ Time interval for writing data

tR‧‧‧Storage time of subunit preparation materials

tProg‧‧‧Storage time when the subunit is actually written

W0‧‧‧Time to transmit information to CE0

W1‧‧‧Time to transmit information to CE1

W2‧‧‧Time to transmit information to CE2

W3‧‧‧Time to transmit information to CE3

1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention.

2 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention.

Figure 3 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention.

Figure 4 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention.

Figure 5 is a flow chart of a waste collection method of a flash memory implemented in a processing unit in accordance with an embodiment of the present invention.

Figure 6 is a schematic diagram of waste collection processing in accordance with an embodiment of the present invention.

Figure 7 is a flow chart of a waste collection method of a flash memory implemented in a processing unit in accordance with an embodiment of the present invention.

Figure 8 is a schematic view of waste collection processing in accordance with an embodiment of the present invention.

9A and 9B are flowcharts of a method of collecting waste materials of a flash memory executed in a processing unit according to an embodiment of the present invention.

The following description is a preferred embodiment of the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual inventive content must be referenced to the scope of the following claims.

It must be understood that the terms "comprising", "comprising" and "the" are used in the <RTI ID=0.0> </RTI> <RTIgt; </ RTI> to indicate the existence of specific technical features, numerical values, method steps, work processes, components and/or components, but do not exclude Add more technical features, values, method steps, job processing, components, components, or any combination of the above.

The words "first", "second", and "third" are used in the claims to modify the elements in the claims, and are not used to indicate a priority order, an advance relationship, or a component. Prior to another component, or the chronological order in which the method steps are performed, it is only used to distinguish components with the same name.

1 is a schematic diagram of a system architecture of a flash memory according to an embodiment of the present invention. The processing unit 110 is included in the system architecture 10 of the flash memory. The data is used to write the specified address to the storage unit 180, and the data is read from the specified address in the storage unit 180. In detail, the processing unit 110 writes the data to the specified address in the storage unit 180 through the access interface 170, and reads the data from the specified address in the storage unit 180. The system architecture 10 uses a plurality of electronic signals to coordinate data and command transfer between the processing unit 110 and the storage unit 180, including a data line, a clock signal, and a control signal. The data line can be used to transfer commands, addresses, read and write data; the control signal line can be used to transmit chip enable (CE), address latch enable (ALE), command extraction Control signals such as command latch enable (CLE) and write enable (WE). The access interface 170 can communicate with the storage unit 180 using a double data rate (DDR) protocol, such as an open NAND flash interface (ONFI), a double data rate switch (DDR toggle), or Other interface. The processing unit 110 can also use the access interface 150 to communicate with the main device 160 through a specified communication protocol, for example, a universal serial bus (USB), an advanced technology attachment (ATA), and an advanced technology. (serial advanced technology attachment, SATA), peripheral component interconnect express (PCI-E) or other interface.

2 is a schematic diagram of a storage unit in a flash memory according to an embodiment of the present invention. The storage unit 180 may include an array 210 composed of MxN memory cells, and each memory unit stores information of at least one bit. The flash memory can be a NAND type flash memory, or other kinds of flash memory. In order to correctly access the information, the row decoding unit 220 is configured to select a row specified in the memory cell array 210, and the column encoding unit 230 is configured to select a data of a certain number of bytes in the specified row as an output. Address unit 240 provides row information to row decoder 220 in which those rows in select memory cell array 210 are defined. Similarly, column decoder 230 selects a certain number of columns in a specified row of memory cell array 210 for read or write operations based on the column information provided by address unit 240. A row can be called a wordline, and a column can be called a bitline. A data buffer 250 can store data read from the memory cell array 210 or data to be written into the memory cell array 210. The memory unit can be single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs).

The storage unit 180 can include a plurality of storage subunits, each of which is implemented on a die, each communicating with the processing unit 110 using an associated access sub-interface. Figure 3 is a block diagram of an access interface and a storage unit in accordance with an embodiment of the present invention. The flash memory 10 may include j + 1 access sub-interfaces 170_0 to 170_j, the access sub-interfaces may also be referred to as channels, and each access sub-interface is connected to i + 1 storage sub-units. In other words, i + 1 storage subunits share an access subinterface. For example, when the flash memory 10 contains 4 channels ( j = 3 ) and each channel is connected to 4 storage units ( i = 3 ), the flash memory 10 has a total of 16 storage units 180_0_0 to 180_j_i. The processing unit 110 can drive one of the access sub-interfaces 170_0 to 170_j to read data from the designated storage sub-unit. Each storage subunit has a separate chip enable (CE, Chip Enable) control signal. In other words, when data reading or writing is to be performed on a specified storage subunit, it is necessary to drive the associated access sub-interface to enable the wafer enable control signal of the storage subunit. Figure 4 is a schematic diagram showing the connection of an access sub-interface and a plurality of storage sub-units according to an embodiment of the present invention. The processing unit 110 can select one of the connected storage sub-units 180_0_0 to 180_0_i through the access sub-interface 170_0 using the independent chip enable control signals 420_0_0 to 420_0_i, and then transmit the command or data through the shared data line 410_0. The selected storage subunit is given, or the data at the specified location is received from the selected storage subunit.

The main device 160 can provide a logical block address (LBA) to the processing unit 110 through the access interface 150 for instructing to write or read data of a specific area. The access interface 170 optimizes the efficiency of data writing, and a piece of data having consecutive logical block addresses can be distributedly placed in different areas in different storage subunits. Therefore, a look-up table (also known as an H2F table) is needed to indicate in which storage sub-unit the data of each logical block address is actually stored. In one embodiment, a sufficiently large space can be configured in the DRAM 130 to store the lookup table.

Assuming that n storage subunits share one channel, the minimum write unit of one storage subunit is m pages. In order to make the data of the waste collection processing more efficient, the embodiment of the present invention reads the valid data of n*m pages from several blocks, and then drives the storage sub-units to write the valid data of the m pages one by one. Until all storage subunits are in a busy state. It should be noted that after the valid data of the m pages is transferred to a storage subunit, the valid data of the other m pages can be transmitted to the next storage device without waiting for the storage subunit to perform the physical writing operation. unit. Through the above design, the processing unit 110 can transfer the data to the next storage sub-unit during the execution of the entity write operation by one storage sub-unit, and execute other entities during the execution of the entity write operation by all the storage sub-units. Operational work. Figure 5 is a flow chart of a waste collection method of a flash memory implemented in a processing unit in accordance with an embodiment of the present invention. The processing unit 110 reads the valid data of n*m pages via the access interface 170 and stores it in the dynamic random access memory 130 (step S511), and initializes the variable k(k=k ₀ ) (step S513). Among them, in addition to the valid data, the read block also contains expired data. k ₀ is a constant between 0 and n-1 to indicate the number of the first storage subunit to which the data is written. It should be noted here that the DRAM 130 has enough space to store valid data for n*m pages. In step S511, the processing unit may obtain the physical addresses of the valid data of the n*m pages according to the H2F table in the dynamic random access memory 130 and drive the storage unit 180 to read the materials from the physical addresses. Next, the processing unit 110 repeatedly executes a loop (steps S531 to S557) until the valid data of n*m pages are written to the storage unit 180.

In each round, the processing unit 110 reads the valid data of the m pages from the dynamic random access memory 130, and transmits the data write command and the physical address to the kth storage subunit via the access interface 170 (step S531). Refer to Figure 4. For example, in step S531, the processing unit 110 can enable the designated one of the independent wafer enable control signals 420_0_0 to 420_0_i through the access sub-interface 170_0 to select the kth from the storage sub-units 180_0_0 to 180_0_i. The storage subunits, then transmit the data write command and the physical address to the selected kth storage subunit through the shared data line 410_0. It should be noted here that the physical address indicates m pages of the same block. Next, the processing unit 110 transmits the valid data of the m pages to the kth storage subunit (step S533), and transmits a start write signal to the kth storage subunit to indicate the start of execution. The body write job (step S535). Refer to Figure 4. For example, in step S533, the processing unit 110 may transmit the valid data of the m pages to the selected kth storage subunit through the shared data line 410_0. For example, in step S535, the processing unit 110 can toggle the write enable (WE, Write Enable) signal corresponding to the kth storage subunit to instruct to start executing the physical write job. When the kth storage subunit receives the instruction from the processing unit 110, it enters a busy state and performs a physical write job for writing valid data of m pages to the specified physical address. Next, when the entire write job has not been completed (NO in step S551), the processing unit 110 increments the variable k (step S553), and determines whether the variable k is greater than or equal to n (step S555). If so, the processing unit 110 sets the variable k to 0 (step S557), and then drives the 0th storage subunit to write the valid data of the m pages (steps S531 to S553). Otherwise, the processing unit 110 then drives the kth storage subunit to write valid data of m pages (steps S531 to S553). When the entire write job is completed (the path of "YES" in step S551), the processing unit 110 ends the garbage collection processing of n*m pages.

Figure 6 is a schematic diagram of waste collection processing in accordance with an embodiment of the present invention. Assume that 4 storage subunits share one channel, and a storage subunit has a minimum write unit of 2 pages, and each page can contain 4K, 8K or 16K or other lengths of byte data. Refer to Figures 4 and 5. In step S511, the processing unit 110 can read 8 (4x2) pages of valid data from the four storage subunits (represented as CE0 to CE3) through the access interface 170 in the time interval T61, and store the data in the dynamic random access memory. Body 130. In detail, the processing unit 110 waits for a period of time tR (for example, 30, 40 or 70 microseconds (μs)) after transmitting the data read command and the physical address to the designated storage subunit through the shared data line 410_0. Let The storage subunit prepares the data on the physical address. Next, the processing unit 110 receives the data of the specified page through the shared data line 410_0 for a period of time Rx (for example, 45 or 50 microseconds (μs)), and x may be any one of 0 to 3. In order to shorten the data writing time T63 in the garbage collection processing, in steps S531 to S535, the processing unit 110 may transmit a data writing command through the access interface 170 for a period of time Wx (for example, 90 or 100 microseconds (μs)), After the physical address and the start of the write signal to the designated storage subunit, the storage subunit does not need to wait for the physical write operation to be performed, and then the data write command, the physical address, and the start of the write signal are transmitted through the access interface 170. For the next storage subunit, x can be any of 0 to 3. The storage subunit performs an entity write job at a time interval tProg (eg, 1200, 1250, or 1300 microseconds (μs)), and may notify the processing unit 110 at the end whether the entity write job was successful. When the entity write job is successful, the processing unit 110 may update the H2F table in the dynamic random access memory 130 to reflect the result of the entity write job.

In order to make the data collection processing of the waste collection processing more efficient, the embodiment of the present invention first schedules multiple read commands and physical addresses of valid data of n*m pages, and in addition to receiving corresponding to the last read. In addition to the valid data of the command and the physical address, before receiving the valid data corresponding to a transmitted data read command and the physical address, the next data read command and the physical address are transmitted to the next designated storage. unit. Through the above design, the time for reading valid data from the storage subunit can be closely arranged, and the idle time between the two pages is shortened as shown in FIG. Figure 7 is a flow chart of a waste collection method of a flash memory implemented in a processing unit in accordance with an embodiment of the present invention. First, the processing unit 110 schedules a command to read the valid data of n*m pages, and initializes the variable 1 (1=0), wherein the variable 1 is used to indicate the read command. Number (step S711). In step S711, the processing unit may obtain the physical address of the valid data of the n*m pages according to the H2F table in the dynamic random access memory 130, and read the command according to the scheduled data. Next, the processing unit 110 transmits the first (that is, the 0th) data read command and the physical address to the corresponding storage subunit via the access interface 170 (step S713). Next, the processing unit 110 repeatedly executes a loop (steps S731 to S751) until the data read command of the valid material of the n*m pages is transmitted to the storage unit 180.

In each round, the processing unit 110 transmits the 1+1th data read command and the physical address to the corresponding storage subunit via the access interface 170 (step S731), and receives the corresponding corresponding from the corresponding storage subunit. One data read command and valid data of the physical address (step S733), the read valid data is stored in the dynamic random access memory 130 (step S735), and the variable 1 is incremented by one (step S737). Next, the processing unit 110 determines whether the variable 1 is greater than or equal to n*m (step S751). If not, the processing unit 110 continues to transmit the 1+1th data read command and the physical address to the corresponding storage subunit via the access interface 170 for performing the valid data reading for the next round (step S731). If yes, the processing unit receives the valid data corresponding to the first data read command and the physical address from the corresponding storage subunit (step S771), and stores the read valid data to the dynamic random access memory 130 (step S773). ).

After the processing unit 110 reads the valid data of the n*m pages and stores the data in the dynamic random access memory 130, the valid data of the n*m pages is written into the storage unit 180 via the access interface 170 (step S791).

Figure 8 is a schematic view of waste collection processing in accordance with an embodiment of the present invention. Suppose four storage subunits share one channel, the most one of the storage subunits. The small write unit is 2 pages, and each page can contain 4K, 8K or 16K or other lengths of byte data. Refer to Figures 4 and 7. The time interval T81 is the time at which the valid material of n*m pages is read. In step S713, the processing unit 110 sends the data read command and the physical address to the designated storage subunit through the shared data line 410_0. Then, the loops of steps S731 to S751 are repeatedly executed, so that the processing unit 110 transmits the next data read command and the physical address to the designated storage subunit through the shared data line 410_0, and then receives the corresponding data read. Valid data for commands and physical addresses. For example, the processing unit 110 transmits the data read command and the physical address to the storage subunit CE1 through the shared data line 410_0, receives the valid data from the storage subunit CE0, and transmits the data read command and the physical address to the storage subunit CE3. Receive valid data from storage subunit CE1, and so on. After the loop is executed, the processing unit 110 receives the last valid data from the storage subunit CE0 through the shared data line 410_0. Comparing Figure 6, using the method shown in Figure 7, the idle time between reading two pages can be shortened.

9A and 9B are flowcharts of a method of collecting waste materials of a flash memory executed in a processing unit according to an embodiment of the present invention. This method combines the data reading efficiency shown in Fig. 7 with the data writing efficiency shown in Fig. 5. For detailed implementation details of steps S911 to S943, reference may be made to the description of steps S711 to S773 in FIG. For detailed implementation details of steps S951 to S971, reference may be made to the description of steps S513 to S557 in FIG.

Although the above-described elements are included in FIGS. 1 to 4, it is not excluded that more other additional elements are used without departing from the spirit of the invention, and a better technical effect has been achieved. In addition, although the flowcharts of Figures 5, 7, 9A and 9B are taken Executed in the specified order, but without departing from the spirit of the invention, those skilled in the art can modify the order among the steps to achieve the same effect, and therefore, the present invention is not limited to only using the above. order of. In addition, those skilled in the art may also integrate several steps into one step, or in addition to these steps, performing more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention has been described using the above embodiments, it should be noted that these descriptions are not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements that are apparent to those skilled in the art. Therefore, the scope of the claims should be interpreted in the broadest form to include all obvious modifications and similar arrangements.

Claims (18)

A method for collecting waste material of a flash memory, which is executed by a processing unit, comprising: reading valid data of n*m pages, wherein n represents the number of multiple storage subunits sharing a channel, and m represents each of the above The number of minimum written pages of the storage subunit; and repeatedly executing a loop for writing the valid data of the m pages one by one to one of the storage subunits until the n storage subunits are busy And the step of reading the valid data of the n*m pages in the above, further comprising: scheduling a plurality of read commands of the valid data of the n*m pages; and receiving the corresponding one And reading the valid data of the command and the physical address, and transmitting the next data read command and the physical address to the storage subunit before receiving the valid data corresponding to each transmitted data read command and the physical address Specify the next one. The method for collecting waste materials of a flash memory according to the first aspect of the invention, wherein, in the loop, when the valid data of the m pages is transmitted to one of the storage subunits, there is no need to wait for the above The storage subunit executes a physical write job to transfer the valid data of the other m pages to the lower one of the storage subunits. The method for collecting waste materials of a flash memory according to claim 1, wherein in the step of reading valid data of n*m pages, the method further comprises: And storing the valid data of the n*m pages in a dynamic random access memory; and wherein, in each of the loops, reading the valid data of the m pages from the dynamic random access memory, And driving the designated one of the storage subunits to write the valid data of the m pages. The method for collecting a flash memory according to the first aspect of the invention, wherein the step of repeatedly performing a loop further comprises: transmitting a data write command and a physical address in each round Assigning one of the storage subunits; transmitting valid information of m pages to the designated storage subunit; and transmitting a start write signal to the designated storage subunit. The method for collecting a flash memory according to claim 4, wherein the step of transmitting a data write command and a physical address to a designated one of the storage subunits further includes Enabling a designated one of the plurality of chip enable control signals to select the specified one from the storage subunit; and transmitting the data write command and the entity by using a data line shared by the storage subunit The address is given to one of the above-mentioned storage sub-units. The method for collecting a flash memory according to the fifth aspect of the invention, wherein the step of transmitting the valid data of the m pages to the designated storage subunit further comprises: transmitting the m through the data line The valid information of the pages is given to the storage subunit specified above. A method for collecting waste material of a flash memory, which is executed by a processing unit, comprising: scheduling a plurality of read commands of valid data of n*m pages, wherein n represents a plurality of storage subunits sharing a channel The quantity, m represents the number of minimum written pages of each of the above storage subunits; in addition to receiving valid data corresponding to the last read command and the physical address, the receiving corresponding to each transmitted data read command and Before the valid data of the physical address, the next data read command and the physical address are transmitted to the designated next one of the storage subunits; and after the valid data of the n*m pages are received from the storage subunit, Write valid data for the above n*m pages. The method for collecting waste materials of the flash memory according to claim 7, further comprising: storing the valid data of the n*m pages in a dynamic random access memory. The method for collecting a flash memory according to claim 7, wherein the data reading command and the physical address are transmitted through a data line shared by the storage subunit, and each of the pages is valid. The information is received through the above data line. A flash memory collection device includes: a channel coupled to a plurality of storage subunits; and a processing unit coupled to the channel for reading n*m pages from the storage subunit Data, where n represents the above sharing of the above channels The number of storage subunits, m represents the number of minimum written pages of each of the above storage subunits; and repeatedly executes a loop for writing the valid data of m pages one by one to one of the storage subunits, Until the n storage subunits are in a busy state and wherein the processing unit schedules the plurality of read commands of the valid data of the n*m pages; and receives the corresponding read command and the entity In addition to the valid data of the address, before receiving the valid data corresponding to each transmitted data read command and the physical address, the next data read command and the physical address are transmitted to the designated next in the storage subunit. By. The waste collection device of the flash memory according to claim 10, wherein, in the loop, when the valid data of the m pages is transmitted to one of the storage subunits, the processing unit does not It is necessary to wait for the storage subunit to perform a physical write job to transfer the valid data of the other m pages to the next one of the storage subunits. The flash memory collection device of claim 10, wherein the processing unit further stores the valid data of the n*m pages in a dynamic random access memory, and Each round of the circle, the processing unit reads the valid data of the m pages from the dynamic random access memory, and drives a specified one of the storage subunits to write the valid data of the m pages. The flash memory collection device of claim 10, wherein, in each round of the loop, the processing unit transmits a data write command and a physical address to the storage subunit. Designation One; transmitting valid data of m pages to the specified storage subunit; and transmitting a start write signal to the designated storage subunit. The flash memory collection device of claim 13, wherein the processing unit further enables a designated one of the plurality of wafer enable control signals in the channel for using the storage device And the unit selects one of the specified ones; and transmits the data writing command and the physical address to the designated one of the storage subunits through a data line in the channel shared by the storage subunit. The flash memory collection device of claim 14, wherein the processing unit transmits the valid data of the m pages to the designated storage subunit through the data line. A flash memory collection device includes: a channel coupled to a plurality of storage subunits; a processing unit coupled to the channel to perform a plurality of read commands of valid data of n*m pages Scheduling, where n represents the number of said storage subunits sharing a channel, and m represents the number of minimum written pages of each of said storage subunits; in addition to receiving valid data corresponding to the last read command and physical address And transmitting the next data read command and the physical address to the designated one of the storage subunits before receiving the valid data corresponding to each transmitted data read command and the physical address; and storing from the foregoing After receiving the valid data of the above n*m pages, the subunit writes the valid data of the above n*m pages. The waste storage device of the flash memory as described in claim 16 of the patent application scope The processing unit stores the valid data of the n*m pages in a dynamic random access memory. The flash memory collection device of claim 16, wherein the data read command and the physical address are transmitted through a data line shared by the storage subunit in the channel, and each of the foregoing The valid data of a page is received through the above data line.