TWI629547B - Liquid crystal display device and method of manufacturing same - Google Patents

Abstract

A liquid crystal display device for reducing damage of a signal line and a switching device caused by an electrostatic discharge shock and a method of manufacturing the same. The liquid crystal display device includes a plurality of pixels defined by intersections between a plurality of gate lines and a plurality of data lines; a plurality of virtual pixels disposed along the circumference of the pixels; a plurality of common lines, and the gates The pole lines are arranged in parallel, the common lines are connected to the pixels and the dummy pixels; the first gate metal receives an external common voltage; and the plurality of second gate metals extend from the common lines to one side, the The second gate metal has a pad shape; the source-drain metal is disposed in a direction parallel to the data lines and is located on one side of the second gate metal; the first connection pattern, the electricity The first gate metal and the source-drain metal are connected to each other; and the second connection pattern is electrically connected to the source-drain metal and the second gate metal.

Description

Liquid crystal display device and method of manufacturing same

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of reducing damage of a signal line and a switching device due to an electrostatic discharge shock and a method of manufacturing the same.

Generally, in order to prevent electrostatic discharge (ESD) from being introduced into a pixel, the liquid crystal display device includes an antistatic discharge circuit disposed in a non-display area where no image is displayed. The antistatic discharge circuit is disposed in the lead-in portion of the gate line to apply a scan signal to the pixel, and is disposed in the lead-in portion of the data line to apply a data voltage to the pixel. This antistatic discharge circuit conducts the electrostatic discharge introduced into the data line and the gate line to the common line, and the electrostatic discharge current introduced into the common line is directed to the gate line or the data line.

Meanwhile, in recent years, according to the trend toward high resolution and size increase, the liquid crystal display device is designed to have a gate electrode and a data line of a smaller width and a switching device of a smaller size. These behaviors mean that the gate line and the data line and the switching device become more susceptible to damage from electrostatic discharge shocks. Therefore, there is a need for a technique capable of more effectively protecting gate lines and data lines in a pixel and switching devices from electrostatic discharge.

Accordingly, the present invention is directed to a liquid crystal display device and a method of fabricating the same that substantially obviate one or more problems due to the limitations and disadvantages of the prior art.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method of fabricating the same in order to reduce damage of a signal line and a switching device due to an electrostatic discharge shock.

Other advantages, objects, and features of the invention will be set forth in part in the description in the description which I understand it in practice. Except In addition, the objects and other advantages of the invention will be realized and attained by the <RTIgt;

In order to achieve the above objects and other advantages, in accordance with the purpose of the present invention as embodied and broadly described herein, a liquid crystal display device includes: a plurality of pixels defined by intersections between a plurality of gate lines and a plurality of data lines; a plurality of virtual pixels disposed along the circumference of the pixels; a plurality of common lines disposed in parallel with the gate lines, the common lines being connected to the pixels and the dummy pixels; a first gate metal And for receiving an external common voltage; a plurality of second gate metals extending from the common lines to one side, the second gate metals having a pad shape; and a source-drain metal disposed at a direction parallel to the data lines and located on one side of the second gate metal; a first connection pattern for electrically connecting the first gate metal and the source-drain metal; a second connection pattern is used to electrically connect the source-drain metal and the second gate metal.

The liquid crystal display device may further include: a plurality of third gate metals extending from the common lines to the other side, the third gate metals having a pad shape; and a third connection pattern for electrically The first gate metal and the third gate metal are connected.

The first to third gate metals and the common lines may be formed of the same material in the same layer as the gate lines.

The source-drain metal can be formed of the same material in the same layer as the data lines.

The first to third connection patterns may be formed of the same material in the same layer as the pixel electrodes disposed in the pixels.

The liquid crystal display device may further include: a virtual data line formed parallel to the data lines so as to be adjacent to the first and last data lines; and a virtual common line in a direction parallel to the gate lines Branching from the first gate metal, the virtual common line traversing the data lines and the virtual data line; a first anti-static discharge circuit between the data lines and the virtual common line The first antistatic discharge circuit is connected to the data lines and the virtual common line; a second antistatic discharge circuit is interposed between the virtual common line and the first gate metal, and the second antistatic discharge circuit Connecting to the virtual common line and the first gate metal; and a third antistatic discharge circuit between the virtual data line and the virtual common line, the third antistatic discharge circuit is connected to the virtual data line And the virtual common line, The virtual data line is disposed between the second antistatic discharge circuit and the third antistatic discharge circuit.

The liquid crystal display device may further include: a fourth antistatic discharge circuit between the gate lines and the source-drain metal, the fourth antistatic discharge circuit being connected to the gate lines and the Source - bungee metal.

In another aspect of the invention, a method of fabricating a liquid crystal display device includes: forming a plurality of gate lines and a plurality of data lines intersecting each other on a substrate to define a plurality of pixel regions; forming a plurality of pixel regions in the pixel regions a pixel, each of which includes a thin film transistor and a pixel electrode; a plurality of dummy pixels are formed along the periphery of the pixels; a plurality of pixels are formed in parallel with the gate lines and connected to the pixels and the dummy pixels a common line, and a plurality of second gate metals extending from one side of the common line and having a pad shape; forming a first gate metal electrically connected to a pad unit for receiving An external common voltage; forming a source-drain metal, the source-drain metal being disposed in a direction parallel to the data lines and located on one side of the second gate metal; and forming a a first connection pattern electrically connecting the first gate metal and the source-drain metal and a second connection pattern for electrically connecting the source-drain metal and the second gate metal .

The method may further include: forming a plurality of third gate metals extending from the common lines to the other side and having a pad shape; and forming a first connection for electrically connecting the first gate metal and the first The third connection pattern of the three gate metal.

The first to third gate metals and the common lines may be formed of the same material in the same layer as the gate lines.

The source-drain metal can be formed of the same material in the same layer as the data lines.

The first to third connection patterns may be formed of the same material as the pixel electrode in the same layer.

The method may further include: forming a virtual data line parallel to the data lines such that the virtual data lines are adjacent to the first and last data lines; forming a virtual common line such that the virtual common line is The first gate metal is branched from the first gate metal in a direction parallel to the gate line, and the virtual common line traverses the data lines and the dummy data line; forming a first antistatic discharge circuit, so that the first defense The electrostatic discharge circuit is between the data lines and Between the virtual common lines, and connected to the data lines and the virtual common line; forming a second anti-static discharge circuit, such that the second anti-static discharge circuit is interposed between the virtual common line and the first gate metal And connecting to the virtual common line and the first gate metal; and forming a third anti-static discharge circuit, such that the third anti-static discharge circuit is between the virtual data line and the virtual common line, And connecting to the virtual data line and the virtual common line, wherein the virtual data line is disposed between the second antistatic discharge circuit and the third antistatic discharge circuit.

The method may further include: forming a fourth antistatic discharge circuit such that the fourth antistatic discharge circuit is disposed between the gate lines and the source-drain metal, and is connected to the gate lines and The source - bungee metal.

The first to fourth anti-electrostatic discharge circuits may be formed simultaneously with the thin film transistor disposed in the pixel region.

The foregoing description of the preferred embodiments of the invention,

2‧‧‧LCD panel

4‧‧‧ gate driver

6‧‧‧Data Drive

8‧‧‧Common voltage supply device

10‧‧‧First Gate Metal

12‧‧‧Second gate metal

14‧‧‧ Third Gate Metal

16‧‧‧Source-bungee metal

18‧‧‧First connection pattern

20‧‧‧Second connection pattern

22‧‧‧ Third connection pattern

24a‧‧‧First anti-static discharge circuit

24b‧‧‧Second anti-static discharge circuit

24c‧‧‧ Third anti-static discharge circuit

24d‧‧‧fourth anti-static discharge circuit

26‧‧‧gate electrode

28‧‧‧Semiconductor layer

30‧‧‧Source electrode

32‧‧‧汲electrode

34‧‧‧Ohm contact layer

36‧‧‧pixel electrode

50‧‧‧Substrate

60‧‧‧gate insulating film

70‧‧‧Protective film

AA‧‧‧ display area

Clc‧‧ liquid crystal capacitor

CL‧‧‧Common line

Cst‧‧‧ storage capacitor

DA‧‧‧Virtual Zone

DCL‧‧‧Virtual Common Line

DDL‧‧‧virtual data line

DL‧‧‧ data line

DP1‧‧‧ virtual pixels

DP2‧‧‧ virtual pixels

GL‧‧‧ gate line

H1‧‧‧first contact hole

H2‧‧‧second contact hole

H3‧‧‧ third contact hole

H4‧‧‧4th contact hole

H5‧‧‧ fifth contact hole

H6‧‧‧ sixth contact hole

P‧‧ ‧ pixels

TFT‧‧‧thin film transistor

Vcom‧‧‧Common voltage

The accompanying drawings are included to provide a further understanding of the embodiments of the invention. In the drawings: Fig. 1 is a configuration diagram illustrating a liquid crystal display device according to an embodiment of the present invention; and Fig. 2 is an enlarged view illustrating a region A of the liquid crystal panel 2 shown in Fig. 1; The figure is an enlarged view illustrating a region B of the liquid crystal panel shown in Fig. 1; Fig. 4 is a comparative example illustrating the effect of the present invention; and Fig. 5 illustrates that the electrostatic discharge shock is concentrated in a specific common line to cause a data line An example of damage; and FIG. 6 is a schematic cross-sectional view illustrating a thin film transistor TFT included in a pixel region and a cross-sectional view along the XY line of the TFT shown in FIG. 2.

Reference will now be made in detail to the preferred embodiments of the invention Wherever possible, the same reference numbers will be used in the drawings

Hereinafter, a liquid crystal display device and a method of fabricating the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a configuration diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

The liquid crystal display device shown in FIG. 1 includes a liquid crystal panel 2, a gate driver 4, a data driver 6, and a common voltage supply device 8.

The liquid crystal panel 2 defines a display area AA and a virtual area DA in which an image is displayed, the virtual area DA being an outer area of the display area AA.

A plurality of pixels P arranged in a matrix form are disposed in the display area AA. The pixels P are disposed in a plurality of pixel regions. The pixel regions are defined by intersections between a plurality of gate lines GL and a plurality of data lines DL. Each of the pixels P includes a thin film transistor TFT, a liquid crystal capacitor Clc, and a storage capacitor Cst. The liquid crystal capacitor Clc drives the liquid crystal in accordance with an electric field which is generated by a voltage difference between a material voltage applied to the pixel electrode through the thin film transistor TFT and a common voltage Vcom applied to the common electrode through the common line CL. The storage capacitor Cst maintains the data voltage applied to the pixel electrode for a predetermined time.

A plurality of dummy pixels DP1 and DP2 that do not display an image are disposed in the virtual area DA. The dummy pixels DP1 and DP2 are disposed along the circumference of the pixels P disposed in the display area AA. At the same time, first to third gate metals 10, 12 and 14, source-drain metal 16 and a plurality of anti-static discharge circuits are provided in the dummy area DA, the first to third gate metals 10, 12 And applying a common voltage Vcom from the common voltage supply device 8 to a plurality of common lines CL, the antistatic discharge circuits protecting the signal lines and the thin film transistor TFTs disposed in the pixels P from external static electricity The impact of the discharge (see Figures 2 and 3).

The gate driver 4 successively supplies a scan signal to the gate line GL. The scan signal is a pulse signal having a value that turns on the turn-on gate voltage of the thin film transistor TFT included in the pixel region and turns off the turn-off gate voltage of the thin film transistor TFT.

The data driver 6 converts the image data supplied from the outside into a material voltage using a standard gamma voltage, and applies the converted data voltage to the data line DL.

The common voltage supply device 8 applies the common voltage Vcom through the first to third gate metals 10, 12 and 14 and the source-drain metal 16 disposed in the dummy region DA to the common line CL (see FIG. 2 and Figure 3).

In particular, in the present embodiment, the resistance deviation between the paths through which the common voltage Vcom is applied to the common line CL is reduced, and thus it is possible to prevent line breakage or thin film transistor TFT which may be caused by concentrated supply of high-voltage electrostatic discharge. Damage.

Hereinafter, the path through which the common voltage Vcom is applied to the plurality of common lines CL will be described in detail.

Fig. 2 is an enlarged view illustrating a region A of the liquid crystal panel 2 shown in Fig. 1. 3 is an enlarged view illustrating a region B of the liquid crystal panel shown in FIG. 1; referring to FIGS. 2 and 3, a plurality of gate lines GL are arranged in a first direction (for example, a horizontal plane), and a plurality of The data lines DL are arranged in a second direction (for example, a longitudinal direction) perpendicular to the first direction. In addition, the plurality of common lines CL are arranged in the first direction such that the common line CL is parallel to the gate line GL.

The plurality of dummy pixels (DP) includes a plurality of first dummy pixels DP1 arranged in the first direction and a plurality of second dummy pixels DP2 arranged in the second direction.

The first dummy pixels DP1 are disposed at upper and lower portions of the display area AA such that they are adjacent to the pixels P arranged in the first row and the last row. The second dummy pixels DP2 are disposed on the left side portion and the right side portion of the display area AA such that they are adjacent to the pixels P arranged in the first column and the last column. Although the examples in which the second dummy pixels DP2 are arranged in three columns are exemplified in FIGS. 2 and 3, the second dummy pixels DP2 may be arranged in a plurality of columns. For reference, the first dummy pixel DP1 is connected to the common line CL instead of being connected to the gate line GL.

Meanwhile, as described above, the first to third gate metals 10, 12, and 14 and the source-drain metal 16 are disposed in the dummy area DA, which will be described below.

The first gate metal 10 is formed around the dummy area DA and electrically connected to the pad unit (not shown), and the pad unit is electrically connected to the common voltage supply device 8. The second gate metal 12 extends from the common line CL to one side (for example, the left side) to form a mat shape. The third gate metal 14 extends from the common line CL to the other side (eg, the right side) to form In the shape of a mat. The first to third gate metals 10, 12, and 14 and the common line CL may be composed of the same material as the gate line GL in the same layer.

Referring to FIG. 2, the source-drain metal 16 is disposed in the second direction and is located on one side of the second gate metal 12. The source-drain metal 16 can be disposed, for example, between a gate pad unit (not shown) and the second gate metal 12. In this case, in order to prevent short-circuiting between the source-drain metal 16 and the gate line GL, the source-drain metal 16 may be formed of the same material as the data line DL in the same layer.

At the same time, the first gate metal 10 is electrically connected to the source-drain metal 16, the source-drain metal 16 is electrically connected to the second gate metal 12, and the first gate metal 10 is electrically connected to the third gate metal. 14. Therefore, the common voltage Vcom applied from the common voltage supply device 8 to the first gate metal 10 is applied to the common line CL, and thus can be applied to the first and second dummy pixels DP1 and DP2 and the pixel P.

Specifically, the first gate metal 10 and the source-drain metal 16 are electrically connected to each other, thereby exposing the first and second contact holes of the first gate metal 10 and the source-drain metal 16 respectively. H1 and H2 are covered by the first connection pattern 18. Here, the first contact hole H1 passes through the protective film and the gate insulating film, and a portion of the first gate metal 10 is exposed, and the second contact hole H2 passes through the protective film, and the source-drain metal 16 Part of it is exposed. The first connection pattern 18 may be formed of the same material as the pixel electrode in the same layer.

In addition, the source-drain metal 16 and the second gate metal 12 are electrically connected to each other, thereby exposing the third and fourth contact holes H3 of the source-drain metal 16 and the second gate metal 12, respectively. And H4 is covered by 20 by the second connection pattern. Here, the third contact hole H3 passes through the protective film, and a portion of the source-drain metal 16 is exposed, and the fourth contact hole H4 passes through the protective film and the gate insulating film, and the second gate metal 12 is provided. Part of it is exposed. The second connection pattern 20 may be formed of the same material as the pixel electrode of the pixel region in the same layer.

As shown in FIG. 3, the first gate metal 10 and the third gate metal 14 are electrically connected to each other, thereby exposing the fifth and sixth portions of the first gate metal 10 and the third gate metal 14, respectively. The contact holes H5 and H6 are covered by the third connection pattern 22. Here, the fifth contact hole H5 passes through the protective film and the gate insulating film, and exposes a portion of the first gate metal 10, and the sixth contact hole H6 passes through the protective film and the gate insulating film, and makes the third Gate metal 16 Part of it is exposed. The third connection pattern 22 may be formed of the same material as the pixel electrode of the pixel region in the same layer.

Thus, the path through which the common voltage Vcom is introduced into the common line CL will be summarized below. The common voltage Vcom is applied to each of the common lines CL in the order of the first gate metal 10, the first connection pattern 18, the source-drain metal 16, the second connection pattern 20, and the second gate metal 12. side. In addition, the common voltage Vcom is applied to the other side of each common line CL in the order of the first gate metal 10, the third connection pattern 22, and the third gate metal 14.

For this reason, in the present embodiment, the common voltage Vcom skips the first to third gate metals 10, 12 and 14 and the source-drain metal 16, thereby being applied to the common line CL. Therefore, the resistance deviation between the paths introduced to the common voltage Vcom in the common line CL can be reduced, and the problem that the electrostatic discharge is concentratedly introduced into the common line CL can be prevented.

For reference, the electrostatic discharge current is directed to a portion having a relatively low resistance. Since the first gate metal 10 has a large area, electrostatic discharge is easily introduced to the first gate metal 10. The electrostatic discharge introduced into the first gate metal 10 may be introduced into a common line CL electrically connected to the first gate metal 10. When the electrical connection paths between the first gate metal 10 and the common line CL are different, a resistance deviation may occur between the first gate metal 10 and the common line CL. As a result, the electrostatic discharge introduced into the first gate metal 10 concentrates toward the common line CL having a relatively low resistance. For this reason, when the electrostatic discharge shock is concentrated in the specific common line CL, the corresponding common line CL may be damaged, or the data line DL intersecting the common line CL may be damaged. Fig. 5 exemplifies an example in which the electrostatic discharge shock concentrates on the specific common line CL causing damage to the data line DL. According to the present invention, the electrical connection paths between the first gate metal 10 and the common line CL are the same, and it is possible to prevent the electrostatic discharge shock from being concentrated in the specific common line CL, and as a result, the destruction of the wiring or the damage of the thin film transistor TFT can be prevented.

Meanwhile, in the present embodiment, in order to reduce damage of the signal line and the thin film transistor due to electrostatic discharge, the liquid crystal display device includes a plurality of antistatic discharge circuits, which are described in detail below.

Referring to FIGS. 2 and 3, the virtual display area DA further includes a virtual data line DDL, a virtual common line DCL, and a plurality of anti-static discharge circuits.

The virtual data line DDL is disposed in the first direction such that it is adjacent to the first and last data lines DL. The virtual data line DDL branches into three virtual data line DDL branches, such that the virtual data lines correspond to the second virtual pixels DP2 arranged in three columns, thereby being connected to the second virtual pixels DP2.

The virtual common line DCL branches out from the first gate metal 10 in the second direction and traverses the virtual data line DDL and the data line DL. The number of such virtual common lines DCL may be at least one.

The antistatic discharge circuits include first to fourth anti-electrostatic discharge circuits 24a to 24d.

The first anti-static discharge circuit 24a protects the data line DL from damage by electrostatic discharge shock. For this purpose, the first anti-static discharge circuit 24a is disposed between the data line DL and the virtual common line DCL, and is connected to the data line DL and the virtual common line DCL.

The second anti-static discharge circuit 24b prevents the virtual common line DCL from being damaged by the electrostatic discharge shock. For this purpose, the second anti-static discharge circuit 24b is disposed between the dummy common line DCL and the first gate metal 10, and is connected to the dummy common line DCL and the first gate metal 10.

The third anti-electrostatic discharge circuit 24c prevents the virtual data line DDL from being damaged by the electrostatic discharge shock. For this purpose, the third anti-static discharge circuit 24c is disposed between the virtual data line DDL and the virtual common line DCL, and is connected to the virtual data line DDL and the virtual common line DCL.

The fourth anti-static discharge circuit 24d prevents the gate line GL from being damaged by the electrostatic discharge shock. For this purpose, a fourth anti-electrostatic discharge circuit 24d is disposed between the gate line GL and the source-drain metal 16, and is connected to the gate line GL and the source-drain metal 16.

In particular, the present embodiment is characterized in that the virtual data line DDL is disposed between the second and third anti-static discharge circuits 24b and 24c. As shown in FIG. 4, when the dummy data line DDL is disposed between the first gate metal 10 and the second anti-electrostatic discharge circuit 24b, due to electrostatic discharge introduced from the first gate metal 10 into the virtual common line DCL As a result, the virtual data line DDL may be easily damaged. According to the present invention, by arranging the dummy data line DDL between the second and third anti-static discharge circuits 24b and 24c, damage of the dummy data line DDL can be prevented.

Hereinafter, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described in detail.

According to the thin film transistor array substrate of the liquid crystal display panel 2 according to the present embodiment, the plurality of gate lines GL, the plurality of common lines CL, and the first to third gate metals 10, 12, and 14 are formed of the same material. In one layer, as described above. Further, the data line DL and the source-drain metal 16 are formed of the same material in the same layer, and the pixel electrode and the first to third connection patterns 18, 20, and 22 are formed of the same material in the same layer.

That is, the first to third gate metals 10, 12, and 14, the source-drain metal 16, and the first to third connection patterns 18, 20, and 22 according to the present embodiment are disposed in the pixel region. Thin film transistors are formed simultaneously, so different mask processes are not required to form these components. Hereinafter, for convenience of description, a process of manufacturing a thin film transistor TFT included in a pixel region will be provided. Fig. 6 is a schematic cross-sectional view illustrating a thin film transistor TFT included in a pixel region and a cross-sectional view taken along line X-Y of the TFT shown in Fig. 2. A method of manufacturing a liquid crystal display device will be described below with reference to Fig. 6.

First, a gate metal layer is formed on the substrate 50 by metal, and then the gate metal layer is patterned to form a plurality of gate patterns. The gate patterns include a plurality of gate lines GL and gate electrodes 26, and the gate electrodes 26 protrude from the gate lines GL corresponding to the pixel regions. The gate patterns further include first to third gate metals 10, 12, and 14, a common line CL, and a virtual common line DCL.

Next, a gate insulating film 60 is formed on the substrate 50 including the gate patterns using an inorganic insulating material such as tantalum nitride (SiNx) or germanium dioxide (SiO ₂ ).

Further, a semiconductor layer 28 containing pure amorphous germanium and an ohmic contact layer 34 containing impure amorphous germanium are stacked on the gate insulating film 60. At this time, the semiconductor layer 28 and the ohmic contact layer 34 are formed in an island shape in a region overlapping the gate electrode 26.

Next, a source-drain metal layer is formed on the substrate 50 including the semiconductor layer 28 and the ohmic contact layer 34 by using a metal selected from the group of conductive metals, and then the source-drain metal layer is patterned. To form a plurality of source-drain patterns. The source-drain patterns include a plurality of data lines DL, a source electrode 30 connected to a plurality of data lines DL corresponding to the pixel regions, and a drain electrode 32 separated from the source electrode 30. Open, making The gate electrode 26 is disposed between the drain electrode 32 and the source electrode 30. The source-drain pattern further includes a source-drain metal 16 and a dummy data line DDL.

Next, the ohmic contact layer 34 exposed between the source electrode 30 and the drain electrode 32 is removed to expose the semiconductor layer 28.

Next, an inorganic insulating material selected from the group consisting of tantalum nitride (SiNx) or cerium oxide (SiO ₂ ), or an organic insulating material selected from benzocyclobutene (BCB) and acrylic resin is used. A protective film 70 is formed on the substrate 50 including the source-drain pattern.

The protective film 70 and the gate insulating film 60 are selectively removed to form pixel contact holes and the aforementioned first to sixth contact holes H1 to H6, which expose the gate electrodes 32.

Next, a transparent conductive metal selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO) is disposed on the resultant structure, and the transparent conductive metal is patterned to form a plurality Transparent pattern. The transparent patterns include a pixel electrode 36 that covers the pixel contact hole and a common electrode (not shown) that forms an electric field with the pixel electrode 36. The transparent patterns further include the aforementioned first to third connection patterns 18, 20, and 22.

Meanwhile, the aforementioned first to fourth anti-electrostatic discharge circuits 24a to 24d include a plurality of thin film transistors. The thin film transistors are also formed simultaneously with the thin film transistor disposed in the pixel region.

For this reason, in the present embodiment, the first to third gate metals 10, 12 and 14, the source-drain metal 16 and the first to third connection patterns 18, 20 and 22 are disposed in the pixel region. The thin film transistors are formed simultaneously, so a separate mask process is not required to form these components.

Meanwhile, based on the configurations shown in FIGS. 2 and 3, the present embodiment can reduce product defects due to electrostatic discharge generated in the process of fabricating the thin film transistor array substrate, thereby improving the yield. In particular, in the process of fabricating a thin film transistor, deposition of an inorganic insulating material and pure amorphous germanium is performed by chemical vapor deposition (CVD), and various metal layers are patterned by dry etching. A large amount of electrostatic discharge can be generated during CVD or dry etching. As described above, the electrostatic discharge may be concentrated in a specific line in the common line CL. In particular, an etching process for selectively removing the deposited protective film 50 or a system for forming a transparent pattern During the process, since the process is performed after the gate patterns are formed, the electrostatic discharge shock is easily concentrated in the specific common line CL. According to the present invention, based on the configurations shown in Figs. 2 and 3, it is possible to reduce product defects due to electrostatic discharge generated in a production process such as CVD or dry etching.

As is apparent from the foregoing description, the present invention reduces the resistance deviation between the paths through which the common voltage is applied to the plurality of common lines, thereby preventing line damage that may be caused by the high voltage electrostatic discharge being concentratedly supplied to a specific common line or Damage to the thin film transistor. Moreover, the present invention changes the design of the virtual data lines, thereby reducing the electrostatic discharge shock of the virtual data lines, as well as preventing damage to the lines or damage to the thin film transistors.

The invention improves the reliability of the product in the product driving process, and reduces the product defects caused by the large amount of electrostatic discharge generated in the manufacturing process of the thin film transistor, thereby advantageously improving the yield of the product and reducing the production cost. .

It is apparent to those skilled in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention. Therefore, it is intended that the present invention cover the modifications and variations of the invention, which are within the scope of the appended claims and their equivalents.

The present application claims the benefit of the Korean Patent Application No. 10-2011-0130497, filed on Dec. 7, 2011, which is hereby expressly incorporated by reference in its entirety herein.

Claims (13)

A liquid crystal display device includes: a plurality of pixels defined by intersections between a plurality of gate lines and a plurality of data lines; a plurality of dummy pixels disposed along a circumference of the pixels; a plurality of common lines, and the The gate lines are arranged in parallel, the common lines are connected to the pixels and the dummy pixels; a first gate metal is used to receive an external common voltage; and a plurality of second gate metals are The wires extend to one side, the second gate metal has a pad shape; a source-drain metal is disposed in a direction parallel to the data lines and located in the second gate metal a first connection pattern for electrically connecting the first gate metal and the source-drain metal; a second connection pattern for electrically connecting the source-drain metal and the second a gate metal; a plurality of third gate metals extending from the common line to the other side, the third gate metal having a pad shape; and a third connection pattern for electrically connecting the first A gate metal and the third gate metal. The liquid crystal display device of claim 1, wherein the first to third gate metals and the common lines are formed of the same material in the same layer as the gate lines. The liquid crystal display device according to claim 1, wherein the source-drain metal is formed of the same material as the data lines in the same layer. The liquid crystal display device according to claim 1, wherein the first to third connection patterns are formed of the same material in the same layer as the pixel electrodes provided in the pixels. The liquid crystal display device according to claim 1, further comprising: a virtual data line formed parallel to the data lines so as to be adjacent to the first and last data lines; a virtual common line from the first gate in a direction parallel to the gate lines Branching out of the metal, the virtual common line traversing the data lines and the virtual data line; a first anti-static discharge circuit between the data lines and the virtual common line, the first anti-static discharge circuit is connected To the data lines and the virtual common line; a second anti-static discharge circuit between the virtual common line and the first gate metal, the second anti-static discharge circuit being connected to the virtual common line and the a first gate metal; and a third antistatic discharge circuit between the virtual data line and the virtual common line, the third antistatic discharge circuit is connected to the virtual data line and the virtual common line, wherein the The virtual data line is disposed between the second antistatic discharge circuit and the third antistatic discharge circuit. The liquid crystal display device of claim 5, further comprising: a fourth antistatic discharge circuit interposed between the gate lines and the source-drain metal, the fourth antistatic discharge circuit Connected to the gate lines and the source-drain metal. A method of manufacturing a liquid crystal display device, comprising: forming a plurality of gate lines and a plurality of data lines intersecting each other on a substrate to define a plurality of pixel regions; forming a plurality of pixels in each of the pixel regions, each pixel a thin film transistor and a pixel electrode are formed; a plurality of dummy pixels are formed along the periphery of the pixels; and a plurality of common lines are formed in parallel with the gate lines and connected to the pixels and the dummy pixels, and Forming a plurality of second gate metals extending from the common lines to one side and having a pad shape; forming a first gate metal electrically connected to a pad unit to receive an external common voltage ; Forming a source-drain metal, the source-drain metal being disposed in a direction parallel to the data lines and located on one side of the second gate metal; forming an electrical connection a first connection pattern of a gate metal and the source-drain metal and a second connection pattern for electrically connecting the source-drain metal and the second gate metal to form a plurality of And a third gate metal extending from the common line to the other side and having a pad shape; and forming a third connection pattern for electrically connecting the first gate metal and the third gate metal. A method of manufacturing a liquid crystal display device according to claim 7, wherein the first to third gate metals and the common lines are formed of the same material in the same layer as the gate lines. A method of manufacturing a liquid crystal display device according to claim 7, wherein the source-drain metal is formed of the same material as the data lines in the same layer. A method of manufacturing a liquid crystal display device according to claim 7, wherein the first to third connection patterns are formed of the same material as the pixel electrode in the same layer. The method for manufacturing a liquid crystal display device according to claim 7, further comprising: forming a virtual data line parallel to the data lines such that the virtual data line is adjacent to the first and last data lines; Forming a virtual common line such that the virtual common line branches out from the first gate metal in a direction parallel to the gate lines and traverses the data lines and the dummy data line; forming a first defense An electrostatic discharge circuit, wherein the first anti-static discharge circuit is interposed between the data lines and the virtual common line, and is connected to the data lines and the virtual common line; Forming a second antistatic discharge circuit such that the second antistatic discharge circuit is interposed between the dummy common line and the first gate metal, and is connected to the dummy common line and the first gate metal; and forming a third antistatic discharge circuit, the third antistatic discharge circuit is interposed between the virtual data line and the virtual common line, and is connected to the virtual data line and the virtual common line, wherein the virtual data line is disposed at The second antistatic discharge circuit is connected to the third antistatic discharge circuit. The method for manufacturing a liquid crystal display device according to claim 11, further comprising: forming a fourth antistatic discharge circuit, wherein the fourth antistatic discharge circuit is disposed at the gate line and the source-汲Between the pole metals, and connected to the gate lines and the source-drain metal. A method of manufacturing a liquid crystal display device according to claim 12, wherein the first to fourth antistatic discharge circuits are formed simultaneously with the thin film transistor provided in the pixel region.