TWI628989B - Method for forming wire and filling via of pcb - Google Patents

Abstract

The invention relates to a method for manufacturing a line and interlayer conduction of a printed circuit board. The modified electroplating graphene (rGO) is applied to the holes and the surface of the substrate, so that the plating metal is simultaneously deposited in the holes between the layers and the surface of the substrate. Then, the metal layer on the surface of the substrate is etched to form a wiring pattern. In addition, if the reduced graphene oxide (rGO) is modified in the holes and the trenches of the line, and the other places cover the plating resist, the plating metal can be simultaneously deposited in the holes and the trenches of the lines. The invention can be applied in high-density interconnect (HDI) circuit design, so that the circuit board does not need a hole pad structure to increase the process design capability of the fine line.

Description

Manufacturing method for wiring and interlayer conduction of printed circuit board

The invention relates to a method for manufacturing printed circuit board lines and interlayer conduction, in particular, only by reducing the conductive layer of the graphene oxide (rGO), the surface metal can be formed simultaneously on the printed circuit board by filling holes. Layer or directly make lines.

A Printed Circuit Board (PCB) is a structured electronic component on an insulating substrate with conductive traces. However, with the development of electronic products in light, thin and short, the changes in PCB must also follow. For example, when the integrated circuit process enters the micron (um) era, the line width and line pitch of the PCB are designed in millimeters (mm). Nowadays, the integrated circuit has entered the nano process, and the PCB has entered the micron era. Moreover, the mode of inter-board interconnection has also entered the high density interconnection (HDI) technology.

At present, the HDI technology is mostly conducted by laser drilling, and then the wet metallization process is used to make the circuit or the conductive process to interconnect them, and then the copper plating is performed. However, when performing interconnection work, the hole pad must be made at the bottom of the blind hole, and its diameter is about twice the diameter. When the future line becomes denser, the area of the hole pad outside the blind hole will become the bottleneck of the wiring.

The above metallization or electro-conductivity process includes a chemical copper process and a direct electroplating process; the latter includes a graphite process and a carbon black process.

However, after the metallization process is completed in the blind-via, the subsequent copper plating operations will have the following effects:

a. The metallized (conductive) layer has a higher impedance than the surface metal copper, and the thickness uniformity within the hole varies greatly. Therefore, when the copper plating operation is performed, the bottom conductive difference impedance is large, resulting in poor copper seeding. This will affect the subsequent deposition rate, causing the deposition of the pores and the copper at the bottom of the hole to form a void phenomenon, or a poor filling or missing filling. The conductive process with a larger impedance value has a higher proportion of occurrence of such undesirable phenomena. Therefore, the market uses chemical copper processes.

b. When the metallization is completed, the chemical copper layer in the hole is extremely thin and may even be less than 0.1 um, and is highly oxidizable. Therefore, if a dry film process or a copper plating hole is directly applied, the oxide film must be removed. This micro-etching operation should not be too strong, and it is feared that the extremely thin conductive layer will be bitten off, but it is too weak. The tenacious oxide film on the copper base of the substrate cannot be cleaned and the adhesion is poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a line and interlayer conduction of a printed circuit board, which is simple in manufacture and does not require a hole pad, so that the area of the line arrangement can be effectively increased.

The method of the present invention can be implemented in the following steps: A. Providing a printed circuit board having an insulating layer on the surface thereof having at least one hole having a diameter of 10 um to 300 um, a diameter to depth ratio of 0.2:1 to 2:1, and a wall surface being non- Conductivity; B. Modifying a layer of reduced graphene oxide (rGO) conductive layer on the surface of the substrate and the wall of the hole; C. performing an electroplating process to form a bond between the metal and the rGO conductive layer, and depositing in the hole while on the surface of the substrate Forming a metal layer; D. performing an etching process to form a metal layer to form a line pattern.

The metal in which the plating process is made is copper.

The periphery of the hole has no perforated pad pattern.

The bottom of the hole is non-conductive.

The surface of the printed circuit board is non-conductive.

The method of the present invention can also be implemented in the following steps: A. providing a printed circuit board having an insulating layer on the surface thereof having at least one hole having a diameter of 10 um to 300 um, a diameter to depth ratio of 0.2:1 to 2:1, and at least one Line trenches with a width of 5um-200um have a width-to-depth ratio of 0.5:1-10:1, and the walls of the holes and trenches are non-conductive; B. Overlay plating on the surface of the substrate other than the holes and trenches a resist; C. a layer of reduced graphene oxide (rGO) conductive layer is modified on the wall of the hole and the trench; D. an electroplating process is performed to form a bond between the metal and the rGO conductive layer, and simultaneously deposit in the hole and the trench Medium; E. remove the plating resist.

The metal in which the plating process is made is copper.

The holes and the bottom of the line trench are non-conductive.

The surface of the printed circuit board is non-conductive.

The plating resist of step B is an exposure development type electroplating ink.

The circuit and interlayer conduction structure of the printed circuit board manufactured by the method of the invention has the following features: the line and the interlayer conduction structure are integrally formed, and have an rGO conductive layer between the printed circuit board; wherein the diameter of the interlayer conduction structure is 10um-300um, diameter to depth ratio is 0.2:1-2:1; line width is 5um-200um um, width to depth ratio is 0.5:1-10:1.

The printed circuit board can be provided with a groove corresponding to the line, so that the rGO conductive layer is directly formed in the groove.

The invention adopts reduced graphene oxide (rGO) as a conductive layer for conducting PCB interconnection, and has the following characteristics:

a. The rGO layer is not afraid of acid or alkali, and it is not attacked to reduce its conductivity in any subsequent process operations.

b. When performing subsequent copper plating operations, a complete micro-etching operation can be implemented to provide a perfect sealing effect.

c. The conductivity of rGO itself is better than that of copper metal, and the conductivity value is close to that of silver metal. Therefore, there is no doubt that the "precipitation of copper seeding" is not uniform in the blind hole, and the copper plating state in the blind hole can be maintained. Good condition, improve the phenomenon of void or missing.

10, 11‧‧‧ resin layer

20‧‧‧Internal lines

30‧‧‧Electroplating Resist

40‧‧‧rGO layer

50‧‧‧ copper foil

51‧‧‧ Copper-plated blind holes

52, 53‧‧‧ lines

Figure 1 shows the results of plating with different apertures when there is no metal layer at the bottom of the blind hole.

Figure 2 is a comparison of Figure 1, but with a metal layer left at the bottom of the blind hole.

Figure 3 (a) and (b) are printed circuit boards of conventional apertured pads and the present invention A comparative diagram of a non-porous pad printed circuit board.

Figure 4 is an enlarged view of the dotted line of Figure 3 (b) for the detailed steps of the process.

Fig. 5 shows the steps of simultaneously plating the hole-filling and metallization layers of the present invention.

Figure 6 shows the steps of simultaneous electroplating and plating of the present invention.

The operating conditions of the following implementation steps can be adjusted and matched according to the environment. The above description is only the recommended range. The specific terms used in the present invention have their original meanings, and certain specific terms are used as follows to provide those skilled in the art to further understand the present invention. For convenience, some special terms will be indicated in italics or quotation marks, but these marked parts will not affect the scope or meaning of the special term itself, just like the unmarked text in this article. That is to say, the same thing will have more than one statement.

Example 1

A piece of printed circuit board is taken, and the surface of the substrate is sequentially an insulating resin layer, a copper layer, and a resin layer. The surface resin layer forms blind holes having pore diameters of 100 um, 125 um, and 150 um, respectively, but the copper layer located at the bottom of the blind hole and its periphery is etched away in advance, so that the bottom of the blind hole is in contact with the inner resin layer or other insulating layer.

Step 1 Modify rGO in the hole

(i) immersing the PCB substrate in an aqueous solution of a regulator (PVI metal salt Polyvinylimidazole, PVI) to form a high score on the surface of the substrate, the bottom surface of the blind hole, and the inner wall Sublayer. The concentration of the aqueous solution of the regulator is 4-10 g/L, controlled at pH 3-6, and the temperature is 40-80 °C. After 15-40 minutes, the water was taken out and dried.

(ii) immersing the PCB substrate in an aqueous solution of Graphene Oxide (GO) to adsorb and bond the graphene oxide to the PVI layer on the inner wall of the hole. The graphene oxide solution has a concentration of 0.1-1 g/L, is controlled at a pH of 3-6, and has a temperature of 35-80 °C. After 25-40 minutes, take out the water and blow dry.

(iii) The PCB substrate was applied to a plasma of H2 for 10 minutes for reduction, and graphene oxide (GO) on the inner wall of the pore was reduced to reduced graphene oxide (rGO).

Step 2 Clean the PCB substrate

(i) The PCB substrate was cleaned with an acidic detergent (SLLOTCLEAN S 20, 0.5-5% of SCHLOTTER) to remove residual impurities. After 3-10 minutes at 15-30 ° C, the water was taken out.

(ii) The PCB substrate was immersed in a microetching solution (SLOTOETCH 584, 10-40 g/L of SCHLOTTER) to further remove impurities. After 3-10 minutes at 15-30 ° C, the water was taken out.

Step 3 Plating Copper Filling

The PCB substrate is immersed in a plating solution to form an interlayer conduction structure, and the plating solution includes CuSO4 (180-350 g/L), H2SO4 (30-60 g/L), chloride ion (20-90 ppm), and carrier agent (SCHLOTTER SLOTOCOUP 31, 3-10 ml/L), gloss (SCHLOTTER SLOTOCOUP 32, 0.1-1 ml/L), leveling agent (SCHLOTTER SLOTOCOUP 33, 0.1-1 ml/L).

Figure 1 shows the results of blind via electroplating with different apertures, showing that the deposited copper metal structure is tight and can be deposited directly on the surface of the non-conductive resin.

The same printed circuit board without removing the copper layer at the bottom of the blind hole was taken, and the above steps were carried out under the same operating conditions. The results are shown in Fig. 2. In contrast, when the aperture is increased, the hole-filling effect of the copper-free layer at the bottom is significantly better. It is speculated that the main reason is that the roughness of the resin layer is larger than that of the copper layer, which provides the ability of the rGO conductive layer to deposit metal in three dimensions. However, the present invention is not particularly limited thereto, and merely provides another option.

Fig. 3(a) shows a common printed circuit board on which a hole, a Cu pad and a line are arranged, wherein the hole pad has a diameter of about twice that of the hole and occupies a considerable space.

The invention directly modifies the reduced graphene oxide (rGO) on the non-conductive material to be electroplated, and does not need to make a pad (Padless), which can make room for the line configuration and achieve the purpose of HDI design. As shown in FIG. 3(b), it is a schematic diagram of the arrangement of holes and lines on the printed circuit board of the present invention. To illustrate the application of the technique of the present invention, the dotted line in Figure 3(b) is enlarged to the fourth figure for the detailed steps of the process. In the figure, a copper-plated blind hole 51, a line 52 connected to the blind hole 51, and another line 53 are disposed on the non-conductive resin layer 11 on the surface of the printed circuit board.

Example 2

Fig. 5(a) shows a cross-sectional view of the resin layers 10, 11 and the internal wiring 20. Next, the laser is drilled at the blind hole location, and the copper metal at the bottom of the blind hole is also removed, as shown in Figure 5(b). Next, rGO is modified on the surface of the resin layer 11 and the wall surface and the bottom surface of the blind via to form an electrically conductive rGO layer 40 as shown in Fig. 5(c). Then carry on electricity In the plating process, metal copper 50 is deposited on the surface of the resin layer 11 and in the blind vias as shown in Fig. 5(d). Finally, an etching process is performed to obtain printed circuit board surface lines 52, 53, and blind vias 51 that open internal lines 20 and surface lines 53, as shown in Figure 5(e).

Example 3

Fig. 6(a) shows a cross-sectional view of the same resin layers 10, 11 and internal wiring 20. In Fig. 6(b), the laser is used to drill or engrave the groove at the position corresponding to the blind hole and the line, and the copper metal at the bottom of the blind hole is also removed, and the dotted line indicates the removed portion.

Prior to electroplating, the plating resist 30 is also laid first at a position where plating is not required, as shown in Fig. 6(c). Next, rGO is modified in the inner wall of the blind via and the trench of the line to form an electrically conductive rGO layer 40, as shown in Fig. 6(d). Then, an electroplating process is performed to deposit copper metal in the blind via 51 and the trenches 52, 53 while completing the filling and wiring fabrication, as shown in Fig. 6(e). Fig. 6(f) shows the removal of the plating resist 30 after the plating is completed.

Based on the experimental results of the above embodiments, the present invention is the first to disclose the manufacturing process of the circuit and the interlayer conduction of the printed circuit board. In the step of plating the metal hole in the printed circuit board, the plating metal can be simultaneously deposited in the interlayer via hole and The surface of the substrate can be removed from the hole pad to increase the layout of the circuit board. The invention can be applied to high-density interconnect (HDI) circuit design with excellent market potential.

Claims (11)

A manufacturing method for wiring and interlayer conduction of a printed circuit board comprises the following steps: A. providing a printed circuit board having an insulating layer on the surface thereof having at least one hole having a diameter of 10 um to 300 um, the aspect ratio of which is 0.2:1. 2:1, and the wall surface is non-conductive; B. Modifying a layer of reduced graphene oxide (rGO) conductive layer on the surface of the substrate and the wall of the hole, including the following steps: (i) immersing the substrate in a solution of Polyvinylimidazole (PVI), a polymer layer is formed on the surface of the substrate and the inner wall of the hole, the pH is 3-6, the temperature is 40-80 ° C, and the time is 15-40 minutes; (ii) the substrate is immersed in an aqueous solution of graphene oxide (GO), a PVI layer adsorbed and bonded to the inner wall of the hole; (iii) reducing GO with a plasma of H _{2 to} form a rGO conductive layer; C. performing an electroplating process to form a bond between the metal and the rGO conductive layer, and depositing in the hole A metal layer is simultaneously formed on the surface of the substrate; D. an etching process is performed to form a metal pattern to form a line pattern, and the periphery of the hole has no hole pad. The method of claim 1, wherein the metal of the plating process is copper. The method of claim 1, wherein the bottom of the hole is non-conductive. The method of claim 1, wherein the surface of the printed circuit board is non-conductive. A manufacturing method for wiring and interlayer conduction of a printed circuit board comprises the following steps: A. providing a printed circuit board having an insulating layer on the surface thereof having at least one hole having a diameter of 10 um to 300 um, the aspect ratio of which is 0.2:1. 2:1, and at least one line groove with a width of 5um-200um, the width-to-depth ratio is 0.5:1-10:1, and the wall of the hole and the channel groove are non-conductive; B. in the hole and the line groove The surface of the substrate other than the groove is covered with a plating resist; C. modifying a conductive layer of reduced graphene oxide (rGO) on the wall of the hole and the groove of the line, comprising the following steps: (i) immersing the substrate in a solution of Polyvinylimidazole (PVI), a polymer layer is formed on the surface of the substrate and the inner wall of the hole, the pH is 3-6, the temperature is 40-80 ° C, and the time is 15-40 minutes; (ii) the substrate is immersed in an aqueous solution of graphene oxide (GO), a PVI layer adsorbed and bonded to the inner wall of the hole; (iii) reducing GO with a plasma of H _{2 to} form a rGO conductive layer; D. performing an electroplating process to bond the metal to the rGO conductive layer while depositing Holes and lines in the trench; E. Remove the plating resist. The method of claim 5, wherein the metal of the plating process is copper. The method of claim 5, wherein the holes and the bottom of the line trench are non-conductive. The method of claim 5, wherein the surface of the printed circuit board is non-conductive. The method of claim 5, wherein the plating resist of step B is an exposure developing type electroplating ink. A circuit and interlayer conduction structure of a printed circuit board, characterized in that: the line and the interlayer conduction structure are integrally formed, and a reduced graphene oxide (rGO) conductive layer is disposed between the printed circuit board; wherein the diameter of the interlayer conduction structure is 10um-300um, diameter to depth ratio is 0.2:1-2:1; line width is 5um-200um um, width to depth ratio is 0.5:1-10:1. The line and interlayer conduction structure of the printed circuit board of claim 10, wherein the corresponding wiring of the printed circuit board is provided with a trench, so that the rGO conductive layer is formed in the trench.