TWI628771B - Semiconductor element-mounted substrate - Google Patents

Abstract

The present invention provides a semiconductor element mounting substrate including: a circuit conductor disposed on an insulating substrate; a plurality of semiconductor element connection pads connected to the circuit conductor; and a semiconductor element mounted on the surface of the insulating substrate; the first capacitor and the first capacitor 2, the capacitor is disposed on the surface or inside of the insulating substrate; the first conductor path connects the first capacitor between the semiconductor element connection pads; and the second conductor path connects the second capacitor to the semiconductor element connection welding Between the disks, wherein the inductance of the first conductor path is smaller than the inductance of the second conductor path, and the capacitance of the first capacitor is smaller than the capacitance of the second capacitor and the internal inductance of the first capacitor is smaller than the second capacitor Internal inductance.

Description

Semiconductor component mounting substrate

The present invention relates to a semiconductor element mounting substrate including a plurality of capacitors.

In recent years, in the development of high-performance and miniaturization of electronic devices represented by portable game machines and communication devices, the semiconductor element mounting substrates used for such devices have been required to be highly functional and miniaturized. Therefore, for a semiconductor element in which the amount of arithmetic processing is increased, it is necessary to stably supply more current in a limited space.

In order to achieve these requirements, there is a semiconductor element mounting substrate in which a plurality of capacitors are built directly under the semiconductor element. A substrate in which such a capacitor is built is disclosed, for example, in Japanese Patent No. 4863546.

An object of the present invention is to provide a semiconductor element mounting substrate which can reduce the current fluctuation by suppressing the value of the impedance of the substrate, thereby enabling the electronic device to operate stably.

A semiconductor device mounting substrate according to an embodiment of the present invention includes: an insulating substrate having a laminated structure in which a plurality of insulating layers are laminated; a circuit conductor disposed on a surface and inside of the insulating substrate; and a plurality of semiconductors The element connection pad is disposed on the surface of the insulating substrate and connected to a part of the circuit conductor; the semiconductor element is mounted on the surface of the insulating substrate via the semiconductor element connection pad; the first capacitor and the second capacitor are matched Provided on a surface or inside of the insulating substrate; and the first conductor path and the second conductor path include a part of the circuit conductor, and the first conductor path electrically connects the first capacitor between the predetermined semiconductor element connection pads. a second conductor path electrically connecting the second capacitor between the predetermined semiconductor element connection pads, wherein an inductance of the first conductor path is smaller than an inductance of the second conductor path, and the first capacitor The capacitance is smaller than the capacitance of the second capacitor and the internal inductance of the first capacitor is smaller than the internal inductance of the second capacitor.

1‧‧‧Insert substrate

1a‧‧‧Insulation

1b‧‧‧Insulation

2‧‧‧Circuit conductor

3‧‧‧Semiconductor component connection pads

4‧‧‧External connection pads

5‧‧‧1st capacitor

5t‧‧‧electrode

6‧‧‧2nd capacitor

6t‧‧‧electrode

7‧‧‧ recess

8‧‧‧ recess

9‧‧‧through hole

10‧‧‧through hole

11‧‧‧Perforation

12‧‧‧ solder mask

12a‧‧‧ openings

12b‧‧‧ openings

A‧‧‧Substrate

B‧‧‧ solder bumps

S‧‧‧Semiconductor components

Fig. 1 is a schematic cross-sectional view showing an example of an embodiment of a semiconductor element mounting substrate of the present invention.

First, an example of the semiconductor element mounting substrate A of the present invention will be described based on Fig. 1 .

The wiring board A includes an insulating substrate 1, a circuit conductor 2, a semiconductor element connection pad 3, an external connection pad 4, a semiconductor element S, a first capacitor 5, and a second capacitor 6.

The semiconductor element mounting substrate A includes an insulating substrate 1 formed as an insulating layer 1b for building up and down on the upper and lower surfaces of the insulating layer 1a for the core, and a circuit conductor 2 disposed on the insulating substrate. The surface and the inside of the board 1 are provided; the plurality of semiconductor element connection pads 3 are disposed on the surface of the insulating substrate 1 and connected to a part of the circuit conductor 2; and the semiconductor element S is mounted on the semiconductor element connection pad 3 via the semiconductor element The surface of the insulating substrate 1 and the first capacitor 5 and the second capacitor 6 are built in the insulating substrate 1.

The first capacitor 5 is built in the upper side of the insulating substrate 1 on the side on which the semiconductor element S is mounted, and is electrically connected to the predetermined semiconductor element connection pad 3 via the first conductor path formed by a part of the circuit conductor 2 . between us.

The second capacitor 6 is built in the lower side of the first capacitor 5 in the insulating substrate 1, and is electrically connected to the predetermined semiconductor by a second conductor path formed by a part of the circuit conductor 2 and longer than the length of the first conductor path. The component connection pads 3 are between each other.

In this way, the first and second capacitors 5 and 6 built in the insulating substrate 1 directly under the semiconductor element S are connected in parallel to the semiconductor element S via the first and second conductor paths, thereby forming the semiconductor element. S is a structure that supplies more current.

In order to stably supply a current to the semiconductor element S, it is important that the sum of the capacitance of the first capacitor 5 and the capacitance of the second capacitor 6 is sufficiently large, and the internal inductance of the first capacitor 5 and the first conductor path are made. At least one of the sum of the inductances and the sum of the internal inductance of the second capacitor 6 and the inductance of the second conductor path is as small as possible, and the impedance value of the entire conductor path is suppressed.

The insulating substrate 1 is formed as an insulating layer 1a for the core The upper and lower surface areas are laminated with an insulating layer 1b for lamination.

Each of the insulating layers 1a and 1b contains a thermosetting resin such as an epoxy resin or a Bismaleimide-Triazine Resin.

A recess 7 is formed in a central portion of the upper surface of the insulating layer 1a for the core. A recess 8 is formed in a central portion of the lower surface of the insulating layer 1a for the core. These recesses 7, 8 are formed, for example, by sandblasting or laser processing.

The first capacitor 5 is placed on the recess 7. In addition, the first capacitor 5 is fixed in the recess 7 by filling the gap between the recess 7 and the first capacitor 5 by laminating the insulating layer 1b on the upper surface area of the insulating layer 1a for the core.

The second capacitor 6 is placed on the recess 8 . Then, the second capacitor 6 is fixed in the recess 8 by filling the gap between the recess 8 and the second capacitor 6 by laminating the insulating layer 1b disposed on the lower surface area of the insulating layer 1a for the core.

On the upper side of the insulating substrate 1, a plurality of through holes 9 having the electrode 5t of the first capacitor as a bottom surface are provided. On the lower side of the insulating substrate 1, a plurality of through holes 10 having the electrode 6t of the second capacitor as a bottom surface are provided. The through holes 9 and 10 have a diameter of about 20 to 100 μm and are formed by, for example, laser processing.

The insulating substrate 1 has a plurality of through holes 11 penetrating the upper and lower sides. The perforation 11 has a diameter of about 50 to 300 μm and is formed by, for example, drilling.

The circuit conductor 2 is formed in the upper and lower surfaces of the insulating substrate 1 and in the through holes 9, 10 and in the through holes 11. The circuit conductor 2 formed in the through hole 9 is connected to the electrode 5t of the first capacitor. The circuit conductor 2 formed in the through hole 10 is connected to the electrode 6t of the second capacitor.

The circuit conductors 2 formed in the through holes 11 electrically connect the circuit conductors 2 on the upper and lower surfaces of the insulating substrate 1 to each other.

The circuit conductor 2 is formed by, for example, a conventional semi-additive method or a subtractive method using a good conductive metal such as copper plating.

The semiconductor element connection pad 3 includes a part of the circuit conductor 2 formed on the upper surface of the insulating substrate 1. The semiconductor element connection pad 3 is exposed in the opening 12a, and the opening 12a is provided on the solder resist layer 12 which is provided on the upper surface of the insulating substrate 1.

The external connection pad 4 includes a part of the circuit conductor 2 formed on the lower surface of the insulating substrate 1. The external connection pads 4 are exposed in the opening 12b, and the openings 12b are provided on the solder resist layer 12 which is provided on the lower surface of the insulating substrate 1.

The semiconductor element S can be formed, for example, of a microprocessor or a semiconductor memory, and is formed of ruthenium, iridium or the like. The electrode of the semiconductor element S is connected to the semiconductor element connection pad 3 via solder bumps B, for example.

The first capacitor 5 and the second capacitor 6 are formed, for example, by alternately laminating a ceramic-containing dielectric body and a copper-containing electrode. The first and second capacitors 5 and 6 have electrodes 5t and 6t at two positions on the outermost layer.

The capacitance of the second capacitor 6 is larger than the capacitance of the first capacitor 5, and more current can be supplied to the semiconductor element S. On the other hand, the internal inductance of the first capacitor 5 is smaller than the internal inductance of the second capacitor 6, which is advantageous in reducing the impedance of the current supply path.

The first capacitor 5 is connected to the semiconductor element connection pad 3 and passes through the first lead including the circuit conductor 2 formed in the through hole 9. The body path is electrically connected to the semiconductor element S.

The second capacitor 6 is connected to the semiconductor element connection pad 3 and passes through the second conductor path including the circuit conductor 2 formed in the upper and lower surfaces of the insulating substrate 1 and the through hole 11 and in the via hole 10, and the semiconductor element S. Electrical connection.

As described above, since the length of the first conductor path is shorter than the length of the second conductor path, the inductance of the first conductor path is smaller than the inductance of the second conductor path.

In the conventional semiconductor element mounting substrate having a plurality of conductor paths, for example, when the second conductor path length is longer than the first conductor path length, the inductance of the second conductor path may be larger than the inductance of the first conductor path.

Therefore, if the internal inductance of the first capacitor 5 connected to the first conductor path and the internal inductance of the second capacitor 6 connected to the second conductor path are not considered, the impedance value of the entire conductor path cannot be suppressed, so that the current is suppressed. The change becomes larger. As a result, the electronic device may not be able to operate stably.

On the other hand, in the semiconductor element mounting substrate A of the present invention, the first capacitor 5 having a smaller internal inductance than the second capacitor 6 is connected to the first conductor path having a smaller inductance. Thereby, it is possible to secure a path having a smaller inductance component and suppress the impedance value of the entire conductor path.

Further, by setting the capacitance of the second capacitor 6 connected to the second conductor path to be larger than the capacitance of the first capacitor 5, the sum of the capacitance of the first capacitor 5 and the capacitance of the second capacitor 6 can be sufficiently increased.

As a result, it is possible to supply the semiconductor element S with a suppressed current fluctuation. More current. Therefore, it is possible to provide the semiconductor element mounting substrate A which can stably operate the electronic device.

Claims (2)

A semiconductor element mounting substrate includes: an insulating substrate having a laminated structure in which a plurality of insulating layers are laminated; a circuit conductor disposed on a surface and inside of the insulating substrate; and a plurality of semiconductor element connection pads disposed in the substrate a surface of the insulating substrate is connected to a part of the circuit conductor; a semiconductor element is mounted on a surface of the insulating substrate via the semiconductor element connection pad; and a first capacitor and a second capacitor, the first capacitor The second capacitor is disposed below the first capacitor, and the first conductor path and the second conductor path include a part of the circuit conductor. The first conductor path electrically connects the first capacitor between predetermined semiconductor element connection pads, and the second conductor path electrically connects the second capacitor and the first capacitor in parallel Between the predetermined semiconductor element connection pads, the inductance of the first conductor path is smaller than the inductance of the second conductor path, and the capacitance of the first capacitor It is smaller than the capacitance of the second capacitor and the first capacitor internal inductance is less than the internal inductance of the second capacitor. The semiconductor element mounting substrate according to the first aspect of the invention, wherein the length of the first conductor path is shorter than the length of the second conductor path.