TWI628769B - Semiconductor component and method of forming same - Google Patents

Abstract

A semiconductor device comprising: a plurality of pads on an active surface of a semiconductor wafer, a first protective layer covering a portion of the active surface of the semiconductor wafer, and exposing a surface of each of the pads, the first bump The lower metal is disposed on the portion of the first protective layer and covers the surface of each of the pads, the reconfigurable layer is disposed on the underlying metal layer of the first bump, and the metal layer of the second bump is disposed on the partially reconfigured layer. And exposing a part of the surface of the reconfigurable layer, the second protective layer is disposed on a surface of the semiconductor wafer, the underlying metal layer of the second bump, and a portion of the reconfigured layer, and the metal wire is disposed besides the bonding pad On a portion of the surface exposed by the second under bump metal layer, the second under bump metal layer can be supported by the line width and spacing of the reconfigured layer to increase the reliability of the semiconductor device.

Description

Semiconductor component and method of forming same

The present invention provides a semiconductor device, and more particularly to a semiconductor device having a repositioning layer having a good pitch and a line width and a method of forming the same.

With the advancement of semiconductor process technology and the continuous improvement of the functions of the chip circuit, the integrated circuit (IC) can be reduced with the growth of various portable products such as communication, network and computer, and market demand. Semiconductor package technologies such as ball grid array (BGA), flip chip and chip size package (CGA) with high density and pinning characteristics are currently well-known mainstream technology.

However, as the integrated circuit process is increasingly miniaturized, and the transmission rate and structural reliability are emphasized, the pitch of the wafer contacts is bound to be smaller than that of the solder bumps under the trend of wafer-level wafer size packaging. Dimensions, which cause problems in which adjacent solder bumps are in contact with each other.

Although a reconfiguration layer (RDL) has been developed in the future to overcome the above problems. The via line is formed using the reconfiguration layer and reconfigured to the appropriate location to form an under bump metallization (UBM) such that there is an appropriate spacing between adjacent solder bumps.

However, the reconfiguration layer used in the prior art as a conduction line is a copper/nickel/gold (Cu/Ni/Au) structure, and after etching, the under-clad metal under the re-configuration layer is caused by the etching ratio. The layer of copper and titanium produces an undercut effect due to the etching selectivity ratio, making the entire The support points below the reconfiguration layer are insufficient, and the reconfiguration layer is relatively easy to dump, causing the structure of the entire semiconductor element to collapse.

In order to solve the shortcomings of the prior art, the main object of the present invention is to provide a semiconductor component having a good pitch and line width reconfiguration layer, wherein the reconfiguration layer is pure copper, and therefore, after the reconfiguration layer is subjected to the etching step The pitch or line width of the under bump metal layer (UBM) under the reconfiguration layer is not reduced by the undercut effect, and the support layer can still be given sufficient support force to make the entire semiconductor component have good integrity. And reliability.

According to the above objective, the present invention discloses a semiconductor device, the structure comprising: a semiconductor wafer, the active surface on the semiconductor wafer has a plurality of pads, and the first protective layer covers a portion of the active surface of the semiconductor wafer, and Exposing the surface of each of the pads, the first under bump metal is disposed on a portion of the first protective layer and covering the surface of each of the pads, and the reconfigurable layer is disposed on the underlying metal layer of the first bump, The under bump metal layer is disposed on the partial relocation layer and exposes a portion of the surface of the relocation layer, the second protective layer is disposed on a portion of the surface of the semiconductor wafer, and a portion of the second bump under the metal And a layer disposed on a surface exposed on the reconfiguration layer, the metal wire being disposed on a surface exposed by the metal layer under the second bump except the pad, whereby one end of the metal wire is transmitted through the second protrusion The under-metal layer, the re-arrangement layer and the first under bump metal layer are electrically connected to the pads on the semiconductor wafer, and the other end can be electrically connected to other components.

10‧‧‧Semiconductor wafer

102‧‧‧ solder pads

20‧‧‧First protective layer

30‧‧‧First under bump metal layer

40‧‧‧First photoresist layer

50‧‧‧Reconfiguration layer

60‧‧‧second photoresist layer

70‧‧‧Second bump under metal layer

80‧‧‧Second protective layer

90‧‧‧Metal wire

104‧‧‧Wire soldering pad

1 is a cross-sectional view showing the formation of a first under bump metal layer and a first photoresist layer on a semiconductor wafer having a plurality of pads according to the disclosed technology; 2 is a schematic cross-sectional view showing formation of a reconfiguration layer on a first under bump metal layer after photolithographic etching of a first photoresist layer in accordance with the disclosed technology; FIG. 3 is a technique in accordance with the present invention. , after removing a portion of the first photoresist layer remaining on the metal layer under the first bump in FIG. 2, forming a second photoresist layer having a plurality of second opening patterns under the first bump a partial surface of the metal layer and a schematic cross-sectional view disposed on the reconfiguration layer; FIG. 4 is a view showing a second lithography process performed on the second photoresist layer having a plurality of second opening patterns according to the disclosed technology FIG. 5 is a cross-sectional view showing a portion of a surface of a re-arrangement layer exposed; FIG. 5 is a cross-sectional view showing a second photo-resist layer as a photomask and a second sub-bump metal layer on the re-disposing layer according to the disclosed technology. FIG. 6 is a view showing the technique of the present invention, in which the second photoresist layer of FIG. 5 is removed to expose a portion of the surface of the underlying metal layer of the first bump, and the metal layer of the first bump is removed. Etching to expose a portion of the surface of the first protective layer FIG. 7 is a schematic cross-sectional view showing the formation of a second protective layer on the structure of FIG. 6 according to the disclosed technology; FIG. 8 is a view showing the lithography of the second protective layer according to the disclosed technology. A schematic cross-sectional view of a portion of the surface of the metal layer under the second bump is exposed; and FIG. 9 is a schematic cross-sectional view showing the formation of a metal wire on the dashed area of FIG. 8 in accordance with the disclosed technology.

First, please refer to Figure 1. 1 is a schematic cross-sectional view showing a semiconductor device disclosed in the present invention. In FIG. 1, a semiconductor wafer 10 is used as a substrate, wherein a plurality of wafers (not shown) are disposed on the semiconductor wafer 10, and each wafer has an active surface (not shown in the figure). And the back side (not shown in the figure), and configured on the active surface of each wafer (not shown in the figure) Pads 102. It should be noted that, in the present invention, the arrangement positions of the pads 102 on the wafer are not limited. Therefore, the pads 102 may be disposed at an intermediate position of the active surface of the wafer, and the four sides of the active surface of the wafer or It can be an embodiment of the present invention on either side of the active surface of the wafer, and is not limited herein. In addition, the manufacturing process of the semiconductor wafer 10 as a substrate is a semiconductor process technology well known in the semiconductor technology field, and the process flow and the material constituting the semiconductor wafer 10 are not in the technical solution to be discussed in the present invention, so statement.

Please continue to refer to Figure 1. A first protective layer 20 is formed on the semiconductor wafer 10, and the first protective layer 20 covers a plurality of pads 102 on each of the wafers of the semiconductor wafer 10. Next, a first lithography process is performed on the first protective layer 20 such that a plurality of first openings (not shown) are formed in the first protective layer 20, and the first openings are disposed on the semiconductor wafer A plurality of pads 102 on each of the wafers 10 are exposed. In an embodiment of the present invention, the method of forming the first protective layer 20 on the semiconductor wafer 10 may be performed by deposition, such as chemical vapor deposition (CVD), atmospheric pressure chemical vapor deposition. (APCVD, atmospheric pressure CVD) or low pressure chemical vapor deposition (LPCVD). In addition, the material of the first protective layer 20 may be a polymer material such as polyimide (PI) or epoxy.

Next, an under bump metallization 30 is formed on the first protective layer 20 and covers the exposed surface of the plurality of pads 102. In the embodiment of the present invention, the first under bump metal layer 30 is formed on the surface of the first protective layer 20 and the plurality of pads 102 by sputtering, wherein the first protective layer 20 and The first under bump metal layer 30 on the surface of the plurality of pads 102 is formed to have a thickness of 0.05 um - 1 um. Further, the material of the first under bump metal layer 30 is titanium/copper (Ti/Cu). Then, a first photoresist layer 40 having a plurality of first opening patterns (not shown in the drawing) is formed on the first under bump metal layer 30.

Next, please refer to Figure 2. 2 is a schematic cross-sectional view showing the formation of a relocation layer on the first under bump metal layer after the first photoresist layer is lithographically etched. In FIG. 2, a first lithography process is performed on the first photoresist layer 40 having a plurality of first opening patterns (not shown in FIG. 1) in FIG. 1 to remove the underlying metal layer 30 overlying the first bumps. The upper portion of the first photoresist layer 40 retains a portion of the first photoresist layer 40 that has undergone the first lithography process and exposes the surface of the first under bump metal layer 30.

Please continue to refer to Figure 2. The first photoresist layer 40 remaining on the first under bump metal layer 30 is used as a mask, and a metal such as pure copper, which is a redistribution layer (RDL), is formed on the first bump. On the under-metal layer 30, wherein the method of forming the re-configuration layer 50 on the first under bump metal layer 30 is achieved by means of plating, and the re-configuration layer 50 is formed under the first bump metal The thickness above layer 30 is 1 um - 10 um and the width is 1 um - 200 um.

Next, please refer to FIG. 3 and FIG. 4 at the same time. 3 shows a second photoresist layer having a plurality of second opening patterns formed on the first bump after removing a portion of the first photoresist layer remaining on the lower metal layer of the first bump in FIG. A portion of the surface of the lower metal layer and a second photoresist layer having a plurality of second opening patterns are disposed in a cross-sectional view of the reconfiguration layer. 4 shows a schematic diagram of performing a second lithography process on a second photoresist layer having a plurality of second opening patterns. In FIG. 3, a portion of the first photoresist layer 40 remaining on the first under bump metal layer 30 is removed in FIG. 2 to expose a portion of the first under bump metal layer 30. The surface and the surface of the reconfiguration layer 50 are exposed. Next, a second photoresist layer 60 having a plurality of second opening patterns (not shown) is formed on a portion of the exposed surface of the first under bump metal layer 30, and overlying the reconfigured layer 50. on the surface. Next, as shown in FIG. 4, a second lithography process is performed on the second photoresist layer 60 having a plurality of second opening patterns to remove a portion of the second photoresist layer 60 overlying the reconfiguration layer 50. And retaining a portion of the surface of the first under bump metal layer 30 and a portion of the second photoresist layer 60 on the relocation layer 50, such that A plurality of second openings (not shown) are formed in the second photoresist layer 60, and the second openings expose portions of the surface of the relocation layer 50.

Next, please refer to Figure 5. FIG. 5 is a schematic cross-sectional view showing the second under-baked metal layer formed on the re-disposing layer with the second photoresist layer as a mask. In FIG. 5, the second photoresist layer 60 remaining on a portion of the surface of the first under bump metal layer 30 and a portion of the second photoresist layer 60 on the relocation layer 50 are used as a mask. The second under bump metal layer 70 is formed on the relocation layer 50, wherein the method of forming the second under bump metal layer 70 on the relocation layer 50 is achieved by electroplating and is formed on the reconfiguration layer The second under bump metal layer 70 above 50 has a thickness of 1 um - 10 um and a width of 1 um - 200 um. In the embodiment of the present invention, the material of the second under bump metal layer 70 is nickel / gold (Ni / Au ).

Please refer to Figure 6 below. FIG. 6 is a schematic cross-sectional view showing the second photoresist layer of FIG. 5 removed and the first under bump metal layer being etched. In FIG. 6, a portion of the second photoresist layer 60 on the first under bump metal layer 30 and the relocation layer 50 in FIG. 5 is removed, so that a part of the surface of the first under bump metal layer 30 and A portion of the surface of the reconfiguration layer 50 is exposed. Then, a portion of the first under bump metal layer 30 on the first protective layer 20 is removed by etching, such as dry etching, to expose the surface of the first protective layer 20. Here, the etched first under bump metal layer 30 has a width of 1 um to 200 um.

Next, please refer to FIG. 7 and FIG. 8 at the same time. Fig. 7 is a schematic cross-sectional view showing the formation of a second protective layer on the structure of Fig. 6. Figure 8 is a cross-sectional view showing the lithography process performed on the second protective layer to expose the underlying metal under bump. In FIG. 7, the second protective layer 80 covers the first protective layer 20, a portion of the surface of the first under bump metal layer 30, a portion of the surface of the reconfigurable layer 50, and a second bump under deposition. Metal layer 70. In the present invention, the second protective layer 80 is formed on the first protective layer 20, a portion of the surface of the first under bump metal layer 30, a portion of the surface of the relocation layer 50, and the second under bump metal layer 70. The method can also be accomplished by means of deposition, such as chemical vapor deposition. CVD, chemical pressure CVD or low pressure CVD. In addition, the material of the second protective layer 80 may also be a polymer material such as polyimide (PI) or epoxy.

Then please refer to Figure 8. A lithography process is performed on the second protective layer 80 to remove a portion of the second protective layer 80 and expose a portion of the surface of the second under bump metal layer 70. It should be noted that, in the right side view of FIG. 8 , that is, the area of the broken line in FIG. 8 , the structure formed by the first under bump metal layer 30 and the rearrangement layer 50 can be regarded as forming a metal wire 90 subsequently. A wire bonding pad 104 (shown in Figure 9). In the present invention, when pure copper is used as the material of the relocation layer 50, when the second under bump metal layer 70 is etched, the relocation layer under the second bump under the metal layer 70 is caused by the etching selection ratio factor. The line width and spacing of 50 is wider than that of the prior art reconfigurable layer material (Ti/Cu). Since the undercut line width is less than that of the prior art, the pure copper-based reconfiguration layer 50 is the upper one. The two-bump metal layer 70 can provide better support capability, so that the entire structure does not fall or collapse due to insufficient underlying support force, thereby improving the yield and reliability of the semiconductor device.

In addition, in the embodiment of the present invention, the second under bump metal layer 70 and the relocation layer 50 are covered by a portion of the second protective layer 80, and the reconditioning layer 50 and the second layer 80 may be added by the second protective layer 80. The reliability of the under bump metal layer 70 prevents leakage current generation and improves the yield of the semiconductor device.

Please refer to Figure 9 immediately. Fig. 9 is a schematic cross-sectional view showing the formation of a metal wire in the dotted line region of Fig. 8. In FIG. 9, a metal wire 90 is formed on a surface exposed by the second under bump metal layer 70 except for the plurality of pads 102 by a general wire bonding process, whereby the metal wires 90 are transmitted through Second bump under metal layer 70, relocation layer 50 and first bump under metal The layer 30 is electrically connected to the pad 102 on the semiconductor wafer 10. In the embodiment of the invention, the metal wire 90 may be copper, titanium, tungsten or gold.

By using copper as the reconfiguration layer 50 as disclosed in the present invention, the problem that the reconfiguration layer 50 is tilted due to insufficient line width is improved, since the line width of the metal layer 30 under the first bump below the relocation layer 50 is 4 um. The line width is greater than the line width of the first under bump metal layer under the reconfiguration layer of the prior art is 3 um or even less than 3 um, and the line width of the reconfiguration layer 50 is 5 um-6 um. It is said that in the prior art, since the line width of the first under bump metal 30 under the reconfiguration layer 50 cannot provide sufficient supporting force for the upper structure, the entire structure is dumped or collapsed. Therefore, according to the technology disclosed in the present invention, pure copper is used as the material of the reconfiguration layer 50, which can reduce the undercut effect on the underlying metal layer under the re-distribution layer during the etching process, and further Providing a better line width improves the reliability and yield of the entire semiconductor component.

Claims (9)

A semiconductor device comprising: a semiconductor wafer having a plurality of pads on an active surface; a first protective layer covering a portion of the active surface of the semiconductor wafer and exposing each of the semiconductor wafers a surface of the first pad; a first under bump metal layer disposed on a portion of the first protective layer and covering the surface of each of the pads; a reconfigurable layer disposed under the first bump a second under bump metal layer disposed on a portion of the reconfigured layer and exposing a portion of the surface of the reconfigured layer; a second protective layer disposed on the portion of the semiconductor wafer The surface, a portion of the surface of the second under bump metal layer, and a portion of the surface on which the relocation layer is exposed; and a plurality of metal wires disposed on the second bump except the pads a portion of the surface exposed by the underlying metal layer, wherein the metal wires pass through the second under bump metal layer, the reconfigured layer, and the first under bump metal layer and the pads are electrically connection. The semiconductor device according to claim 1, wherein the first under bump metal layer is titanium/copper (Ti/Cu). The semiconductor device according to claim 1, wherein the relocation layer is copper (Cu). The semiconductor device according to claim 1, wherein the second under bump metal layer is nickel/gold (Ni/Au). The semiconductor device according to claim 1, wherein the first protective layer and the second protective layer are a polyimide resin or an epoxy resin (Epoxy). The semiconductor device of claim 1, wherein a line width of the second under bump metal layer, the rearrangement layer, and the first under bump metal layer other than the pads is 6 um, respectively. 4um and 3um. The semiconductor device according to claim 1, wherein the metal wire is copper, titanium, tungsten or gold. The semiconductor device according to claim 1, wherein the forming the first under bump metal layer is achieved by sputtering. The semiconductor device according to claim 1, wherein the forming the rearrangement layer and the second under bump metal layer are achieved by plating.